INTEGRATION OF AN IMPROVED HARVESTER-ON-CHIP CORE DICE ON
COMMERCIAL SOI-BASED MEMS TECHNOLOGY
G. Murillo1*, J. Agustí1, G. Abadal1, F. Torres1, J. Giner1, E. Marigó1, A. Uranga1, N. Barniol1
1
Dept. Enginyeria Electrònica, Universitat Autònoma de Barcelona, 08193-Bellaterra, Spain
Abstract: This work presents the design of the fully-dedicated core dice of an energy harvester-on-chip (HoC)
with electrostatic transduction. The core dice has been fabricated by using a SOI-BASED MEMS technology
which allows us to fix the problems found in the first prototype. The main highlights of this design are the use of
ARCHITECH® software, which offers us the possibility of carrying out a parametric design by defining
hierarchical blocks, and the advantage of using a SOI silicon layer of 60 μm to fabricate the mechanical
suspensions, which increases the robustness and performance of the design. Simulations have been performed in
order to validate the final design. Finally, several attempts of assembling the core dice together with a support
substrate, by using an ad-hoc bonding technique, have been carrying out.
Keywords: Harvester-on-Chip, Energy Scavenging, Silicon-over-Insulator, Electrostatic Transduction
allows us to use a 60 μm silicon layer to build our
fingers and suspensions. This change is translated into
an improvement of the resonance movement direction
selectivity and an increase of more than one order of
magnitude in the transduction density.
INTRODUCTION
The basic ideas of the concept of HoC are the use
of the whole chip as inertial mass of a damped springmass system, and the micromachinable area to define
the transduction and anchored parts. The first HoC
prototype, which was just a proof-of-concept, was
introduced in a previous work [1] and it was
fabricated in a CMOS technology. In this case, the
core dice has been fabricated by using a SOI-BASED
MEMS technology which allows us to fix the
problems found in the first prototype. For this design,
we have used of ARCHITECH® software, which
allow to perform parametric design by defining
hierarchical blocks.
IMPROVED DESIGN
This chip has been designed with the idea of
fixing the problems found in the first prototype of this
concept [1]. Several conclusions were extracted from
the last proof-of-concept prototype. First, there is a
trade-off between transduction area and stiffness loss
in each individual suspension, with its subsequent size
increase and worsening of the vibration direction
selectivity, when the cells number is increased.
Therefore, the idea of multi-cells, which was
introduced with the HoC concept, has to be changed,
by joining the cells, in order to decrease the
suspensions amount and increasing the number of
comb driver fingers and consequently the transduction
area. Secondly, the ratio between transduction area
and chip volume has to be improved by increasing the
comb-driver finger thickness. In order to overcome
these two challenges, we have changed from a
standard CMOS technology to a commercial SOIMEMS fabrication technology. The technology
selected was MEMSOI from Tronics®. This foundry
0-9743611-5-1/PMEMS2009/$20©2009TRF
Fig. 1: Parametric model of the whole chip and
detailed scavenging spine model.
Typically, the design process of a chip with these
features is a tedious work, where after the first design
several cycles of simulation-redesign have to be
carried out, with the consequence of an increase in
difficulty and design time. In this case, we have used
ARCHITECH® [2] to parametrically define the chip
elements and features and obtain useful simulation
results. The advantage of use this type of design
procedure is that this software can automatically
generate the final device layout. Once we have the
parametric scavenger model (see Fig. 1), we can
change dynamically parameters, such as comb-driver
beams number or the suspensions type, without
redrawing the design layout. Only the electrical
connection tracks and the test pads had to be manually
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PowerMEMS 2009, Washington DC, USA, December 1-4, 2009
driver is related to the finger width, wf, gaps number,
Ng, and distance between fingers, df.
drawn to complete the final chip layout (Fig. 2).
Ng =
L − wf
wf + d f
L>> w f
L
wf + d f
(4)
When this relationship is introduced in the
capacitance expressions for the designed IPGCT
scavenger, an analytical expression depending on the
design parameter can be obtained. A study of the
maximum reachable power related to the number and
separation of the beams has been performed.
Fig. 2: Layout of whole chip with four spines of
scavenging cells cross-connected.
-4
-5
-6
1
ΔU Q =cte = Vin2 rC ΔC
2
Power = ncycles ΔU cycle f
Power (W)
From the point of view of the transduction design,
this generator is enclosed into the electrostatic energy
harvesters. Specifically it is an in-plane gap closing
electrostatic transduction (IPGCT), formed with
several comb-drivers and designed to work in the
constant charge cycle [3, 4]. The most important
expressions for this type of generator are Eq. 1 and
Eq. 2. In order to increase the energy gain inside the
variable capacitor, ΔU, we should increase the
capacitance ratio, rC, or the capacitance difference,
ΔC, or the initial precharge voltage, Vin.
-8
-9
-10
-11
-12
15
20
10
15
10
5
z (μm)
5
df (μm)
Fig. 3: Ideal maximum reachable power depending on
initial adjacent fingers distance, df, and moved
distance, z.
(1)
(2)
As we can see in Fig. 3, the maximum reachable
power is almost independent of the fingers movement
at resonance and critically dependent on the minimum
gap between adjacent fingers. However, the longer
amplitude, the higher maximum voltage in the
variable capacitance (see Fig. 4)
Because of the independence of the resonant
amplitude and the throughput, the maximum allowed
displacement was set to 9 μm. This resonant
movement will be easier to reach than a larger one in
terms of energy. Therefore, any weak vibration
acceleration will be enough to carry out the energy
conversion and consequently the generator efficiency
will be improved.
But we have to take into account that with this
conversion cycle (where ncycles = 2) the maximum
reached voltage between the capacitor plates, Vmax,
depends on this capacitance ratio, rc, and the initial
voltage, Vin, as well.
Vmax = rCVin
-7
(3)
Since the maximum voltage is restricted by
technologic limitations, and the energy depends on the
square voltage, the parameter (among these three: Vin,
rc and ΔC) which should not be increased is rc. Thus,
we must find a design with a value of its medium
capacitance as large as possible and remaining the
ratio with a suitable value.
Moreover, we can take into account that we are
using comb drivers, where the length, L, of a comb
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this converter would be around 20 μW, i.e. 1.5
mW/cm3, for an acceleration magnitude of 0.4 m/s2,
an initial and final voltage of 10 V and 55 V
respectively, and an effective quality factor of 50
(electrical and mechanical damping effects).
Moreover, its required acceleration magnitude to
achieve the desired movement amplitude at resonance
is expected to be quite low. As it was commented in
[1], this chip has to be assembled with a support
substrate which allows its resonant movement..
120
Voltage (V)
100
80
60
40
20
15
10,0µ
20
10
235 Hz
15
10
z (μm)
5
x-axis direction
y-axis direction
z-axis direction
8,0µ
df (μm)
Amplitude (m)
5
Fig. 4: Maximum voltage depending on initial
adjacent fingers distance, df, and moved distance, z.
SIMULATIONS
Mechanical simulations of the whole anchored
chip have been performed (Fig. 5 and 6), defining in
the simulation environment a frequency sweep for a
three space-directions acceleration. The simulations
show that the first mode of resonance will be around
235 Hz for the desired movement direction. Nondesired movements have almost five times higher
resonant frequencies.
6,0µ
4,0µ
1190 Hz
1035 Hz
2,0µ
0,0
200
400
600
800
1000
1200
1400
1600
1800
2000
Frequency (Hz)
Fig. 6: Relative displacement in three space
directions. First mode frequency in the desired
movement direction is about 235 Hz.
WHOLE GENERATOR FABRICATION
In order to obtain a whole functional generator,
we need to follow the next fabrication process:
• Fabrication of scavenger core die.
• Creation of support substrate.
• Assembling of both parts
As mentioned previously, the core dice has been
fabricated by using a SOI-BASED MEMS technology
(Fig. 7).
Fig. 5: 3D solid model of the chip together with view
of packed chip with pad windows and simulated
suspensions detail.
From the designed chip, maximum and minimum
capacitance values of 178 pF and 32 pF respectively
could be reached, which means a capacitance ratio of
5.5 and a capacitance difference of 146 pF. The
maximum power which could be ideally obtained with
Fig. 7: SEM images of fabricated chip before
encapsulation.
235
conductive adhesive are going to be used in upcoming
approaches.
In order to performance the first test for the HoC a
simple PCB layout was designed to allow the physical
support and electrical connection. The fabrication has
been carried out by using a circuit board plotter to
pattern on one side the tracks to electrically connect
the total variable capacitance to the external control
and power management circuits, and on the other side
the support pillars. These columns have to be raised in
order to allow mounting the chip on top of them and
the HoC resonant movement by means of avoiding the
contact between both surfaces. The PCB fabrication
process includes the patterning of the tracks in the
PCB back-side and the contact pads in the front-side.
Then a layer of more than 300 µm, which is the
thickness of the lid fabricated chip, has to be removed
in order to obtain the support pillars. Finally, a hole
through each PAD has to be drilled and filled with
conductive paste to create a via between pillar and
track.
A first assembling test, without vias and
consequently without electrical connection, has been
carried out by using a small piece of silicon wafer and
one fabricated chip (see Fig. 8). In order to perform
the bonding, Chemtronics CW2400, a two part silver
loaded conductive epoxy that cures at room
temperature, has been used. Alignment was carried
out with a component alignment system (ERSA PL
550) which allows us to place precisely the HoC
above the PCB substrate, and match the PCB pillars
with the chip pads.
(a)
(b)
(d)
(c)
(e)
Fig. 9: ERSA PL 550 component alignment system
(a), view of PCB pillars and chip pad alignment t(b
and c), and lateral view of chip and PCB before (d)
and after (e) contact.
CONCLUSION
This work presents the design of a fullydedicated core dice of an energy harvester-on-chip
(HoC) with electrostatic transduction. A parametric
design has been developed by using ARCHITECH®
software. A SOI- based MEMS technology, which
allows robustness and better performance, has been
used instead of a commercial CMOS technology.
First assembling test between the HoC and a PCB
substrate has been successfully performed. Further
experimental characterizations have to be carried out
to demonstrate the correct working of the whole
assembled system. Maximum and minimum
capacitance, resonant frequency and resistance in the
HoC should be measured.
REFERENCES
[1]
Murillo G, Abadal G, Torres F, Lopez J L,
Giner J, Uranga A, Barniol N 2009 Harvesteron-Chip: Design of a Proof of Concept
Prototype Microelectronic Engineering 86
1183-1186
[2]
www.coventor.com, Coventor Website
[3]
Roundy S, Wright P K, Rabaey J M 2004
Energy Scavenging for Wireless Sensor
Networks: With Special Focus on Vibrations
[4]
Murillo G, Abadal G, Torres F, Lopez J L,
Giner J, Uranga A, Barniol N 2008 On the
Monolithic Integration of Cmos-Mems
Energy Scavengers 23rd Conference on
Design of Circuits and Integrated Systems
(DCIS) (Grenoble, France, 12-14 November
2008)
Fig. 8: Fabricated chip dedicated to energy
harvesting, first prototype of support PCB and first
test of pseudo flip-chip bonding of PCB and piece of
silicon wafer (from left to right).
Finally, Fig. 9 shows several images of procedure
steps, which obtains a successful assembling. In order
to develop a systematic procedure, and be able to
control the amount and the fine position of adhesive in
the PCB pads, a EFD ultra 2400 series, tips with a 200
nm of inner diameter and a new less viscous
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