www.nanocmos.ac.uk
Meeting the Design Challenges
of Nano-CMOS Electronics
eScience Pilot Project
Electronics and Physics Science Research Council (EPSRC)
£3.7M EPSRC
£4.4M FEC
£5.8M IC
A. Asenov (PI)
The University of Glasgow
11 PDRAs
7 Science
4 eScience
7 PhD
www.nanocmos.ac.uk
University Partners
Device Modelling Group (DMGUG)
National e-Science Centre (NeSCE)
Microsystems Technology Group (MSTGUG)
Advanced Processor Technologies Group (APTGUM)
e-Science NorthWest Centre (eSNW)
Mixed-Mode Design Group in IMNS (MMDGUE)
National e-Science Centre (NeSCG)
Electronic Systems Design Group (ESDGUS)
Intelligent Systems Group (ISGUY)
www.nanocmos.ac.uk
Industrial Partners
Global EDS vendor and world TCAD leader
600 licences for grid implementation, model implementation
UK fabless design company and world microprocessor leader
Core IP, simulation tools, staff time
UK fabless design company and world mixed mode leader
Additional PhD studentship for mixed mode design
Global semiconductor player with strong UK presence
Access to technology, device data, processing
Global semiconductor player with strong UK presence
Access to technology, device data, processing
Global semiconductor player with UK presence
CASE studentship, interconnects
Trade association of the microelectronics industry in the UK
Recruiting new industrial partners and dissemination
www.nanocmos.ac.uk
Summary
 Background
 Phase I
eScience
Science
 Phase II
 International impact
www.nanocmos.ac.uk
Summary
 Background
 Phase I
eScience
Science
 Phase II
 International impact
www.nanocmos.ac.uk
Variability is a showstopper
G. Declerck,
Keynote talk,
VLSI Technol.
Symp. 2005
Variability is the single most important CMOS technology
and design issue
www.nanocmos.ac.uk
Statistical variability dominates CMOS
Random Dopants
PolySilicon
Line Edge Roughness
σVT (VD = 50 mV)
σVT (VD = 1.0 V)
Random Dopants
39 mV
40 mV
Poly Silicon Pinning
26 mV
26 mV
Line Edge Roughness
16.8 mV
17 mV
Source
www.nanocmos.ac.uk
Impact of statistical variability on yield
1.8
Reference
System
1.6
Parametric Yield (perf
& energy) loss =
cost$$
1.4
1.2
Manufactured
System
1
0.8
0.6
0.4
0.4
Target
Energy
0.6
0.8
1
1.2
1.4
1.6
1.8
2
Critical path (normalized)
Target Cycle Time
Energy Normalized
Energy (normalized)
2
2
1.8
1.6
1.4
1.2
Stochastic
Time-dependent
variability
1
Design
centered for
time=t0
0.8
0.6
0.4
0.4
0.6
0.8
1
Critical Path (normalized)
1.2
1.4
1.6
1.8
Target cycle time
2
www.nanocmos.ac.uk
Objectives






Understanding and forecasting the behaviour, characteristics and
variability of next generation nano-CMOS devices using Grid-enabled
statistical 3D numerical simulations;
Developing compact model and parameter extraction strategies to capture
new device characteristics and variability (based on physical device
simulation and early research devices), creating efficient databases for
circuit design;
Developing hybrid, Grid based device/circuit simulation techniques
applicable to novel nano-CMOS devices with significant variability;
Investigating the impact of new device architectures and device variability
on well established design components, sub-systems and systems
presently designed using conventional MOSFET architectures;
Developing novel design concepts that cope with increased variability,
using specific properties of the new devices;
Learning how electronics researchers can use e-Science technologies to
support their work, improve their productivity and enable them to undertake
research hitherto impossible.
www.nanocmos.ac.uk
Grid based statistical simulation and verification
2
Energy (normalized)
The First Phase
1.8
Reference
System
1.6
Parametric Yield (perf
& energy) loss =
cost$$
1.4
1.2
Manufactured
System
1
0.8
0.6
0.4
0.4
Target
Energy
0.6
0.8
1
1.2
1.4
1.6
1.8
Critical path (normalized)
Target Cycle Time
2
www.nanocmos.ac.uk
Summary
 Background
 Phase I
eScience
Science
 Phase II
 International impact
www.nanocmos.ac.uk
Initial Proposed
E-Infrastructure
Components
Currently
Realised
E-Infrastructure
Components
Based on and Driven by Actual Science Need
Workflow Mgt Framework
Data Mgt Framework
Workflow Definition
Domain Knowledge Capture/Pres.
Robust Enactment
Data Access/Linkage/Integration
Dependency Mgt
Data Transformation
Job submission/mgt
Replication/Movement
Computational Steering
Metadata/Provenance
Visualisation Services
Storage/Curation Services
VERY LARGE SCALE
Optimised nanoCMOS Grid Infrastructure
Resource Mgt Framework
Advanced Security Framework
Accounting Components
Trust Federation
Information Services
Identity Management
Resource Broking Service
Security attributes definition
Meta-scheduling Services
Policy Decision/Enforcement Points
Reservation/Allocation Services
Attribute Request/Release Policies
Challenge
of scale of
number of
files
generated
and need
for fine
grained
security
www.nanocmos.ac.uk
nanoCMOS Job Submission & Mgt

OMII-UK and GridSAM & JSDL

Proof of concept systems for NGS, Condor, SGE clusters

However main resource available to us was ScotGrid

Primarily an EGEE/GridPP cluster – now integrated (partner) with NGS

gLite-wms-*, edg-job-*, lcg-job-*, globus-*, GANGA
www.nanocmos.ac.uk
nanoCMOS Data Mgt

OMII-UK and Data Mgt

Proof of concept systems using OGSA-DAI for data/meta-data mgt but real issue for
scientist was managing access to 100,000’s files generated from large scale simulations
AND

dealing with security of those files

Andrew File System (AFS)

Distributed file system

Stable (around since early 80’s)

Client-server model

AFS clients on main clusters (ScotGrid, most nodes of the NGS)

Runs on Windows, Macs, Linux-flavours, …

Users have access to familiar environments, e.g. cd, ls, cat, …

Key is that it supports

Fine grained security (through Kerberos)

Access Control Lists for groups, directories
www.nanocmos.ac.uk
nanoCMOS Security

Integration of variety of security technologies for complete end-end
security solution
GSI
Kerberos
VOMS

Portal level access and security through Shibboleth and SPAM-GP

Portlets for scoping, acceptance, configuration and authorisation of portal resources

Service level security through GSI, VOMS and PERMIS (via VPman)

First major test of latest OGF AuthZ standards for push/pull/use of attribute certificates

Data level security through Kerberos

Integrated with Grid/GSI-based security through gssklog

Cluster level security through GSI, VOMS, LCMAPS, LCAS

nanoCMOS VO registered on ScotGrid and on NGS VOMS servers
www.nanocmos.ac.uk
nanoCMOS e-Infrastructure Plans
 Moving up the electronics design space
Simulation, data, security frameworks designed to be generic with
(pluggable) components suitable for…



Device Simulation

Compact Model Extraction

Circuit Simulation

…
Next steps

Hardening of systems to support production level environment


Workflows, Computational Steering, Resource reservation/allocation…?
Perhaps, but…

Robust resource broking,

Robust meta-scheduling,
…almost
certainly!
www.nanocmos.ac.uk
Summary
 Background
 Phase I
eScience
Science
 Phase II
 International impact
www.nanocmos.ac.uk
The most comprehensive
technology available
VD = 50mV
VD = 1.0V
RDD+LER+PSG
Compact models
www.nanocmos.ac.uk
Meticulously calibrated to advanced CMOS
45nm LP technology
ST Microelectronics
1E-3
Ids (A/ m)
1E-5
1E-7
Results from Crolles 2
Results from Atomistic Simulator
1E-9
1E-11
0.0
0.2
0.4
0.6
Vgs (V)
B. Cheng
0.8
1.0
1.2
www.nanocmos.ac.uk
Excellent agreement with measurements
B. Cheng
www.nanocmos.ac.uk
Comprehensive evaluation of future technologies
25nm
35nm
18nm
13nm 9nm
Measured
TI
IBM
Fuj
Int
LER follows ITRS
LER=4nm
www.nanocmos.ac.uk
Ground breaking 100,000 3D simulations
24 CPU years
www.nanocmos.ac.uk
New level of understanding
www.nanocmos.ac.uk
For the first time, 3D MC
is used to simulate variability
C. Alexander
www.nanocmos.ac.uk
Ready to use compact models
Aurora
www.nanocmos.ac.uk
The Gold standard: 1,000,000 circuit simulations
To devise best statistical enhancement strategies
www.nanocmos.ac.uk
Summary
 Background
 Phase I
eScience
Science
 Phase II
 International impact
www.nanocmos.ac.uk
The second phase
The First Phase
www.nanocmos.ac.uk
VHDL-AMS Behavioural Modelling (Southempton)
1.5
1.5
VHDL-AMS Model, S Fitting
1.2
1.2
0.9
0.9
0.6
Output (V)
Output (V)
H-SPICE, INVERTER, LEVEL=13
Model: Boltzmann
1.2, 0.0, 0.5736, 0.029
0.3
0.3
0.0
0.6
0.0
10/0.05u,
Vth=+/-0.4~0.5V, Step=0.02V
-0.3
-0.3
0.0
0.3
0.6
Vth changing From 0.4 to 0.5V
0-500s
0.9
1.2
1.5
Input (V)
H-SPICE models:
Level=13, Vdd=1.2V,1.4E-9, 10/0.05
Behavioural modelling captures
analogue effects but with much
less computation
-0.3
-0.3
0.0
0.3
0.6
0.9
1.2
Input (V)
VHDL Model:
Vth=Vth0-0.05*now**0.25;
x0=0.478+0.199*abs(Vth);
dx=0.245-0.4426*abs(Vth);
Vout==1.2/(1.0+exp((Vinx0)/dx))
1.5
www.nanocmos.ac.uk
Statistical Static Timing Analysis (Southampton)

Netlist extraction generates Standard Delay
Format data, associated with Verilog netlist
 Can choose min, typ
 Global delay option

or max delays at runtime
For variability, we want local randomised delays
 Could generate random "typical" delay
 Need Vdd dependence
 Monte Carlo Simulation will be slow

Will develop SSTA
for each gate
www.nanocmos.ac.uk
Design for Variability - Motifs (Glasgow)
Variability in Motifs of Different Sizes
Parallel Configuration
No Resistance
With Resistance
Motifs
Series Configuration
No Resistance
Motif Library
With Resistance
www.nanocmos.ac.uk
Design for Variability - Motifs (Glasgow)
Uncommitted Logic Array of Motifs
• Currently and future work
includes;
NMOS Motifs
– Motifs as an alternative design
methodology.
Metal Interconnect
Metal Interconnect
– Uncommitted logic arrays
(ULAs).
– Integrating motifs with
evolutionary algorithms.
PMOS Motifs
Deconstruction
to Motif
based design
www.nanocmos.ac.uk
EAs to minimise variability (York)
Variability optimisation of
standard Cell Library (SCL)
– Transistor topology
– Transistor parameters e.g. widths
www.nanocmos.ac.uk
e.g. Power
EAs to minimise variability (York)
e.g. Delay
Standard cell
Power/Performance optimisation
www.nanocmos.ac.uk
Large-Scale Design Exemplars (Manchester)


SpiNNaker
– fault-tolerant architecture
for large-scale neural
modelling
Future work:
– explore impact of
variability on component
subsystem
– explore interaction
between fault-tolerance
and variability
www.nanocmos.ac.uk
Balsa: Design for Variability

Synthesis System for self-timed circuits
– correct behaviour despite variable delays
Future work:
– investigation of Motif back-end for DfM
– feasible because of minimal number cells required for
synthesis
80000
70000
60000
50000
40000
30000
20000
AN3EHD
OR2HHD
BUFMHD
AOI22EHD
AO12EHD
BUFNHD
BUFLHD
BUFKHD
BUFQHD
BUFJHD
ND3EHD
ND2HHD
AO22EHD
OR3EHD
NR3EHD
BUFHHD
NR2EHD
OR2EHD
AO222EHD
AN2EHD
0
INVHHD
10000
BUFEHD

www.nanocmos.ac.uk
Random Telegraph Signal (RTS) noise
Metal
K+
Na+
+ + +
- - -

+
Si02

+

+

+
Potential barrier
(source-drain)
Si
> 40% of drain current!!!
30  30 nm device
www.nanocmos.ac.uk
RTS as random noise in probabilistic architectures
h0
h1
h2
h3
h4
Example probabilistic architecture:
Continuous Restricted Boltzmann Machine
w34
v0
v1
v2
v3
Example subcircuit:
2-quadrant multiplier
System-level
S
Subcircuit-level
Noisy transistor
as basic unit
G
D
Device-level
Devise a methodology to perform transient analyses with RTS
www.nanocmos.ac.uk
Summary
 Background
 Phase I
eScience
Science
 Phase II
 International impact
www.nanocmos.ac.uk
International dissemination
www.nanocmos.ac.uk
www.nanocmos.ac.uk
www.nanocmos.ac.uk
Influencing the ENIAC agenda
www.nanocmos.ac.uk
SP7 fully aligned with NanoCMOS goals
Almost word by word copy from NanoCMOS