PRINCIPAL RESEARCH PROJECTS SUBMISSIONS - NANOCMOS
Please keep comments as succinct as possible and do not exceed 3 pages in total.
This form will be published on the EPSRC’s website as part of the publication of
evidence received by the panel.
Institution(s):
Universities of
Glasgow,
Edinburgh,
Manchester, York,
Southampton
Main Contact:
Prof. A. Asenov
Institute/ Group
Name:
Institute/ Group
Size (FTE)
Group webpage
Academic
http://www.elec.gla.ac.uk/groups/dev_mod/ Researchers 11
(FTE)
PG Students 15
(FTE)
Glasgow Device
Modelling Group
is the PI’s group
29
Lecturers 3
(FTE)
Strategic Vision Statement of e-Science research (200 words max.):
To develop a Grid-based infrastructure with associated technologies and
methods to support early evaluation of the impact of future CMOS devices
and their increasing variability on the design of present and next generation
circuits and systems. This will facilitate circuit and system design in the
presence of significant variability; allow migration to new device technologies
and encourage new design styles and solutions to cope with increased device
variability. This includes:
 Understanding and forecasting the behaviour, characteristics and
variability of next generation nano-CMOS devices, circuits and systems,
using Grid-enabled statistical 3D numerical simulations, statistical compact
models and statistical circuit simulation.
 Developing novel design concepts that cope with increased variability,
using specific properties of the new devices.
 Optimised and user friendly access and usage of high performance
distributed computing resources such as the National Grid Service (NGS),
ScotGrid and a range of HPC resources at partners sites, to support and
interlink statistical 3D device, circuit and mixed mode simulations, data
annotation and storage and fine-grained security according to IP concerns.
 Learning how electronics researchers can use e-Science technologies to
support their work, improve their productivity and enable them to
undertake research hitherto impossible.
Research Themes (the programme review structure is based on the
following themes. Please identify those relevant to your research
numbering them in order of priority. Please also give a brief summary of
your research focus in each theme and give the key lead contact(s)) (200
words max.):
1
Data and Information Management
2
Sharing and Collaboration
2
Distributed Research Infrastructures
1
Research Tools and Techniques
1
Physical Sciences and Engineering
Medicinal and Biological Sciences
Social Sciences, Arts and Humanities
Environmental Sciences
From the engineering point of view the statistical nature of intrinsic parameter
fluctuations creates new challenges for current electronics design and
simulation methodologies. A previously deterministic design process must
become statistical. For each individual gate shape, statistical simulations of a
large sample of microscopically different transistors must be carried out, and
3D device simulations become 4D. The engineering focus of the research is
advanced physical simulation of statistical variability in present and future
nano-CMOS devices; development of statistical compact model strategies
and statistical circuit simulation tools, and hierarchical circuit and systems
simulation and verification technology. The aim is to understand the impact of
statistical variability in the present CMOS technology generations and to
develop design techniques to cope better with the variability in future
technology generations.
The nature of this research demands access to and use of major HPC
computational resources, data and meta-data management, storage and
mining capabilities and user-driven support for fine grained security. The
associated e-Infrastructure that has been developed supports all of these
elements and has addressed the challenges in moving from simple “use” of
Grid into “production use” of Grid with support for bulk computational
simulations; management of terabytes of associated simulation data and
metadata, and robust and accepted security solutions.
Key Research Highlights over last ten years (these might include journal
papers, awards, patents, spinout activity, etc. Please be selective and
choose a top five similar to RAE).



Successful development, testing and adaptation of e-Science Grid-based
technologies for large-scale statistical device simulation and for statistical,
variability-aware circuit simulations. These include support for large-scale
bulk job submission; distributed data and meta-data management; finegrained user-driven security and applications-oriented annotation and
analysis.
The NanoCMOS project has led the development and the specification of
Grid security related to controlled exposure of industrially sensitive IP,
software licences and technology and device data. This includes the
integration of heterogeneous security solutions into a seamless integrated
framework and exploitation of recently published international Grid security
standards.
The Grid technology has allowed physical simulation of statistical
variability on an unprecedented scale including statistical samples of 105
transistors. This has never been undertaken before and has lead to radical
new insights into variability in the design process and established Glasgow
and NanoCMOS as a world leading authority in this area. The analysis of
the results also has allowed the development of statistical enhancement
techniques, which are adopted in practical simulation of statistical CMOS
variability.
 Increased coherence, cohesion and interaction between the device,
design and e-Science partners and wider industry. Through adopting a
strategy based on a hierarchical statistical simulation and verification of
individual IP blocks and SoC, nanoCMOS has made a marked contribution
to the increased interactions and alignment between the device and
design research communities in the UK and the UK design industry. This
was endorsed and prioritised at the EPSRC Electronics Theme Day on 20
May 2009.
 The NanoCMOS project has played a key role in the organisation of two
major International Conferences on CMOS Variability (ICCV1, ICCV2) in
London with speakers from Intel, IBM, Chartered, Altera, ARM, Synopsys,
Cadence and Mentor. This has raised the awareness of the variability
issues in design and the technology development by NanoCMOS and is
directly shaping industrial awareness of these issues.
Currently, 56 papers and 61 invited talks have been given by the NanoCMOS
consortium partners related to the NanoCMOS research. This include the
highly prestigious and competitive IEEE Transactions on Electron Devices (3
papers), Electron Device Letters (3 papers) and IEDM (3 papers), all of which
were enabled by the Grid infrastructure developed by NanoCMOS.
Key Research results taken up by industry and/or other users and/or
policy makers over the past ten years (please provide information about
the technologies and how they were adopted - 200 words max.).


The technology developed in NanoCMOS is widely used in two major
European projects REALITY and MODERN focused of the impact of
device variability on design. REALITY is an FP7 STREP (€2.9M) including
Glasgow, IMEC, ST Microelectronics and ARM. The ENIAC MODERN
project (€26M) has on board all major European semiconductor
manufacturing and design companies including ST Microelectronics,
Infineon and NXP. Glasgow will deliver all necessary simulations of
transistor variability based using the NanoCMOS technology. A new FP7
project TRAMS has been funded by the most recent FP7 call including
Intel.
Due to strong industrial demand a new company Gold Standard
Simulations (GSS) has been established by Glasgow University to
commercialise the 3D statistical simulation tools developed through the
NanoCMOS project
Graduate Student Research Training (Please provide brief details of type
of training provided, including current numbers of students as well as
trends over the last ten years, country of origin, gender and first
destination analysis).
The grant supports 7 PhD students. Another 12 PhD students conduct
research in the in related to NanoCMOS topics. All of PhD students receive
training at the interface between semiconductor devices and semiconductor
device modelling, circuit and system design and e-Science. This is done by
specialised training sessions and specific training courses run by the
individual partners.
Funding - Describe ongoing support for e-Science enabled research.
Please aggregate the data where possible (or please use HESA headings
– RC, other public funding etc.).
NanoCMOS enabled projects
Grant
FP7
EP/G04130
FP7 No. 216537
Fp7 No. 216171
GR/E038344/1
Name
TRAMS
ENIAC MODERN EPSRC contribution
REALITY
NANOSIL
Atomic Scale Simulation of Nanoelectronics Devices
Total
440000
727166
250039
76000
1218409
Key Collaborators (Academic and non academic, including overseas,
please provide details about main groups, countries and sources of
funding (200 words max.))
The industrial collaborators of NanoCMOS include:
Synopsys: Global EDS vendor and world TCAD leader - 600 licences for grid
implementation, model implementation
ARM: UK fabless design company and world microprocessor leader - Core IP,
simulation tools, staff time.
Wolfson Microelectonics: UK fabless design company and world mixed
mode leader – Additional PhD studentship for mixed mode design.
Freescale: Global semiconductor player with strong UK presence - Access to
technology, device data, processing.
Fujitsu: Global semiconductor player with UK presence - CASE studentship,
interconnects.
NMI: Trade association of the microelectronics industry in the UK - Recruiting
new industrial partners and dissemination
All of these partners work closely with the NanoCMOS project partners and
are continually updated on new results related to device variability and
associated new e-Infrastructure technologies, e.g. simulation tools, to address
variability in the design process.
Use and access to facilities (please provide details of main facilities
used, any issues relating to access and frequency of usage. This can
include e-Science infrastructure (i.e. NGS, OMII, DCC, etc.) and others,
including campus facilities).
The e-Infrastructure developed in NanoCMOS has focused on supporting
large scale HPC-oriented problems; managing large scale meta-data and
distributed data sets, and incorporating appropriate security. The project has
primarily exploited partner HPC clusters and the ScotGrid infrastructure at
Glasgow. We note that the NanoCMOS virtual organisation (VO) has used
more resources of ScotGrid than any other VO despite ScotGrid and Glasgow
being an EGEE/GridPP2 tier-2 site including VOs such as ATLAS with over
1500 members. Some use of the NGS resources has been made however IPrestrictions often mean that certain simulations are restricted to electronic
partner clusters.
The project originally attempted to use the OMII-UK software and built proof of
concept systems with these solutions, however a combination of factors
meant that alternative solutions were required. These included robustness
and reliability of the OMII-UK job submission and management systems
(GridSAM) as existed at that time; lack of support for large scale distributed
file-based data and metadata, and lack of inter-operability with security
solutions as demanded by the partners.
Public engagement activities (please provide details of activities such as
public lectures, engaging with the media etc (200 words max.)).
Conferences organised by NanoCMOS:

First International Conference on CMOS
collaboration with NMI (London, October 2007)

Second International Conference on CMOS Variability (ICCV2) in
collaboration with NMI (London, May 2009)

CMOS variability research in Europe: From Atomic Scale to Circuits and
Systems (Edinburgh, September 2008)
Variability
(ICCV1)
61 Invited talks
Production level videos on NanoCMOS have also recently been created and
distributed through the JISC e-Infrastructure Use Cases and Service Usage
Models (e-IUS) project. These explain more about the nanoCMOS scientific
challenges and the e-Infrastructure developed to meet these challenges.
in