Datorarkitektur I
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Datorarkitektur I
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What’s going on next in this course?
INSTRUCTION SET
I/O
n
I/O
2
I/O
1
1. Machine Instructions
2. Types of Machine Instructions
3. Conditional and Unconditional Branches
4. Branch Instructions to Support Subroutines
CPU
Main
Memory
5. The Stack
6. Basic Input-Output Operations
There we’ll concentrate in this
and some of the
following lectures
7. Addressing Mode Trade-offs
8. Presentation of Addressing Modes
9. Instruction Formats
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Petru Eles, IDA, LiTH
Datorarkitektur I
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Datorarkitektur I
Machine Instructions
•
•
One of the main characteristics of a CPU is its
instruction set.
The instruction set is the collection of machine
instructions the CPU executes.
A machine instruction is represented as a
sequence of bits (binary digits).
These bits have to define:
- What has to be done (the operation code)
- To whom the operation applies (source operands)
- Where does the result go (destination operand)
- How to continue after the operation is finished
0 0 0 01 0 1 11 0 0 01 0 1 1
opcode
•
•
operand operand
(memory) (register)
Types of Machine Instructions
•
Machine instructions are of four types:
- Data transfer between memory and CPU registers
- Arithmetic and logic operations
- Program control (branch)
- I/O transfer
•
Important aspects concerning instructions:
- Number of addresses
- Types of operands
- Addressing modes
Instruction
set design
- Operation repertoire
- Register access
- Instruction format
The representation of a machine instruction is
divided into fields; each field contains one item of
the instruction specification (opcode, operands,
etc.); the fields are organized according to the
instruction format.
The addresses of source and destination operands,
as well as the address of the following instruction to
be executed, can be specified in several ways:
these are the addressing modes.
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Number of Addresses in an Instruction
To compute X := (A + B) * C
Number of Addresses in an Instruction (cont’d)
(a Pascal statement)
4-address instruction: op A1, A2, A3, A4
A1 ← [A2] op [A3]
Next instruction address = A4
I1: ADD
I2: MUL
I3:
•
X, A, B, I2
X, X, C, I3
- Four address instructions are unpractical; implicitly the next instruction to be executed is the
one that follows in memory; there are specialized instructions for branching;
- One address instructions impose the utilisation
of a single, implicit, register for all instructions.
This is too restrictive. The use of multiple registers is required.
- Fewer addresses/instruction simplifies the instruction format, reduces the instruction length
and the complexity of the CPU; however instructions become more primitive.
3-address instruction: op A1, A2, A3
A1 ← [A2] op [A3]
ADD
X, A, B
MUL
X, X, C
2-address instruction: op A1, A2
A1 ← [A1] op [A2]
MOVE
ADD
MUL
Most contemporary computers have two and three
- address instructions; reasons:
A, X
X, B
X, C
1-address instruction: op A1
Acc ← [Acc] op [A1]
LOAD
ADD
MUL
STORE
A
B
C
X
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Datorarkitektur I
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Datorarkitektur I
Program Control (Branching)
An example (Motorola 68000)
Conditional and Unconditional Branches
•
•
N words
NXTW
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Unconditional branch:
------------BR
Target
------------------------Target - - - - - - - - - - - - -------------
•
Conditional branch: causes a branch only if a
specified condition is satisfied.
Conditional branches are based on information
stored in condition code flags; usually these flags
are grouped together into the status register of the
CPU.
BLK2
LEA
LEA
MOVE.L
MOVE.W
SUBQ.L
BNZ
BLK1,A1
BLK2,A2
N,D0
(A1)+,(A2)+
#1,D0
NXTW
Implicitly the next instruction to be performed is the
one that immediately follows the current one.
There are specialized instructions which can
change the sequence of instruction execution. The
final effect of such an instruction is to load a new
value into the Program Counter (PC).
•
N words
BLK1
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•
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Datorarkitektur I
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Condition Code Flags and their Use for Branching
•
The most commonly used flags are:
- N (negative): is set to 1 if the result is negative;
otherwise cleared to 0.
- Z (zero):
is set to 1 if the result is 0; otherwise cleared to 0.
- V (overflow): is set to 1 if arithmetic overflow occurs; otherwise cleared to 0.
- C (carry):
is set if a carry occurs from the
most significant bit position during
an arithmetic operation; otherwise
cleared to 0.
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Branch Instructions to Support Subroutines
•
------------SUBQ.L #1,D0
BNZ
NXTW
Main problems:
- jump to a procedure
- return from the procedure
- pass parameters
- support nesting of procedure calls
Example:
-------------CALL
PROCA
-------------PROCA
--------------------------CALL
PROCB
-------------BR
(LR)
----------------------
N Z V C
NXTW
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(branch if not zero)
•
Other conditional branches: BEZ (branch if equal
zero), BLZ (branch if less than zero), .....
•
The flags are affected by certain instructions
(usually arithmetic and logic but N and Z may be
also affected by data transfer instructions); later
branch instructions can use the flags as set by a
previous arithmetic, logic or transfer operation.
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PROCB
--------------------------CALL
PROCC
-------------BR
(LR)
---------------------PROCC
--------------------------BR
(LR)
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Alternative Solutions for Branching to Subroutines
•
•
The simplest solution is to have a special
unconditional branch instruction (called CALL)
which saves the return address into a specific
location, usually a register (the "link register" LR).
This simple solution is adopted by the PowerPC.
This solution does not work with nested subroutine
calls if return addresses are not saved by the
programmer. The previous example has to be
changed as follows in order to be correct:
-------------CALL
PROCA
-------------PROCA
MOVE
LR,LOCA
-------------CALL
PROCB
-------------BR
(LOCA)
---------------------PROCB
MOVE
LR,LOCB
-------------CALL
PROCC
-------------BR
(LOCB)
---------------------PROCC
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Alternative Solutions (cont’d)
•
•
More complicated solutions are needed to support
recursive subroutine calls.
Problems are solved if the return address is saved
automatically using a special data structure called
the stack.
The Stack
• The stack is a list of data elements, with the
restriction that elements can be added or removed
at one end of the list only. This end is called the top
of the stack and the other end is called the bottom.
• Placing a new element on top of the stack is an
operation called push; removing the top element is
called pop.
• Several computers have hardware implementations
of a stack structure; a portion of the main memory
is managed as a stack and a special register (Stack
Pointer - SP) contains the reference to the top of
the stack. Operations like PUSH and POP are
hardware implemented.
--------------------------BR
(LR)
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Datorarkitektur I
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Stack Operations
•
Location LC1 11110000
Location LC2 00000000
11111110
00000001
00000000
00000010
After PUSH LC1
After POP LC2
Location LC1 11110000
Location LC1 11110000
Location LC2 00000000
Location LC2 11110000
SP
A CALL instruction automatically saves the return
address on top of the stack; Before branching to the
subroutine address a PUSH PC is automatically
executed.
• A RETURN Instruction jumps to the address which
is automatically popped from the stack.
• Pentium and Motorola 68000 support this
alternative.
The example in this case:
-------------CALL
PROCA
-------------PROCA - - - - - - - - - - - - - CALL
PROCB
-------------RETURN
----------------------
11110000
11110000
00000001
00000001
-------------CALL
PROCC
-------------RETURN
----------------------
00000000
00000000
PROCC
00000010
00000010
SP
PROCB
•
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Similar stack based techniques are also used for
parameter passing.
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Datorarkitektur I
Basic Input-Output Operations
•
Example
Communication between CPU and a videoterminal using
program-controlled I/O. The device interface consists of:
- 8 bit buffer register DATAIN associated with the
keyboard;
- synchronization control flag SIN associated
with the keyboard; SIN is set to 1 if there is a
valid character in DATAIN; it is automatically
cleared when the content of DATAIN is read.
- 8 bit buffer register DATAOUT associated with
the display;
- synchronization control flag SOUT associated
with the display; SOUT is set to 1 if the display
is ready to receive a character; it is automatically cleared when a character has been transferred to DATAOUT.
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Example (cont’d)
To initiate an I/O operation the CPU issues an
address (specifying the I/O module and device) and
an I/O command.
There are four types of I/O commands
- control commands (clear screen, rewind tape, etc)
- test status
- read commands
- write commands
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--------------------------RETURN
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Datorarkitektur I
•
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Stack Based Subroutine Activation and Return
This is the initial situation:
SP
Datorarkitektur I
CPU
Main
Memory
DATAIN DATAOUT
SIN
SOUT
The sequence for character input from the keyboard:
RDWAIT
TESTIO
SIN
BEZ
RDWAIT
IN
R1,DATAIN
The sequence for character output to the display:
WRWAIT TESTIO
SOUT
BEZ
WRWAIT
OUT
R1,DATOUT
•
SIN, DATAIN, SOUT, DATAOUT are addresses of
the respective device registers (flags). They are
part of the address space used to access I/O
devices and this is considered to be independent
from the memory address space.
⇒ When the special I/O instructions are used the
address is considered to belong to an I/O device
and the corresponding bus control to access the
device is activated (see lecture 4).
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Addressing Modes
Example (cont’d)
The previous sequences in the case I/O is memory
mapped
•
Certain addresses are pre-assigned to status and
data registers of I/O modules and devices. The
CPU treats these registers similar to memory
locations and uses the same machine instructions
to access both memory and I/O devices (see
lecture 4).
•
The addresses of source and destination operands,
as well as the address of the following instruction to
be executed, can be specified in several ways:
these are the addressing modes.
The sequence for character input from the keyboard:
RDWAIT
TESTBIT SIN
BEZ
RDWAIT
MOVE
DATAIN,R1
The sequence for character output to the display:
WRWAIT TESTBIT SOUT
BEZ
WRWAIT
MOVE
R1,DATOUT
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Datorarkitektur I
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Datorarkitektur I
Why Different Addressing Modes?
•
•
Different alternatives to specify the address of an
operand or of the result provide flexibility which
simplifies programming;
The number of bits reserved for address
representation in an instruction word is limited
8 bits
Memory
Addressing Modes: Trade-offs
•
Few and simple addressing modes:
- requires large fields in the address word for address representation or the address range
which can be referred will be reduced;
- reduces flexibility of programming.
- provides fast address calculation;
- reduces CPU complexity;
•
Several sophisticated address modes:
- allows for size reduction of the address fields in
the instruction word without reducing the effective address range;
- provides flexibility in programming;
- address calculation can be sophisticated and
slow;
- can increase CPU complexity.
opcode
operand
MOVE operand,R1
With 8 bits for the address field, only 28 memory
locations can be referred with the instruction above.
If we could specify a register number (instead of the
address itself) in the address field and indicate that
the address of the operand is in that register, 216
memory locations could be referred (considering 16
bit registers):
MOVE (R2),R1
Memory
opcode
operand
R2
16 bits
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Addressing Modes
Immediate Addressing
•
•
•
•
•
•
•
•
•
Immediate
Direct
Register
Indirect
Displacement
Indexed
Relative
Stack
ADD R4,#3
effect:
R4←R4+3
The operand is directly in one of the fields of the
instruction word.
operand
Direct Addressing
•
ADD R4,X
effect:
R4←R4+[X]
The effective address of the operand is in the
instruction word.
Memory
operand address
operand
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Datorarkitektur I
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Register Addressing
•
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b) Register indirect addressing
ADD R4,R3
effect:
R4←R4+R3
Register addressing is similar to direct addressing,
but the address field refers to a register rather than
main memory.
register reference
•
ADD R4,(R1)
effect:
R4←R4+[R1]
Register indirect addressing is similar to indirect
addressing, but the address field refers to a register
rather then to main memory.
Memory
register reference
operand
operand
operand addr.
Indirect Addressing
a) Memory indirect addressing
ADD R4,(X)
effect:
R4←R4+[[X]]
• The instruction word contains the effective address
of a memory location which actually contains the
effective address of the operand,
memory address
Memory
op. addr.
•
Register indirect addressing is often combined with
autoincrement and autodecrement: after each
execution of the instruction the register containing
the address is incremented (decremented)
ADD R4,(R1)+
effect:
R4←R4+[R1]
R1←R1+1
Example shown on slide 7 (Motorola 68000):
operand
•
With indirect addressing a larger number of
memory words can be addressed than with direct
addressing: 2N > 2K
N - the word size
K - size of the address field in instruction word
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NXTW
Petru Eles, IDA, LiTH
LEA
LEA
MOVE.L
MOVE.W
SUBQ.L
BNZ
BLK1,A1
BLK2,A2
N,D0
(A1)+,(A2)+
#1,D0
NXTW
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Displacement Addressing
•
ADD R4,R1.X
effect: R4←R4+[R1+X]
A base register (which can be often any general
purpose register) holds an effective address - the
base address; the displacement (X) is stored in the
instruction word and is considered as an offset from
the base address.
Memory
base reg. displacem.
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Example with indexed addressing
Compute the sum of the elements in a table holding N
integers:
N integers
TABLE
NXTADD
operand
base addr.
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+
MOVE
MOVE
ADD
ADD
COMP
BNZ
MOVE
#0,R2
#0,R0
R0,TABLE[R2]
#1,R2
R2,N
NXTADD
R0,SUMME
Indexed Addressing
•
ADD R4,X[R1]
effect: R4←R4+[X+R1]
Indexed addressing resembles base-displacement
addressing. However, at indexed addressing it is
considered that the address field in the instruction
word contains an effective address and the index
register contains a displacement.
Memory
index reg. mem. addr.
operand
displacem.
+
Petru Eles, IDA, LiTH
•
Indexing is often combined with autoincrement or
autodecrement; after execution of the instruction
the index register is automatically incremented/
decremented.
ADD R4,X[R1]+
effect: R4←R4+[X+R1]
R1←R1+1
The example above:
MOVE
#0,R2
MOVE
#0,R0
NXTADD
ADD
R0,TABLE[R2]+
COMP
R2,N
BNZ
NXTADD
MOVE
R0,SUMME
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Datorarkitektur I
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Datorarkitektur I
Combining Indirect and Indexed Addressing
Relative Addressing
•
preindexing (preindexed indirect addressing)
ADD R4,(X[R1])
effect: R4←R4+[[X+R1]]
This is a variant of displacement addressing, but
the base address is implicitly in the program
counter. The instruction word contains a
displacement which can be positive or negative.
Memory
index reg.
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displacem.
mem. addr.
op. addr.
PC
displacem.
+
+
effective address
operand
•
postindexing (postindexed indirect addressing)
ADD R4,(X)[R1]
effect: R4←R4+[[X]+R1]
Relative addressing is used in branch instructions.
The target of a branch is usually near to the
instruction executed ⇒ fewer bits are needed to
store the displacement than the effective address of
the target instruction.
Memory
index reg.
mem. addr.
Stack Addressing
mem. addr.
displacem.
+
operand
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•
Special operations that work on the stack (PUSH,
POP, CALL, RETURN) implicitly refere to the top of
the stack. They use so called "stack addressing"
where the effective address is the one stored in the
Stack Pointer register (SP).
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Datorarkitektur I
Instruction Formats
Instruction Formats (cont’d)
•
•
The instruction format refers to the way the fields
within an instruction word appear in memory and
how they encode the operation codes and
operands.
opcode
operand_1
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Some opcodes implicitly require certain addressing
mode.
Other opcodes allow different addressing modes for
the operands. In this case some bits have to
indicate the actual addressing mode; for different
addressing modes the respective operand field is
organized differently and can be of different length.
operand_2
opcode
operand_1
mode bits
•
Trade-offs at the design of instruction formats
- short instructions require less memory then
long ones but provide few bits for encoding opcodes and operand addresses.
- variable length instruction formats can reduce
the demand on memory by efficient use of the
bits in the instruction word. However, they increase the complexity of the CPU and can
cause performance reduction (especially with
pipelining).
Petru Eles, IDA, LiTH
•
For register specification the number of bits needed
depends on the number of registers available.
If 32 general purpose registers are uniformly
available for any purpose ⇒ 5 bits are needed
when a register has to be specified (as an operand,
indirect address, index register, etc.).
If only 16 of this 32 registers can be used for
general purpose (as operands) and from the rest
only 8 as index registers ⇒ 4 bits are sufficient for
specification of register operands and only 3 for
index register specification.
•
Intel 80X86 and Pentium have variable length
instruction formats (from 1 to 15 bytes)
In the PowerPC fixed length instruction format is
used (4 bytes).
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Datorarkitektur I
Summary
•
•
One of the main characteristics of a CPU is its
instruction set. Instructions are represented as
binary digits according to a certain instruction
format.
Usually the instruction set of a computer covers
data transfer, arithmetic/logic, program control, and
I/O transfer. However, the instruction sets of
different computers can be very different (number
of addresses, addressing modes, etc.).
•
For program control purposes conditional and
unconditional branching has to be provided.
Conditional branches are based on conditional
code flags.
•
Subroutine calls are important because they are
frequent in current programs. Special facilities for
subroutine call are based often on hardware
implemented stacks.
•
Particular operations can be used to solve I/O
transfer. If access to a certain device is memorymapped, ordinary data transfer operations are used
for I/O.
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operand_2
mode bits
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Summary (cont’d)
•
Addresses of operands and instructions can be
specified in different ways. Evolved addressing
modes provide for flexibility in programming as well
as for a large range of addressable memory
locations.
•
Addressing modes:
- Immediate addressing
- Direct + Register addressing
- Indirect addressing (with autoincrement and autodecrement)
- Displacement, Relative and Indexed addressing
(with autoincrement and autodecrement)
- Stack addressing
•
Instruction formats define how the fields in an
instruction word are organized and how long they
are. Instruction words can be of fixed or variable
length.
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