International Journal of Engineering Trends and Technology (IJETT) – Volume 34 Number 1- April 2016
Design of 32 Bit Low Power RISC Processor
for DSP Applications
K.Hari Priya#1, Chinthakindi Roja Sree*2
#1Associate Professor, *2 M.Tech(vlsi system design) Scholar & Department of ECE &Anurag Group of
Institutions
Hyderabad, India
ABSTRACT In this paper, Implementation of 32 bit
low power Five stage pipelining RISC processor using
Harvard architecture for DSP applications is
presented. To achieve low power, architecture
modifications are made in the incrementer circuit by
using binary excess converter (BEC) instead of ripple
carry adder, in arithmetic and logic unit (ALU)
multiplier and adder is designed by using modified
Wallace tree with common Boolean logic and carry
select adder (CSLA) using common Boolean
logic(CBL).In order to use processor for DSP
applications multiply and accumulator unit (MAC)
unit is designed.FIR filter application is developed by
using designed RISC processor. This project is
implemented on Sparten3 Xilinx FPGA board by using
verilog, Xilinx 13.2 ISE simulator and XST is used for
simulation and synthesis. On chip functionality
verified by chip scope pro analyzer and power is
analyzed by Xpower analyzer. Result analysis shows
that power as been reduced from 532.82mw to
105.18mw.
Key words-Reduced instruction set computer (RISC),
Arithmetic and logic unit (ALU), Binary to excess
converter(BEC),Common Boolean logic (CBL),
Digital signal processing (DSP),finite impulse
response (FIR).
I.
INTRODUCTION
General purpose processors are mainly used for the
general purpose application and these processors are
classified into two types those are RISC and CISC.
The performance of the RISC processor is very high
compare to CISC. A 16-bit non-pipelined von
Neumann RISC processor is used for signal
processing applications [6].In the proposed project
Harvard architecture is used and to achieve low power
Advantageous architectural modifications have been
made in the incremented circuit used in program
counter [1],carry select adder unit[3] and a high speed
and low power modified Wallace tree multiplier[5]
has been designed and introduced in the design of
ALU. In order to use processor for DSP applications
multiply and accumulator unit (MAC) unit also have
to designed [7].An Incrementer (INC) is an important
building block in many digital systems such as the
address generation unit of microcontrollers and
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microprocessors. Conventional incrementer circuits
are designed using ripple carry adder. The critical
delay for the incrementing operation is determined by
the delay incurred in the carry bit propagation time,
through the chain of AND gates. As the size of the
chain grows, this delay also increases, making the
delay of the most significant bit (MSB), the largest
one in the process. A new circuit for the incrementer
is proposed in this project. The proposed circuit
reduces the operation complexity and number of
devices used. It paves way for less power dissipation
[1]. In electronics, adder is a digital circuit that
performs addition of numbers. To perform fast
arithmetic operations, carry select adder (CSLA) is
one of the fastest adders used in many dataprocessing processors. The structure of CSLA is such
that there is scope of reducing power consumption.
Simple and efficient gate – level modification is used
in order to reduce power of CSLA. The conventional
carry select adder using BEC has the disadvantage of
more power consumption [2]. The proposed SQRT
CSLA using common Boolean logic has low power
than all the other adder structures. In this way
proposed SQRT CSLA has low power which makes it
simple and efficient for VLSI hardware
implementations [3].Multiplication process is often
used in digital signal processing systems,
microprocessors designs, communication systems, and
other application specific integrated circuits.
Multipliers are complex units and play an important
role in deciding the power consumption of digital
designs. Speed of the multiplier can be increased by
reducing the generated partial products. Many
attempts have been made to reduce the number of
partial products generated in a multiplication process,
C. S. Wallace introduced a way of summing the
partial product bits in parallel using a tree of Carry
Save Adders which became generally known as the
“Wallace Tree” [4].In the proposed project to achieve
low power modified Wallace tree is used and final
addition is done by using carry select adder using
common Boolean logic [5].
II. SYSTEM DESIGN
A.BLOCK DIAGRAM OF RISC PROCESSOR
The fig1 shows the main block diagram of
32-bit pipelined RISC processor, which is used for
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signal processing applications. The architecture of the
proposed RISC CPU is a uniform 32-bit instruction
format, single cycle pipelined processor. It has a
load/store architecture, where the operations will only
be performed on registers, and not on memory
locations. The RISC processor has been designed for
Executing 23-instruction set with 1kb ROM and
rom.32 bit register file and 10 bit address is used in
designing 32 bit RISC processor.The functionality of
the project is as follows. CLK and reset gives as input
to this project.Based upon the inputs Clk, reset and
pc_enable program counter will increment at every
positive edge of the clock and the output address will
be generated. Based upon the address the processor
first fetches the instruction from the program memory.
This instruction is further sent to the decoder. Decoder
decodes the instruction into 6bit opcode and 5bit
addresses. Based upon the addresses the input data
writes into any one of registers in register file.
Execution unit reads the values from register file and
do the instruction operation based on the opcode.The
value given by the execution unit write back to
register file.
III. LOW POWER INCREMENTER
CIRCUIT
In the proposed project 10 bit counter is used by using
the 5 bit BEC logic instead of RCA. Block diagram of
10 bit program counter is shown in fig 2.
Fig 2 10 bit incrementer circuit
The basic idea of this work is to use Binary to Excess1 Converter (BEC) instead of RCA in the regular
incrementer circuit to achieve low power
consumption. In the proposed project 10bit program
counter with BEC logic is used. The below design
employs the carry select adder method in place of the
conventional ripple-carry adder structure.
The main modules in program counter are:
1. Binary to excess-1 converter (BEC).
2. Multiplexer.
A.BINARY TO EXCESS-1 CONVERTER
Fig 1 Block diagram of RISC processor
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The entire work performed by usage of Binary to
Excess-1 Converter (BEC) instead of RCA with Cin =
1 in the regular Counter to achieve lower power
consumption. The main advantage of this BEC logic
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comes from the lesser number of logic gates than the
n- bit Ripple Carry Adder (RCA). A structure of 4-bit
BEC and the truth table and Boolean expressions are
shown in Fig.3 and Table 1 respectively.
This reduces the power when compared with the
conventional methods of incremented structures.
TABLE 1
In arithmetic logic unit (ALU) is a digital circuit used
to perform arithmetic and logic operations. In the
proposed project low power adder and multiplier is
designed in order to achieve low power. The main
modules in ALU are:
TRUTH TABLE FOR BINARY TO EXCESS-1
CONVERTER
Binary b[4:0]
Excess-1 X[4:0]
0000000000
0000000001
0000000001
0000000010
0000000010
0000000011
0000000011
0000000100
0000000100
0000000101
IV. ARITHMETIC AND LOGIC UNIT
1. Carry select adder with common Boolean logic
(CSLA with CBL).
2. Modified Wallace tree multiplier with common
Boolean logic.
In order to reduce the complexity of the adder circuits
used in the arithmetic unit of the RISC CPU, low
power carry select adder circuit with CBL has been
introduced. The ALU also consists of a modified
Wallace tree multiplier, which uses compressor
circuits to achieve low power.
1. CARRY SELECT ADDER WITH COMMON
BOOLEAN LOGIC
X0=~b0
C1=b0 and b1
In this paper, a modified carry select adder by sharing
the common Boolean logic term is proposed. Fig4
shows the block diagram of Proposed SQRT CSLA.
The main modules in carry select adder with CBL are
X2=b2 xor (b0 and b1)
a. Ripple carry adder (RCA).
X1=b0 xor b1
C2=b2 and b3
b. Common Boolean logic (CBL)
C0=C1 and C2
After Boolean simplification, it can remove the
redundant logic operations in the conventional carry
select adder. It generates a redundant sum and Carry
out signal by using NOT and OR gate and select value
with the help of multiplexer. The multiplexer is used
to select the correct output according to its previous
carry out signal. The proposed CSLA provides less
power dissipation.
C3=C1 and b2
X3=b3 xor C3
COMMON BOOLEAN LOGIC
Fig 3.A 4-bit Binary to Excess-1 Converter (BEC)
It can be seen that the carryout bit of the block is
calculated in parallel by using a parallel chain of AND
gates. On the other hand, the Ripple Carry Adder
structure uses a series pattern of carry propagation.
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Simple and efficient gate level modification is used in
order to reduce the power of CSLA. To remove the
duplicate adder cells in the conventional CSLA, an
area efficient SQRT CSLA is proposed by sharing
Common Boolean Logic (CBL) term as shown in the
following figure5.
While analyzing the truth table of single bit full adder,
results show that the output of summation signal as
carry-in signal is logic “0” is inverse signal of itself as
carry-in signal is logic “1”. It is illustrated by red
circles in Table2. To share the Common Boolean
Logic term, we only need to implement a XOR gate
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International Journal of Engineering Trends and Technology (IJETT) – Volume 34 Number 1- April 2016
and one INV gate to generate the summation pair. And
to generate the carry pair, we need to implement one
OR gate and one AND gate. In this way, the
summation and carry circuits can be kept parallel.
Fig 5 Internal structure of the proposed area-efficient
carry select adder is constructed by sharing the
common Boolean logic term.
In the proposed SQRT CSLA, the transistor count is
trade-off with the speed in order to achieve lower
power delay product. Thus the proposed SQRT CSLA
using CBL is better than all the other designed adders.
Fig.4.Proposed SQRT CSLA using Common Boolean
Logic
2. MODIFIED WALLACE TREE MULTIPLIER
WITH COMMON BOOLEAN LOGIC
Table 2
Truth table of single bit full adder, where the
upper half part in the case of Cin=0 and the lower
half part is the case of Cin=1.
A multiplier is one of the key hardware blocks in most
digital and high performance systems such as FIR
filters, micro processors and digital signal processors
etc. A system's performance is generally determined
by the performance of the multiplier because the
multiplier is generally the slowest element in the
whole system and also it is occupying more area
consuming. Multipliers are usually structured into
three functions: partial-product generation, partialproduct accumulation and final addition. The main
source of power is the partial-product accumulation
stage. Multiplier require high amount of power during
the partial products addition. The proposed
architecture aims to reduce the power by using
modified Wallace tree with common Boolean logic as
shown in fig 6.
This method replaces the Binary to Excess-1 converter
add one circuit by common Boolean logic. As
compared with modified SQRT CSLA, the proposed
structure has less power dissipation. Internal structure
of proposed CSLA is shown in Fig5.
Fig.6 Modified Wallace tree multiplier with pyramid
structure
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International Journal of Engineering Trends and Technology (IJETT) – Volume 34 Number 1- April 2016
This leads reduced power consumption. The design
makes use of compressors in place of full adders, and
the final carry propagate stage is replaced by a CSLA
with CBL as shown in figure 7.The Carry Select
Adder (CSLA) provides a good compromise between
cost and performance in carry propagation adder
design. A Square Root Carry Select Adder using RCA
is introduced but it offers some speed penalty.
However, conventional CSLA is still area-consuming
due to the dual ripple carry adder structure. In the
proposed work, generally in Wallace multiplier the
partial products are reduced as soon as possible and
the final carry propagation path carry select adder is
used. In this project, modification is done at gate level
to reduce power consumption. The Modified Square
Root Carry Select-Adder (MCSLA) is designed using
Common Boolean Logic and then compared with
regular CSLA respective architectures, and this
MCSLA is implemented in Wallace Tree Multiplier as
shown in fig 8.
Fig.7 Wallace tree architecture using CBL based
SQRT CSLA
The proposed architecture aims to reduce the
overall power dissipation. The design makes use of
compressors in place of full adders, and the final carry
propagate stage is replaced by a CSLA with CBL. The
Wallace tree is constructed by considering all the bits
in each fours row at a time and compressing them in
an appropriate manner. Thus, compressors form the
essential requirement of low power multipliers. The
power consumption of the multipliers will be in direct
proportion to the efficiency of the compressors. Thus,
in order to satisfy the requirement of low power, this
project provides novel designs of 3:2, 4:2 and 5:2
compressors. The proposed designs are highly
efficient in terms of low power. The Wallace tree
construction method is usually used to add the partial
products in a tree-like fashion in order to produce two
rows of partial products that can be added in the last
stage. The Wallace tree is fast since the critical path
delay is proportional to the logarithm of the number of
bits in the multiplier. The prominent method considers
all the bits in each column at a time and compresses
them into two bits (a sum and a carry).For compress
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them into two bits many type of compressor are used
such as 4:2compressor, 3:2 compressor, 5:3
compressor.
The modified Wallace tree module has three steps:
1. Partial Product Generation Stage
2. Partial Product Reduction Stage
3. Partial Product Addition Stage
PARTIAL PRODUCT GENERATION STAGE
The Wallace tree basically multiplies two unsigned
integers. The Proposed Wallace tree multiplier
architecture comprises of an AND array for
computing the partial products, an adder for adding
the partial products so obtained and a CSLA WITH
CBL adder in the final stage of addition.
COMPRESSOR
REDUCTION
FOR
PARTIAL
PRODUCTS
The latency in the Wallace tree multiplier can be
reduced by decreasing the number of adders in the
partial products reduction stage. In the proposed
architecture, multi bit compressors are used for
realizing the reduction in the number of partial
product addition stages. The combined factors of low
power, low transistor count and minimum delay
makes the 5:2 , 4:2 and 3:2 compressors, the
appropriate choice. In these compressors, the outputs
generated at each stage are efficiently used by
replacing the XOR blocks with multiplexer blocks so
that the critical path delay is minimized. The various
adder structures in the conventional architecture are
replaced by compressors.
Compressors are arithmetic components, similar in
principle to parallel counters, but with two distinct
differences: (1) they have explicit carry-in and carryout bits; and (2) there may be some redundancy
among the ranks of the sum and carry-output bits.
3:2 COMPRESSOR
A 3-2 compressor takes 3 inputs x1, x2, x3 and
generates 2 outputs, the sum bit s, and the carry bit c.
The compressor is governed by the basic equation x1
+ x2 + x3 = Sum + 2 * Carry The 3-2 compressor can
also be employed as a full adder cell when the third
input is considered as the Carry input from the
previous compressor block or X3 = Cin.
4:2 COMPRESSOR
The 4:2 compressor has 4 input bits and
produces 2 sum output bits (out0 and out1 ), it also has
a carry-in (Cin) and a carry-out (Cout) bit (thus, the
total number of input/output bits are 5 and 3); All
input bits, including Cin, have rank 0; the two output
bits have ranks 0 and 1 respectively, while Cout has
rank 1 as well. Thus, the output of the 4:2 compressor
is a redundant number; for example, out1 = 0 and
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International Journal of Engineering Trends and Technology (IJETT) – Volume 34 Number 1- April 2016
Cout = 1 is equivalent to out1=1 and Cout=0 in all
cases.
5:2 COMPRESSOR
The 5:2 compressor has 5 input bits and
produces 2 sum output bits (sum and cout3), it also
has a carry-in (cin1, cin2) and a carry-out (cout1,
cout2,cout3) bit (thus, the total number of input/output
Fig.10 5:2 compressor I/O diagram
This work gives the reduced area compared to normal
Wallace tree multiplier. Finally an area efficient
Wallace tree multiplier is designed using common
Boolean logic based square root carry select adder
PARTIAL PRODUCT ADDITION STAGE
Fig.8 (a) 4:2 compressor I/O diagram; (b) 4:2
compressor architecture
For addition 32 bit CSLA with CBL as shown in fig4
is used.
REGISTER FILE
The register file consists of 32 general purpose
registers of 32-bits capacity each. These register files
are utilized during the execution of arithmetic and
data-centric instructions. It is fully visible to the
programmer. It can be addressed as both source and
destination using a 5-bit identifier. The register
addresses are of 5-bit length. The load instruction is
used to load the values into the registers and store
instruction is used to retrieve the values back to the
memory to obtain the processed outputs back from the
processor. For DSP applications MAC unit is used.
INSTRUCTION DECODER UNIT
Fig.9 Logic used in 4 bit Wallace Tree Multiplier
using 4:2 Compressor
bits are 7 and 4); All input bits, including cin1, have
rank 0 and cin2 has rank 2 ; the two output bits have
ranks 0 and 1 respectively, while cout2 has rank 1 and
cout1 has rank 2 as shown in Fig10.
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The decoder units decodes the instruction and gives
out the 5-bit source and destination addresses
respectively, depending on the op-code’s operation
and it also decides whether the write back circuit has
to be enabled or not. In case of Load/Store
instructions, the IDU updates the Link register. In case
of Jump instructions, if the conditions are satisfied, the
IDU updates the PC register with the new address
from where the next instruction has to be retrieved
rather than the normal incremented value. Instruction
format followed by Logical instructions and Data
transfer instructions, such as, MOV, AND, OR, XOR,
ADD, SUB, SL (Shift Left), SR (Shift Right), SWAP
and Multiply instructions and Immediate instructions
ANDI, ORI, XORI, ADDI, SUBI. the instruction
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International Journal of Engineering Trends and Technology (IJETT) – Volume 34 Number 1- April 2016
format for JUMP, JZ (Jump if Zero), JNZ (Jump if not
Zero).
INSTRUCTION SET
Table 3
Instruction set and corresponding opcodes
V. MULTIPLIER-ACCUMULATOR
All DSP Algorithms would require some
form of the Multiplication and Accumulation
Operation. This is the most important block in DSP
systems. It is composed of an adder, multiplier and the
accumulator. Basically the multiplier will multiply the
inputs and give the results to the adder, which will add
the multiplier results to the previously accumulated
results. Power dissipation is one of the most important
design objectives in integrated circuit, after speed.
Digital signal processing (DSP) circuits whose main
building block is a Multiplier-Accumulator (MAC)
unit. Low power MAC unit is desirable for any DSP
processor. This project explores the design of low
power MAC by using low power adder and multiplier.
The main modules in MAC are
1. Modified Wallace tree with common
Boolean logic.
2. Carry select adder with common Boolean
logic.
In order to achieve low power CSLA with
CBL and modified Wallace tree with CBL is used as
described above. This operation eases the computation
of the most important formula i.e. b (n)x(n-k)which is
needed in filters, Fourier analyzers, etc. MAC unit
consists of adder, multiplier, and an accumulator.
Figure 11 shows the MAC Unit architecture. The
inputs for the MAC are fetched from memory location
and fed to multiplier block of the MAC, which will
perform multiplication and give the result to adder
which will accumulate the result and then will store
the result into a memory location. This entire process
is to be achieved in a single clock cycle. In this
project, 16 bit Modified Wallace tree multiplier and
32 bit CSLA with CBL are used for high performance
MAC unit design
INSTRUCTION FORMATS
RAM
RAM is a Volatile memory that requires power to
maintain the stored information. In this project RAM
is designed with 1kb memory (1024locations) ,10bit
address,32bit input and output data.
ROM
ROM is a Non-volatile memory is computer memory
that can retain the stored information even when not
powered. In this project ROM is designed with 1kb
memory(1024locations) ,10bit address,32bit input and
output data.
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Fig.11MULTIPLIER-AND ACCUMULATOR
Modified Wallace tree multiplier is used to
multiply the values of A and B. CSLA with CBL is
used for addition. In the proposed project it has been
applied for fir filter.
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International Journal of Engineering Trends and Technology (IJETT) – Volume 34 Number 1- April 2016
FIR FILTER
In signal processing, a finite impulse response
(FIR) filter is a filter whose impulse response (or
response to any finite length input) is
of finite duration, because it settles to zero in finite
time. This is in contrast to infinite impulse
response (IIR) filters, which may have internal
feedback and may continue to respond indefinitely
(usually decaying).The impulse response of an Nthorder discrete-time FIR filter lasts exactly N + 1
samples (from first nonzero element through last
nonzero element) before it then settles to zero.FIR
filters
can
be discrete-time or continuous-time,
and digital or analog.
Fig 12 FIR FILTER
For a causal discrete-time FIR filter of order N, each
value of the output sequence is a weighted sum of the
most recent input values:
pc_enable program counter will increment at every
positive edge of the clock and the output address will
be generated. Based upon the address the processor
first fetches the instruction from the program memory.
This instruction is further sent to the decoder. Decoder
decodes the instruction into 6bit opcode 5bit
addresses. Based upon the addresses the input data
writes into any one of registers in register file.
Execution unit reads the values from register file and
do the instruction operation based on the opcode
value. The value given by the execution unit write
backs into register file and to RAM. In order to use the
32 bit low power RISC processor for DSP applications
MAC is designed and applied for FIR filter. The
inputs for FIR filter(inputs and coefficients) is
generated from MATLAB and used in verilog code by
using Xilinx 13.2.Simulation and synthesis is done by
using Xilinx 13.2 ise simulator and xst. Sparten3
Xilinx FPGA board is used for testing and
demonstration of the implemented system. FPGA
output is seen on monitor by using chip scope pro
analyzer .For analyzing the power, Xpower analyzer is
used. As compared with conventional RISC processor
power has been reduced.
SIMULATION RESULT FOR
PROGRAM
COUNTER
where:
is the input signal,
is the output signal,
is the filter order; an th -order filter
has
terms on the right-hand side
is the value of the impulse response at
the i' th instant for
of an thorder FIR filter. If the filter is a direct form
FIR filter then is also a coefficient of the
filter.
In this project MATLAB is used to generate
the coefficients and inputs for direct form low pass
FIR filter with 8khz pass band frequency,19khz
sampling frequency of order 20.The generated
coefficients and inputs are converted into binary form
by using Q8 format and used as inputs in verilog code
for writing FIR filter code by using Xilinx 13.2.
SIMULATION RESULT FOR CARRY SELECT
ADDER USING COMMON BOOLEAN LOGIC
VI. RESULTS
Here verilog code is written for 32bit
RISC
processor, with 10 bit program counter,32 bit carry
select adder using common Boolean logic ,32bit
Wallace tree multiplier,32bit register file with
32registers,memories of 32bit with 1024 locations
,instruction set and MAC is designed based upon the
block diagram, logic and module specifications as
shown above. Based upon the inputs Clk reset and
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International Journal of Engineering Trends and Technology (IJETT) – Volume 34 Number 1- April 2016
SIMULATION
RESULT
FOR
MODIFIED
Table 4
WALLACE TREE
FPGA RESULT OF 32 BIT RISC PROCESSOR BY
USING CHIP SCOPE PRO ANALYSER
VII. CONCLUSION & FUTURE SCOPE
CONCLUSION
This project presents an approach to reduce
the power of RISC processor design. The conventional
incrementer, adder and multiplier in RISC processor
have the disadvantage of more power consumption. A
new circuit for the incrementer, adder and multiplier is
presented in this project .The proposed incrementer
circuit using binary excess counter (BEC), CSLA
using common Boolean logic, modified Wallace
multiplier using common Boolean logic tree in RISC
processor has less power dissipation compared with
conventional adder, counter and multiplier.
Simulation, Synthesis is done by using Xilinx 13.2.
Sparten3 Xilinx FPGA board is used for testing and
demonstration of the implemented system. FPGA
output is seen on monitor by using chip scope pro
analyzer.
FUTURE SCOPE
This project can be further extended for
higher number of bits, in future it can be used as
programmable RISC processor for DSP applications
by using flash memory interface.
ACKNOWLEDGEMENT
The authors express their sincere thanks to
Chairman of Anurag Group of Institutions Dr. P.
Rajeswar Reddy for all his support. They are indebted
to Dr. K. S. Rao, Director Anurag Group of
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International Journal of Engineering Trends and Technology (IJETT) – Volume 34 Number 1- April 2016
Institutions,Prof. J.V. Sharma H.O.D ECE Dept. AGI,
for their valuable suggestions.They also express
thanks to their parents,friends and colleagues.
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AUTHORS PROFILES
K. HARI PRIYA obtained her B.Tech, M.Tech
degree in E.C.E in the years of 2000, 2005 from
AMACE, University of Madras, Deemed University
of IASE, Rajasthan respectively. She had 8 years of
teaching experience. Presently she is an Assistant
professor Anurag Group of Institutions (Autonomous)
Hyderabad and pursuing Ph.D in K.L. University,
Vijayawada.
CH. ROJA SREE, Received her M.TECH degree
(VLSI System Design) from ANURAG GROUP OF
INSTITUTIONS
(Autonomous),
Ghatkesar,
Hyderabad and B.TECH from AURORA COLLEGE
OF ENGINEERING. Her research interest Digital
integrated circuit Design.
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