Low-Power and Area-Efficient Carry
Select Adder on Reconfigurable
Hardware
Under the guidance of
Mr. M. Raghupathy
Assistant Professor
Dept. of ECE
GITAM University
Presented by
V.Santhosh kumar ,
B.Tech ,ECE ,4th Year,
GITAM University
CONTENTS
 ABSTRACT
 INTRODUCTION
 EXISTING SYSTEM
 PROBLEMS IN EXISTING SYSTEM
 PROPOSED SYSTEM
 SOLUTION OF THE PROBLEM
SIMULATION RESULTS OF REGULAR CSLA
ADVANTAGES & APPLICATIONS
 CONCLUSION
ABSTRACT
 Carry Select Adder (CSLA) is one of the fastest adders used in many data-
processing processors to perform fast arithmetic functions.
 By gate level modification of CSLA architecture we can reduce area and power.
 Based on this modification 16-b square-root CSLA (SQRT CSLA) architecture have
been developed.
 The proposed design has reduced area and power as compared with the regular
SQRT CSLA .
 This work evaluates the performance of the proposed designs in terms of area,
power by hand with logical effort and through Xilinx ISE 14.2(Verilog HDL) and
this will be implemented in FPGA (Sparton 6).
INTRODUCTION
In electronics, an adder or summer is a digital circuit that performs addition
of numbers.
Adders can be constructed for many numerical representations, such as BCD or
Excess-3, the most common adders operate on binary numbers.
Adders plays Major role in Multiplications and other advanced processers
designs
EXISTING SYSTEM
The carry-select adder generally
Adders (RCA) and a Multiplexer .
consists
of
two
Ripple
Carry
Adding two n-bit numbers with a carry-select adder is done with two adders
(therefore two RCA).
In order to perform the calculation twice, one time with the assumption of the
carry being zero and the other assuming one.
REGULAR 16BIT SQRT CSLA
AREA EVALUATION METHODOLOGY OF REGULAR 16-b SQRT CSLA
Gate count=
57(HA+FA+MUX)
FA=39(3*13)
HA=6(1*6)
MUX=12(3*4)
PROBLEMS IN EXISTING SYSTEM
The problem in CSLA design is the number of full adders are increased then
the circuit complexity also increases.
The number of full adder cells are more thereby power consumption of the
design also increases
Number of full adder cells doubles the area of the design also increased.
SOLUTION OF THE PROBLEM
 The parallel RCA with Cin=1 is replaced with Binary-Excess 1 converter( BEC).
four-bit BEC
Modified CLSA
Basic function of CLSA is obtained by using the 4-bit BEC together with the mux.
PROPOSED SYSTEM(16-b CLSA)
Contd…
In this system we use the BEC to reduce the RCA circuits
Here based on the carry input the MUX will be select corresponding input
In this design we give the MUX inputs are RCA output and BEC output
Compare to regular design the area of the design is less
AREA EVALUATION METHODOLOGY OF MODIFIED 16-b
SQRT CSLA
GATE COUNT=
43(HA+FA+MUX+BEC)
(13+6+12+1+1+10)
COMPARISION
GROUP
REGULAR
MODIFIED
GROUP 2
57
43
GROUP 3
84
61
GROUP 4
117
84
GROUP 5
147
107
RTL SCHEMATIC
Simulation Result
Evaluation Results
Power Utilized = 32 mW
Delay= 16.204 ns
TOOL USED
Programming language: VERILOG HDL
Tool : Xilinx ISE (14.2)
ADVANTAGES
Low power consumption
Less area (less complexity)
More speed compare regular CSLA
APPLICATIONS
Arithmetic logic units
High Speed multiplications
Advanced microprocessor design
Digital signal process
CONCLUSION
A simple approach is proposed in this paper to reduce the area and power
of SQRT CSLA architecture. The reduced number of gates of this work offers the
great advantage in the reduction of area and also the power. The modified CSLA
architecture is therefore, low area, low power, simple and efficient for VLSI
hardware implementation.
REFERENCES
[1] B. Ramkumar, Harish M Kittur “Low power and Area efficient carry select adder,”IEEE
Trans,Vol.20,Feb 2012.
[2] T. Y. Ceiang and M. J. Hsiao, “Carry-select adder using single ripple carry adder,” Electron.
Lett., vol. 34, no. 22, pp. 2101–2103, Oct. 1998.
[3] Y. Kim and L.-S. Kim, “64-bit carry-select adder with reduced area,” Electron. Lett., vol.
37, no. 10, pp. 614–615, May 2001.
[4] J. M. Rabaey, Digtal Integrated Circuits—A Design Perspective.Upper Saddle River, NJ:
Prentice-Hall, 2001.
[5] Samir Palnitkar, “Verilog Hdl: A Guide to Digital Design and Synthesis”2005,2nd Edition.