International Journal of Engineering Trends and Technology (IJETT) – Volume 29 Number 5 - November 2015
Design and Implementation of High Speed Carry Select
Adder using Sum and Carry Generation Unit
N. Vijaykumar1, B. Rajasekhara Reddy2, D. Raghava Reddy3
Department of electronics and communication engineering,
Narasaraopeta Institute of Technology, Narasaraopeta
ABSTRACT: In the design of Digital
Integrated Circuits area occupancy, delay and
power play an important role because of the
increasing necessity of portable and fast systems.
Adders are one of the most widely used digital
components in various Digital Circuits. Carry
Select Adder (CSLA) is one of the fastest adders
among the Conventional adder structures, it can be
used in many processors, multipliers, and different
applications. Due to its less complex structure,
there is still scope for obtaining better design
Carry Select Adder (CSLA) architecture designs
for power optimization combined with better
performance. The conventional CSLA architecture
uses dual RCAs which has large area consuming.
Existing system eliminates all the redundant logic
operations present in the conventional CSLA and
Existing system a new logic formulation for CSLA.
In the Existing system, the Carry Select (CS)
operation is scheduled before the calculation of
final-sum, which is different from the conventional
approach. Bit patterns of two anticipating carry
words (corresponding to cin = 0 and 1) and fixed
cin bits are used for logic optimization of CS and
generation units. The proposed CSLA is based on
the modified logic formulation and its structure
Due to its small carry-output delay compare to the
Existing system, the proposed CSLA design is a
good candidate for Square Root (SQRT) CSLA.
number N increases, the delay time of carry ripple
adder will increase accordingly in a linear way.
The Sum for each bit position in an
elementary adder is generated sequentially only
after the previous bit position has been summed
and a carry propagated into the next position. The
CSLA is used in many computational systems to
alleviate the problem of carry propagation delay by
independently generating multiple carries and then
select a carry to generate the sum. However, the
CSLA is not area efficient because it uses multiple
pairs of Ripple Carry Adders(RCA) to generate
partial sum and carry by considering carry input
Cin=0 and Cin= 1 , then the final sum and carry are
selected by the multiplexers (mux). The existing
modified SQRT CSLA is to use Binary to Excess-1
Converter (BEC) instead of RCA with Cin=1 in the
regular CSLA to achieve lower area and power
consumption with slightly increase in the delay.
Keywords— Adder, Area efficient, Boolean logic.
Fig. 1 The N-bit carry ripple adder constructed by N set
single bit full-adder.
I. INTRODUCTION
Addition usually impacts widely the overall
Performance of digital systems and an arithmetic
function. In electronic applications adders are most
widely used. Applications where these are used are
multipliers, DSP to execute various algorithms like
FFT, FIR and ITR. In microprocessors, millions of
instructions per second are performed. So, speed of
operation is the most important constraint. In
digital adders, the speed of addition is limited by
the time required to propagate a carry through the
adder. In the carry ripple adder, each full-adder
starts its computation till previous carry-out signal
is ready. Therefore, the critical path delay in a carry
ripple adder is determined by its carry-out
propagation path. For an N-bit full-adder as
illustrated in Fig. 1, the critical path is N-bit carry
propagation path in the full-adders. As the bit
ISSN: 2231-5381
The basic idea of the proposed architecture is
that which replaces the BEC by Modified Logic
formulation method. In this paper, an area-efficient
carry select adder by sharing the modified logic
term is proposed. After Boolean simplification, it
can remove the duplicated adder cells in the
conventional carry select adder. The multiplexer is
used to select the correct output according to its
previous carry-out signal. This paper is organized
as follows: In section II Existing CSLA design is
shown, section III deals with proposed CSLA
design, section IV explains Regular SQRT CSLA.
Results are analyzed in section V and section VI
concludes.
II. EXISTING CSLA DESIGN
The optimized carry select adder architecture
is shown in fig 1.The carry select adder mainly
consist of four sections.
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International Journal of Engineering Trends and Technology (IJETT) – Volume 29 Number 5 - November 2015
The output of the half adder is given as input
to the carry generator circuit. Two carry generator
circuits are used in the design, CG0 and CG1. CG0 is
used to generate carry by assuming carry input as 0
and CG1 is used to generate carry by assuming
input carry as 1. Both CG0 and CG1 receives half
carry word and half sum word from the half adder
and generate two n-bit full carry words C1 0 and C1 1
corresponding to input carry 0 and 1 respectively.
1) Half sum generator
2) Carry generator
3) Carry selection
4) Full sum generator
Fig 2.2: Gate-level optimized design of (CG0) for inputcarry = 0.
Fig 2: Existing
CS Adder Design
1) Half sum generation unit:
The sum generation unit makes use of full
adder implementation using two half adders. Here
the first half adder receives the n-bit input and
provides half adder sum and carry. The Half Sum
Generator generates half-sum word s0 and halfcarry word c0from the given inputs. It simply uses a
half adder. The number of adders needed is same as
the number of input bits.
Fig 2.3: Gate-level optimized design of (CG1) for inputcarry = 1.
3) Carry selection unit:
The carry selection unit selects one the final
carry from the two carry words available at its
input line using the input carry cin. Here the carry
select unit selects the output of CG0 if the input
carry (cin) is 0 and selects the output of CG1 If the
input carry (cin) is 1. The carry select unit here is
implemented using an optimized design.
Fig2.1:Gate-level design of the HSG.
This half adder results are given as input for
carry generator and full sum generator. The full
sum generator obtains output after receiving the
carry input.
2) Carry generation:
ISSN: 2231-5381
Fig 2.4: Gate-level design of the CS unit.
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International Journal of Engineering Trends and Technology (IJETT) – Volume 29 Number 5 - November 2015
IV. SIMULATION RESULTS
The proposed design is developed using
VHDL and synthesized using XILINX 13.2i and is
simulated in ISim for Spartan-3e FPGA series.
4) Full sum generation unit:
The full sum of the system is generated by
XORing the selected carry from carry selection unit
with the half sum obtained in the half adder. Thus
the half sum and the obtained carry are both
XORed to get the final sum of the system.
Fig 4.1: Simulation Results of Existing 8 BIT CSLA
Adder Design.
Fig 2.5: Gate-level design of the final-sum generation
(FSG) unit.
III.PROPOSED CSLA DESIGN
The proposed CSLA is based on the modified
logic formulation and its structure is shown in
Fig.3. This circuit for SQRT CSLA re-designed.
The Modified SQRT CSLA consists of one HSG
unit, one FSG unit, one CG unit, and one CS unit.
The CG unit will generate carry corresponding to
input-carry 0 and 1. The HSG receives two n-bit
operands (a and b) and generate half-sum word s0
and half-carry word c0 of width n bits each.CG unit
receives s0 and c0(0) from the HSG unit and
generate two n-bit full-carry words corresponding
to input-carry 0 and 1, respectively. The Modified
SQRT CSLA consists only less number of Logic
gates, Area and Delay when compare to Existing
CSLA Adder Design.
Fig 3: Existing CSLA Adder Design.
ISSN: 2231-5381
Fig 4.2: Simulation Results of Existing 16 BIT CSLA
Adder Design.
Fig 4.3: Simulation Results of Proposed 8 BIT CSLA
Adder Design.
Fig 4.4: Simulation Results of Proposed 16 BIT CSLA
Adder Design.
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International Journal of Engineering Trends and Technology (IJETT) – Volume 29 Number 5 - November 2015
V. PERFORMANCE COMPARISON
The results shows that the delay of the system
have been reduced comparing to previous systems.
Table1 shows the comparison of the delay between
existing and proposed carry select adders. Table2
shows the comparison of the Logic Gates between
existing and proposed carry select adders.
Table 1: Comparison Of Delay Existing and
Proposed Carry Select Adders.
Word size
Adder
Delay
8 BIT
Existing CSLA
14.670ns
Proposed CSLA
10.553ns
Existing CSLA
24.334ns
Proposed CSLA
15.633ns
16 BIT
[3] J. M. Rabaey, Digital Integrated Circuits,‖ IEEE Trans.on
VLSI Systems, 2003.
[4] Ramkumar, B. and Harish M Kittur, (2011) ‗Low Power and
Area Efficient Carry Select Adder‗, IEEE Transactions on Very
Large Scale Integration (VLSI) Systems, pp.1-5.
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2101-2103, Oct 1998.
[6] J. M. Rabaey, Digital Integrated Circuits-A Design
Perspective, Upper Saddle River, NJ: Prentice-Hall, 2001.
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reduced area‖, Electron. Lett. Vol. 37, no. 10, pp. 614-615, May
2001.
[8] Edison A. J and C. S. Manikanda babu, ―An efficient CSLA
architecture for VLSI hardware implementation‖, Interanational
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reconfigurable
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Table 2: Comparison of Number of Logic Gates
Existing and Proposed Carry Select Adders.
Design
NO. of gates
Existing CSLA
8Bit
Proposed CSLA
8Bit
Existing CSLA
16Bit
Proposed CSLA
16Bit
60
48
120
96
VI.CONCLUSION
A simple approach is proposed in this paper
to reduce the area and delay of SQRT CSLA
architecture. The reduced number of gates of this
work offers the great advantage in the reduction of
area and also the total delay (Table 1 & 2).The
modified CSLA reduces the area and delay when
compared to Proposed CSLA.
REFERENCES
[1]. Basant Kumar Mohanty, ―Area-Delay Power Efficient
Carry Select Adder‖ ,IEEE Transactions On Circuits And
Systems—Ii: Express Briefs, Vol. 61, No. 6, June 2014.
[2]. He, Y. Chang, C. H. and Gu, J. ―An Area Efficient 64-Bit
Square Root Carry-Select Adder for Low Power
Applications‖ ,in Proc. IEEE Int. Symp. Circuits Syst., vol.4,
pp. 4082–4085,2005.
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