Degradation Study of AIGaN/GaN HEMT through
Electro-Thermo-Mechanical Calculations and
Thermo-Reflectance Measurements
by
MA SSAcHUSETTS INSTITUTE
OF TECHNOLOGY
Feng Gao
NOV 19 2010
B.S., Physics (2008)
LIBRARIES
Fudan University
Submitted to the Department of Materials Science and Engineering
in Partial Fulfillment of the Requirements for the Degree of
Master of Science in Materials Science and Engineering
at the
ARCHIVES
Massachusetts Institute of Technology
August 2010
@2010 Massachusetts Institute of Technology
All rights reserved
r
Author
U Department of Materials Science and Engineering
August 13, 2010
Certified by
Tomes Palacios
Associate Professor of Electrical Engineering
Thesis Supervisor
And
'
ari V. Thompson
Professor of Materials Science and Engineering
Thejsis
ader
Accepted by
unnstopher Schuh
Chair, Departmental Committee on Graduate Students
Acknowledgment
First of all, I would like to express my deepest gratitude to my thesis advisor, Prof. Tomas
Palacios. He is one of the most energetic, smartest and kindest people I have ever known. It is
my great fortune to join his group and be his student. During these two years, I learned a lot
from him not only the knowledge of my research but also the characteristics of being a
successful person. I always remember his encouragement when I got frustrated, 'You came to
MIT to be the world expert in research. You have the greatest potential to provide the best
work!' Had it not been his great guidance to my research and considerable support to my life, I
would have never finished this thesis.
Secondly, I would like to thank all my labmates: Bin Lu, Omari Saadat, Han Wang, Will Chung,
Allen Hsu, Mohamed Azize, Kevin Ryu, Daniel Piedra and Benjamin Mailly for all the help and
advice to my research. They are always good resource for ideas and discussions. In addition, I
would like to thank my collaborator Katey Lo in Prof. Rajeev Ram's group for all her great help
in my experiment setup and measurements. I also like to thank my thesis reader, Prof. Carl
Thompson for giving me invaluable advice and suggestive comments in my thesis.
Last but not least, I would like to share this thesis with my parents. Without their warming
support and encouragement, I can hardly make it done. I love you from the bottom of my heart.
This work was made possible by the DRIFT MURI project by the Office of Naval Research and
by the National Reconnaissance Office.
Degradation Study of AIGaN/GaN HEMT
through Electro-Thermo-Mechanical Calculations
and Thermo-Reflectance Measurements
by
Feng Gao
Abstract
During the last few years, AIGaN/GaN high electron mobility transistors (HEMTs) have been
intensively studied for high frequency high power applications. In spite of this great interest,
device reliability is still an important challenge for the wide deployment of AIGaN/GaN HEMT
technology. To fully understand reliability in these devices, it is necessary to consider the
electrical, mechanical and thermal properties of the operating AIGaN/GaN transistors. Since
AIGaN and GaN are both piezoelectric materials, the coupling among electric field, lattice
heating and mechanical characteristics gives rise to large changes in strain field and elastic
energy density in the transistors under the pinch-off conditions. Most previous work have
studied the inverse piezoelectric effect on device degradations, however, quantitative analysis
of this failure mechanism is still needed. In this thesis, we have developed the first fullycoupled electro-thermo-mechanical simulation of AIGaN/GaN HEMTs to study the correlation
between the critical voltages of the gate current degradation and the lattice temperature
distributions of these devices under the reverse-gate-bias reliability testing. In addition, we
have compared the numerical results of our simulations with DC measurements and high
resolution thermo-reflectance images, obtaining excellent agreement for both of them.
Moreover, our studies suggest a covenient and low-cost way to obtain the reliability
characteristics of AIGaN/GaN HEMTs by using the thermo-reflectance measurements of the
lattice temperature distributions for those devices.
Content
5
CHAPTER 1 INTRODUCTIO N .......................................................................................................................................
1.2
BACKGROUND AND M OTIVATION OF RELIABILITY STUDIES ............................................................................
5
7
1.3
THESIS OUTLINES ........................................................................................................------...............
9
1.1 INTRODUCTION OFALGAN/GAN HEM Ts............................................................................................
11
CHAPTER 2 SELF-CONSISTENT ELECTRO-THERMAL SIMULATIONS...........................................................
2.1
INTRODUCTION ..............................................................................................................................---
11
2.2
BASIC SEMICONDUCTOR PHYSICS ..........................................................................................................
11
2.2.1
2.2.2
2.3
11
Poisson's Equation .............................................................................................................................
Carrier Continuity Equations..............................................................................................................12
12
DRIFT-DIFFUSION M ODEL....................................................................................................................
2.3.1 Drift-Diffusion Transport Equations ...............................................................................................
2.4 LATTICE HEATING M ODEL ....................................................................................................................
2.4.1 Lattice Heat Flow Equation ................................................................................................................
2.4.2 M odified Drift-Diffusion Equations ...............................................................................................
2.4.3 Heat Generation Equations................................................................................................................15
2.4.4 Therm al Boundary Conditions ........................................................................................................
2.5
13
14
14
15
16
17
M OBILITY M ODEL ..............................................................................................................................
2.5.1
Low Field M obility M odel of AIGaN/GaN HEIMTs ...........................................................................
18
2.5.2
High Field M obility M odel of AIGaN/GaN HEM Ts...................................................................
19
2.6
20
SIMULATION RESULTS .........................................................................................................................
2.6.1 Transistors Structures ........................................................................................................................
2.6.2 IVCurves.............................................................................................................................................21
2.6.3 Electric Field Distribution ...................................................................................................................
2.6.4 Lattice Tem perature Distribution..................................................................................................
2.7 SUMMARY ........................................................................................................................................
CHAPTER 3 THERM O-REFLECTANCE M EASUREM ENTS................................................................................
21
22
25
26
27
27
3.1
INTRODUCTION ..................................................................................................................................
3.2
THEORY..................................................................................................................................--.-
3.3
EXPERIMENTAL SETUP .........................................................................................................................
28
3.4
EXPERIMENTAL RESULTS......................................................................................................................
29
.. 27
3.4.1 Calibration of Thermo-Reflectance Coefficient..............................................................................
3.4.2 Lattice Tem perature Distribution ..................................................................................................
3.4.3 Experim ent vs. Sim ulation ..................................................................................................................
3.5 DISCUSSION ................................................................................................................................-----3.6 SUMMARY ........................................................................................................................---..---..----
29
31
38
40
41
CHAPTER 4 PIEZOELECTRIC-THERM AL CALCULATIONS.................................................................................
42
4.1 INTRODUCTION ..................................................................................................................................
42
4.2
42
THEORY............................................................................................................................................
3
4.2.1
4.2.2
4.2.3
4.2.4
4.2.5
4.2.6
4.2.7
4.2.8
4.3
CALCULATION RESULTS........................................................................................................................
4.3.1
4.3 .2
4.3.3
4.4
Fundam ental Equation.......................................................................................................................42
Equati ons of State ..............................................................................................................................
Alternative Form ulation .....................................................................................................................
M aterial Properties ............................................................................................................................
Constitutive Relations ........................................................................................................................
Equilibrium Equations ........................................................................................................................
The Boundary Conditions Problem ...............................................................................................
Elastic Energy Density ........................................................................................................................
Strain ..................................................................................................................................................
Stress ..................................................................................................................................................
Elastic Energy Density ........................................................................................................................
SUMMARY ........................................................................................................................................
CHAPTER 5 REVERSE-GATE-BIAS RELIABILITY TESTING .................................................................................
43
44
45
48
53
54
55
57
57
60
62
63
64
5.1
INTRODUCTION ..................................................................................................................................
64
5.2
STRUCTURE OF TESTED TRANSISTORS ...................................................................................................
64
5.3
CALIBRATION OF THERMO-REFLECTANCE COEFFICIENT ..............................................................................
65
5.4
DC M EASUREMENTS OF GATE CURRENT DEGRADATION .........................................................................
65
5.5
THERMO-REFLECTANCE M EASUREMENTS OF DEGRADATION.......................................................................
67
5.6 DISCUSSION ......................................................................................................................................
70
SUMMARY ........................................................................................................................................
72
5.7
CHAPTER 6 CONCLUSIONS AND FUTURE W ORK ................................................................................................
73
6.1
CONCLUSIONS ...................................................................................................................................
73
6.2
FUTURE W ORK ..................................................................................................................................
74
REFERENCE ...................................................................................................................................................................
75
....................................................
..
....
....
............
.. ...
..
.....
I..
...................................
.......
INTRODUCTION
CHAPTER 1
1.1
Introduction of AlGaN/GaN HEMTs
GaN-based high electron mobility transistors (HEMTs) have thrived since their first
demonstration in 1993 [1]. In less than 20 years, they have evolved from devices with less than
20 mA/mm of output current and virtually no high-frequency performance, to devices with
extremely high output power 900W at 2.9GHz and 81W at 9.5GHz, high frequency fT = 225
GHz at Lg = 60nm, high-power efficiency PAE = 75% at Psat = 100W, broadband operation 1.02.5 GHz with 50% efficiency [2] and world-wide commercialization since 2004 [3-6].
The great development and extraordinary performance of GaN-based HEMTs is mainly
because of the outstanding electronic properties of AIGaN/GaN structures.
Characteristic
________________
Bandgjap (eV)
Electron Mobility at 300K
(cm2! Vs)
Saturated (peak) Electron
Velocity (x10 7 cm/s)
Critical Breakdown Field
Silicon IInGaAs
AIGaAs/ IlnGaAsI
nAlAs/
1.1
1.42 ,., 1.35
, ,
(W/cm-K)
3.266
1500
8500
5400
700
1500-
1.0
(1.0)
0.3
1.3
(2.1)
0.4
1.0
(2.3)
0.5
2.0
(2.0)
1.3
(2.1)
3.0
3.0
1.5
0.5
0.7
4.5
>1.5
(MV/cm)
Thermal Conductivity
SiC
15..75.
Table 1.1
As shown in the Table 1.1, AIGaN/GaN structure has high electron mobility (>1500 cm 2N*s at
room temperature) and high electron velocity (-2.5x1 0 7cm/s peak velocity and -1.3x10 7cm/s
saturated velocity). In addition, strong piezoelectric and spontaneous polarization in Ill-nitride
materials results in a high sheet carrier density (normally 0.7-1.4*1013 cm-2) in AIGaN/GaN
hetero-structure without any conventional doping. The high electron mobility and carrier
....
...............
.........
...
I-I.I..-.....,-,",--"",-,-,-,1--l'I",,-"",-
-
-
-
-
_.'
-- *'**
- -
-
hetero-structure without any conventional doping. The high electron mobility and carrier
concentration of AIGaN/GaN HEMTs allow the fabrication of these devices with maximum
drain current densities in excess of 2 A/mm [7].
On the other hand, as a result of the wide band-gap (-3.49 eV) and high breakdown electric
field (>3 MV/cm) of AIGaN/GaN structure, GaN-based HEMTs have very large breakdown
voltage (8300V in [8]). Both high current density and large breakdown voltage are important
requirements for power amplifiers. Moreover, the high electron velocity makes this material
system one of the best candidates for very high frequency operation.
*Miary
100
10
aN
s
0.1
2 GHz
10 GHz
30 GHz
60 GHz
Frequency Band
Figure 1.1-1: Important potential applications for GaN-based power transistors
Figure 1.1 summarizes some of the multiple commercial and military applications that could
benefit from the use of AIGaN/GaN HEMTs as power devices. As shown above, these
transistors can be used in many applications requiring high frequency and high power
operations. At lower frequencies, AIGaN/GaN HEMTs are being pursued for power-switching
applications [9] and even for biological [10] and chemical/physical sensors [11]. At higher
frequencies, the performance of AIGaN/GaN HEMTs has been evolving very fast over the last
20 years. A maximum current gain cut-off frequency (fT) of 163 GHz was reported in
AIGaN/GaN HEMTs with a gate length in the 60-90 nm range [12]. When biased for maximum
__
power gain, these devices could reach 230 GHz of maximum power gain cut-off frequency
(fmax) [13].
The last 20 years has also witnessed the great progress of the output power and power added
efficiency (PAE) in GaN devices as power amplifiers. Currently, AIGaN/GaN HEMTs have
been already commercially available for power amplification in cell-phone base stations at
2GHz and a total output power in excess of 280W have been reported at that frequency [14].
At 4GHz, AIGaN/GaN HEMTs have demonstrated more than 32 W mm' of output power with
a PAE of 54.8% at Vds=120V [15]. This performance is more than one order of magnitude
better than those of any other competing semiconductor technology such GaAs and InP.
1.2 Background and Motivation of Reliability Studies
While GaN-based HEMTs are routinely presenting excellent performance, the greatest
challenge for the wide deployment has been, and remains, achieving a high level of reliability
and stability concurrently with high-performance operation [16].
First of all, improvements in reliability require a better understanding of the failure mechanisms
of GaN-based HEMTs. Years of research into this area have identified the following major
degradation modes, which can represent the peculiarities of the physics of GaN devices, the
imperfection of the materials and the stability of the fabrication processes:
" Schottky and Ohmic Contacts Degradation
* Surface Trapping-induced Degradation
*
Hot Electron-induced Degradation
* Inverse Piezoelectric-induced Degradation
These four failure modes are also schematically demonstrated in a cross section of a typical
AIGaN/GaN HEMT in the figure below, identifying critical areas which can be subjected to the
degradation.
.........-.
.........
........
Schottky Contacts
Degradation
Surface Trapping-induce
Degradation
Ohmic Contacts
Degradation
Hot Electron-induced
Degradation
Inverse Piezoelectricinduced
Degradation
Figure 1.2-1: Schematic cross section of an AIGaN/GaN HEMT. Critical areas subjected to degradation are
identified by arrows.
Although the 'gate sinking' resulting from the unstable Schottky contacts was identified as one
of the major failure mechanisms of GaAs MESFETs and HEMTs, the Schottky contacts on
GaN appear to be normally stable and no 'gate sinking' effect of DC bias has been reported
until now, despite of some findings of changes in the Schottky barrier height after some
thermal treatments [17],[18]. For the ohmic contacts, minor degradation with less than 2%
variation of fresh condition was found during a 2000-h thermal storage test in the nitrogen
atmosphere at 340*C [19]. A more systematic study of the stability of the Schottky and ohmic
contacts is still needed, but this kind of degradation is much more moderate compared to the
others.
Surface trapping-detrapping of electrons at surface states has been suggested as a possible
mechanism responsible for the RF current slump and dispersion, which lead in changes of the
maximum drain current and knee voltage resulting in reduced power and gain. This kind of
trapping can compensate part of the surface component of the spontaneous polarization
..............
.
...
I.
I.
-I
-...........
-....
.1
working as a 'virtual gate' between the actual gate and drain, and hence reduce the 2DEG
electron concentration [20].
Another well-know failure mechanism of GaAs-based devices is the hot electron-induced
device aging [21],[22], which has also been invoked to explain the current collapse and gatelag effects in GaN-based HEMTs. There are many excellent work reviewing on this topic,
especially those working on the characterization of hot-electron effects by the
electroluminescence (EL) microscopy [23].
In this thesis, we study in detail the degradation due to inverse piezoelectric effect. Since the
uniqueness of the GaN-based HEMTs, high vertical electric field is created at the drain edge of
the gate, which would be seen in our simulations and measurements later. When the electric
field or the applied voltage reach a critical value, the gate leakage current starts to jump
resulting from the trap generations. And eventually strain relaxation and crystallographic defect
formation take place in the device layers. A specific hypothesis relating to the inverse
piezoelectric effect has been recently formulated by some authors [24],[25], however, an
accurate and complete understanding of the physics behind this degradation mechanisms is
still needed. In this thesis, we present a simulation, modeling and measurement framework for
the purpose of studying this piezoelectric induce degradation. We have also identified thermoreflectance measurements is a powerful technique to evaluate device reliability.
1.3
Thesis Outlines
The thesis is organized in the following way:
In Chapter 2, we develop self-consistent electro-thermal simulations of GaN-based HEMTs in
order to estimate the electric field and lattice temperature of two types of fabricated devices.
The simulated and measured IV curves of those devices are compared to evaluate the
accuracy of the simulations.
In Chapter 3, we use for the first time thermal-reflectance measurements of the surface lattice
temperature of the AIGaN/GaN HEMTs to test the accuracy of the thermal part of the
simulations developed in Chapter 2. The experimental results of the peak lattice temperature
match the previous simulation data very well. Moreover, we found an interesting feature of the
thermal-reflectance measurements that could be used as an easy and fast tool for the
reliability testing of the AIGaN/GaN HEMTs.
In Chapter 4, with the simulation data of the electric field and lattice temperature obtained in
Chapter 2 and verified in Chapter 3, we established a new piezoelectric-thermal model for the
calculations of the mechanical characteristics such as strain, stress and elastic energy density
in the AIGaN layer of a HEMT under various bias conditions, which are very important for the
prediction of the reliability in the failure modes of the inverse piezoelectric-induced degradation.
In Chapter 5, we use thermo-reflectance measurements to study device degradation as a
function of reverse-gate-bias step stress.
CHAPTER 2
SELF-CONSISTENT ELECTRO-THERMAL SIMULATIONS
2.1 Introduction
Through decades of research in semiconductor physics, a basic set of equations and models
has been developed to understand and predict the performance of semiconductor devices
including GaN-based HEMTs [26]. The commercial software Silvaco Atlas is a device simulator
which incorporate many of these equations [27], and we have used it to simulate the electrical
and thermal characteristics of the AIGaN/GaN transistors we fabricated in lab to obtain the
electric field and lattice temperature distributions in the cross section of the devices and to
analyze key features in the AIGaN layer that will be investigated in the latter chapter.
2.2
Basic Semiconductor Physics
Inthis section, the basic equations used by our device simulator are reviewed.
2.2.lPoisson's Equation
Poisson's equation is one of the most fundamental equations in the theory of semiconductor
devices [26]. It has the following form:
div(EV y/) = -p
(2.2.1-1)
where tp is the electrostatic potential, E is the local permittivity and p is the local space charge
density. Poisson's equation relates the electrostatic potential to the space charge density. The
reference potential can be defined in various ways. For the software Silvaco Atlas that we are
using in the thesis, the reference potential is always the intrinsic Fermi potential of the device
[27].
2.2.2 Carrier Continuity Equations
The carrier continuity equations are another set of fundamental equations of device physics
which have the following simple and very intuitive forms [26]:
oh 1
-=-div , + G - R
(2.2.2-1)
q
-divJP,+ G, - R,
(2.2.2-2)
where n and p are the electron and hole concentration, Jn and Jp are the electron and hole
current densities, Go and Gp are the generation rates for electrons and holes, Ra and Rp are
the recombination rates for electrons and holes.
Carrier continuity equations connect the carrier concentration to the carrier current densities
and generation-recombination rates, offering an important link to the device performance.
2.3
Drift-Diffusion Model
Poisson's equation and carrier continuity equations provide the general framework for
semiconductor device simulations. But they are not sufficient to simulate devices. Further
secondary equations are needed to specify particular models for current densities and
generation-recombination rates.
The current-density equations, or charge transport models, are usually obtained by applying
approximations and simplifications to the Boltzmann transport equation [28]. Those
assumptions can result in a number of different transport models such as the drift-diffusion
model, the energy balance transport model or the hydrodynamic model.
In this thesis, we use the simplest model of charge transport, the drift-diffusion model, which is
accurate enough for our simulations of the electrical characteristics of GaN-based transistors.
As we will see in the later part of this chapter, excellent agreement between simulations and
experiments have been obtained.
2.3.1 Drift-Diffusion Transport Equations
In the framework of the drift-diffusion model [28], the current densities are expressed in terms
of the quasi-Fermi levels On and Op as the following:
Jn = -qpnnV
#n
(2.3.1-1)
JP = -qp pV
#,
(2.3.1-2)
where pn and pp are the electron and hole mobilities. The quasi-Fermi levels On and Op are
linked to the carrier concentrations and the potential through Boltzmann approximations:
n = n i, exp
kTL -
2313
p = ni, exp
(2.3.1-4)
k TL-
_
where nie is the effective intrinsic concentration, TL is the lattice temperature and tp is the
electrostatic potential. These two equations can be re-written to define the quasi-Fermi
potentials:
kT
n
, = V_ TL in
q
(2.3.1-5)
nie
O, - V k in p
q
(2.3.1-6)
ni
By substituting these equations into the equation 2.3.1-1 and the equation 2.3.1-2, the
following conventional formulas of the drift-diffusion transport equations are obtained:
J= qnpE +qDVn
5n
V
kT
(2.3.1-7)
q
J, = qppE, -qDVp,
Z,
=-V(v_
kL Ine(2318)
q
If we are not considering the lattice heating effect, we just set the local lattice temperature as
constant e.g. 295K, and self-consistently solve the three sets of equations (Poisson's equation,
carrier continuity equations and drift-diffusion transport equations) under specific device
domains and structures, to get all of the electrical characteristics such as electrostatic
potential, electric field, current densities, etc in the device.
Although these simulations results match the measurements quite well under low bias
conditions, at higher bias, as the lattice heating plays a more and more important role to the
electrical performance of the real device, this model becomes inaccurate (see the black
dashed line in Figure 2.6.2-1 and 2.6.2-2 in the latter section). In addition, these simulation
results do not include any data on the lattice temperature of the device, which will be heavily
used in our further calculations in the latter chapters. So, it is necessary to introduce another
two important models: lattice heating model and mobility model into our simulations.
2.4 Lattice Heating Model
Silvaco Atlas allows us to calculate the lattice temperature distributions in semiconductor
devices using its lattice heating model [27]. This model consists of several sets of heat-transfer
related equations, which can be combined with the drift-diffusion model for self-consistent
simulations.
2.4.1 Lattice Heat Flow Equation
The first fundamental equation of the lattice heating model is the intuitive lattice heat flow
equation:
C
=V(V TL)+ H
(2.4.1-1)
And in the steady state:
V(KVTL) + H = 0
where C is the heat capacitance per unit volume,
generation and TL is the local lattice temperature.
(2.4.1-2)
K iSthe
thermal conductivity, H is the heat
2.4.2 Modified Drift-Diffusion Equations
In the framework of the lattice heating model, the electron and hole current densities are
modified to account for the spatially varying lattice temperatures:
J= -qn(V, +PVTL)
(2.4.2-1)
J, = -qpp(V$, + PVTL)
(2.4.2-2)
where Po and Pp are the absolute thermoelectric powers for electrons and holes.
Conventionally, Pn and Pp are modeled as follows [27]:
k
q
P
n
N,
(ln
3
2
-
(2.4.2-4)
)
For simplicity and fast convergence of the simulation, in this thesis we will just use the normal
drift-diffusion equations as the equations 2.3.1-7 and 2.3.1-8.
2.4.3 Heat Generation Equations
When carrier transport is handled in the drift-diffusion model, the heat generation term, H, has
the following form:
H =q"
+q
"
-qT(J,,VP,))+qTL
JpVPp)+q(R -G)[TL
pp
pann
-qTL Ird
+
+ Pn ]divJn -qTL
n,p
bnJ
-IT
-)&
P
(
p
n,p
and in the steady state, the current divergence can be replaced with the net recombination.
Equation 2.4.3-1 then simplifies to:
+q(R-G)[p, -,
+q
H=[q
lnn
p+TL (Pp
(2.4.3-2)
lpp
In the above equation, the heat generation could be separated into three terms, each of which
has its own physical meaning:
"
q
+q
lnn
is the Joule heating term;
ppp
is the recombination-generation heating and cooling term;
*
q(R - G)[#, -
*
-qTL(JnVPn +JPVPp)is the term of the Peltier and Thomason effects.
n+ TL (P
-Pn)]
In our simulations, also for the reason of easy and fast convergence, we only calculate the
Joule heating term for the heat generation. This term can be re-written in a simpler and form as
follows:
H = (Jn + J,) - E
(2.4.3-3)
2.4.4 Thermal Boundary Conditions
To solve the lattice heat flow equation in the device domain, the thermal boundary conditions
must be specified:
( J,,, 5)
a(T - T,)t
(2.4.4-1)
where a is either 0 or 1,Jtot is the total energy flux and s is the unit of the external normal of the
boundary.
The projection of the energy flux onto s is:
(J -i)
L + (TLpn
0
+ On)jn
+ (TLpp + Op)jp
(2.4.4-2)
When a=0, equation 2.4.4-2 specifies a Dirichlet boundary condition (fixed boundary
temperature).
In this thesis work, we use Dirichlet boundary condition for all thermal simulations, which
implies that we set the bottom of the device substrate at fixed room temperature 295K.
2.5 Mobility Model
Electrons and holes are accelerated by electric fields, but lose momentum as a result of
various scattering processes. These scattering mechanisms include lattice vibrations
(phonons), impurity ions, other carriers, surfaces, and other material imperfections. Since the
effects of all of these microscopic phenomena are lumped into the macroscopic mobilities
introduced by the transport equations, these mobilites are therefore functions of the local
electric field, lattice temperature, doping concentration, and so on.
Mobility modeling is normally divided into two areas:
* Low field behavior
* High field behavior
The low electric field behavior has carriers almost in equilibrium with the lattice and mobility
has a characteristic low-field value that is commonly denoted by the symbol Pno,po. The value of
this mobility is dependent on phonon (lattice temperature) and impurity scattering (impurity
concentration), both of which act to decrease the low field mobility.
The high electric field behavior shows that the carrier mobility declines with the electric field
because the carriers that gain energy can take part in a wider range of scattering processes.
The mean drift velocity no longer increases linearly with the increasing electric field, but rises
more slowly. Eventually, the velocity does not increase any more with the increasing field but
otherwise drops and at the end it saturates at a constant velocity. This constant velocity is
commonly denoted by the symbol vsat. This behavior can be well modeled by the Monte Carlo
Simulations shown in the Figure 2.5-1 below:
...........................................
...........................
x
2.5-
Velocity Saturation Model of
AIGaN/GaN HEMTs
e
0'
0.5
@T=300K
0
0.2
0.4
1.4
1.2
1
0.8
0.6
Lateral Electric Field (MV/cm)
1.6
1.8
2
Figure 2.5-1: Monte Carlo simulations of the electron velocity in AIGaN/GaN
HEMTs as a function of the lateral electric field [29].
2.5.1 Low Field Mobility Model of AlGaN/GaN HEMTs
Based on the Monte Carlo simulations [29], the general expression for the low field mobility of
AIGaN/GaN transistors used in the drift-diffusion simulations can be fitted :
yo(TL,N) =p'in
-~
fl4(2.5.1-1)
where TL is the local lattice temperature and N is the local (total) impurity concentration. The
values of a, @1, P2, 13, 04, pmin, Pmax, Nret that we used in out simulations are listed in the
following table:
modeled by equation (2.5.1-1) is plotted in the Figure 2.5.1-1:
Al3aN/fUaN ritiVi IS
~700
600
o500
e
r,400
300
200
310
3
32
370
350 3
3
Lattice Temperature / K
380
390
400
Figure 2.5.1-1: Low field electron mobility in AIGaN/GaN HEMTs as a
function of the lattice temperature.
From the figure above, we can see that the low field electron mobility in GaN drops from -1000
cm 2N*s to -130 cm2N*s as the lattice temperature increases from 300K to 400K.
2.5.2 High Field Mobility Model of AlGaN/GaN HEMTs
According to the reference [29], the general expression for the high field mobility of
AIGaN/GaN transistors used in the drift-diffusion simulations has the following formulation:
o ( TL,N ) +
=
E
a -1+
E C)
n2
v
a
E n -1"
E
+L-
(2.5.2-1)
ni
EC
where po(TL,N) is the low field mobility modeled in equation 2.5.1-1, and E is the local electric
field. The values of vsat, a, n1, n2, Ec we used in our simulations are listed in the following table:
vsat(10cm I s)
GaN
1.3
a
n,
n2
E,(kV /cm)
7.0
4.5
0.7
215
The high field mobility behavior modeled by the equation (2.5.2-1) is plotted in the Figure
2.5.2-1:
............
....
.... ...
1000
900
800
High Field Mobility Model of
AIGaN/GaN HEMTs
700
E 600
500
C 400
e
LLI00
@T=300K
100
00
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
Lateral Electric Field / (MV/cm)
Figure 2.5.2-1: Electron mobility in AIGaN/GaN HEMTs as a function of the
lateral electric field at T=300K.
From the figure above, we can see that the high field electron mobility in GaN drops from
-1000 cm2N*s to -0 cm 2N*s (i.e the electron velocity saturates) as the lateral electric field
increases from 0 to 2 MV/cm at 300K.
2.6 Simulation Results
Using the drift-diffusion model, lattice heating model and specific mobility models for
AIGaN/GaN HEMTs and correctly setting all of the material parameters including band gap,
density of states, electron affinity, permittivity, thermal conductivity, etc., we have simulated the
electric field and lattice temperature distribution. There is a lot of excellent work in the literature
regarding the simulations of the electrical performance of AIGaN/GaN HEMTs [30] [31], but
very little on the simulations of the thermal performance [32]. Therefore, this chapter of the
thesis focuses mainly on the lattice temperature simulations of the AIGaN/GaN transistors. It
also discusses the electrical performance of the devices to test the accuracy of the physical
models used.
..
......
...
2.6.1 Transistors Structures
The simulated transistors have exactly the same structures of our real AIGaN/GaN HEMTs,
which were fabricated following our standard technology. In order to investigate into the effect
of different substrates on the lattice temperature distribution in the device, we fabricated the
same AIGaN/GaN HEMTs structures on SiC (transistor A) and Silicon substrates (transistor B)
respectively. The following figures show the structures of our two types of transistors:
2pim
2pm
Figure 2.6.1-1: Schematic structure of Transistor A
Figure 2.6.1-2: Schematic structure of Transistor B
2.6.2 IV Curves
The DC current measurements and the simulation data of Transistor A and Transistor B are
shown in the Figure 2.6.2-1 and 2.6.2-2. We can see that the experimental and simulated IV
curves of both transistors are in perfect agreement and a clear difference between using
models with and without lattice heating models (black dashed lines).
_
. --:::-:::::::
:: ; : : _:-Z;-::::::::::
"_::::
::::::
--
...
.- ..........
............
.
.....
- experimert
simulation
T sLattice heating effect
TransistcirA
600
I
E
~2W
ISO
6
3W
02
7
8
9
1
100
50
1
Vds I V
Figure 2.6.2-1: Measured (dot) and simulated (solid
line) IV curves of transistor A. The black dashed line
indicates the calculated IV curve at Vgs=2V without
lattice heating models.
2
3
4
6
5
Vd
i
7
8
9
10
V
Figure 2.6.2-2: Measured (dot) and simulated (solid
line) IV curves of transistor B. The black dashed line
indicates the calculated IV curve at Vgs=2V without
lattice heating models.
From the IV curves above, we also find that the drain-to-source current of Transistor A is larger
than in Transistor B. This is because of the better quality and lower defects densities of the
sample grown on the SiC substrate, which create fewer buffer traps than in the sample grown
on the Silicon substrate.
The excellent agreement between the experiment and simulation results of the DC
performance of the AIGaN/GaN HEMTs provide a strong proof of the accuracy of the physical
models we are using in the simulations and also validate the framework of the self-consistent
electro-thermal method used to simulate the electric field and the lattice temperature
distribution in the AIGaN/GaN HEMTs, both of which are much more difficult to measure in
reality.
2.6.3 Electric Field Distribution
The vertical and lateral electric fields across the device in the AIGaN lattice above the channel
are extracted from the simulation data for both transistors:
2
- ---Vg=V Vd=12V
-
VpfWVVds=15
---Vgs=0Vs=15y
---
vgs=uy vOs-Ie
Vgs=OVVds=15V
2- -Vg
s4Vd s-1I8V
1C'1.5
5
0.5
Source
1
0
L
Gate
15
2
26
Microns
3
36
Drain
4
Source
45
W5
1
Gate
_
2.5
Microns
15
Drain
_
3
3.5
4
4.5
Figure 2.6.3-1: Simulation of the vertical electric field Figure 2.6.3-2: Simulation of the vertical electric field
along the AIGaN layer of transistor A under increasing along the AIGaN layer of transistor B under increasing
drain-to-source bias at Vgs=OV.
drain-to-source bias at Vgs=OV.
-
-
Vgs-OV Vdsw3V
i2 -
--
1
-
-o
-Vgt=V Vds=3V
Vgs=V Vds=6V
Vs=0V Vds=9V
TransistorA
Vgs=VVds=6V
--
Vgs=0V Vds=9V
Vgs=cV Vds=12V
Vgs=0V Vds-15V
Vg=V Vd=18V
-
Transistor B
Vgs=OV Vds=12V
--
Vgs=V Vds=15V
Vgs9OVds=1V
0
I1
0.68
3 0.4
e-
Source
4
:
Gate
Source
:
Gate
0
-
Drain -,
Drain -+
I. ~
1
1.5
2
2.5
Microns
3
3.5
4
4.5
W5S
1
1,5
2
2.5
Microns
3
3.5
4
4.5
Figure 2.6.3-3: Simulation of the lateral electric field Figure 2.6.3-4: Simulation of the lateral electric field
along the AIGaN layer of transistor A under increasing along the AIGaN layer of transistor B under increasing
drain-to-source bias at Vgs=OV.
drain-to-source bias at Vgs=OV.
23
2.5
-Vg-2V
-
Vds=16V
---
7
Vgs-3VVde=18V
Vgs=-3V Vds=18V
.
.5
.
w
0-6os--
Source
Drain
0.5S- Source
Drain
Gate
1
5
1.5
2
2.6
Gate
3
3.5
4
4.5
Microns
B6
1.6
2
2.6
Micrors
3
3'
A
46
Figure 2.6.3-5: Simulation of the vertical electric field Figure 2.6.3-6: Simulation of the vertical electric field
along the AIGaN layer of transistor A under decreasing along the AIGaN layer of transistor B under decreasing
gate-to-source bias at Vds=18V.
gate-to-source bias at Vds=1 8V.
Vgs=2V Vds=18V
1.6
14
-
TransistorA
-- Vgs=VVds1BV
Vgs=(V Vds=18V
Vgs-lVVds18V
Vgs=OV Vds=18V
VgS-1VVds=18V
6
Vg--t VVds=18V
Vgs=-2VVds=18V
V_-2VVds=18V
4
Vgs--3V Vde-18V
12 -Vgs-3V
Vds=18V
2
6
0.6
0. 4
0.4
0.2
WS
Transistor [!
Source
1
1.5
2
2.5
Microns
2-Source
Drain
Gate
3
3.5
4
45
i
;Gate
1A
2
25
Drain --
-3
3.5
A
A
Microns
Figure 2.6.3-7: Simulation of the lateral electric field Figure 2.6.3-8: Simulation of the lateral electric field
along the AIGaN layer of transistor A under decreasing along the AlGaN layer of transistor B under decreasing
gate -to-source bias at Vds=1 8V.
gate -to-source bias at Vds=18V.
From the figures above, both the lateral and vertical electric fields peak at the drain edge of the
gate, rise as the increasing drain-to-source voltage and drop as the decreasing gate-to-source
voltage. In addition, the very similar electric field profiles of Transistor A and Transistor B result
from the same device scales and structures regardless of the different substrates and defect
densities.
2.6.4 Lattice Temperature Distribution
The lattice temperature distributions across the device in the AIGaN layer above the channel
are also extracted from the simulation data for both transistors:
3N .
I
I
I
1
330
.
315
'310
2
5
3,5
25A
Microns
4
2.5
Microns
45
Figure 2.6.4-1: Simulation value of the lattice Figure 2.6.4-2: Simulation value of the lattice
temperature along the AIGaN layer of transistor A temperature along the AIGaN layer of transistor B
under increasing drain-to-source bias at Vgs=OV.
under increasing drain-to-source bias at Vgs=OV.
3Z-
Vgs-3VVds-I8V
3-
310
305
1
1.
2
2.
3
3.
4
45
05
Microns
300-
4
1
5
Gate
2
2.5
Micrers
3
3.5
4
4.6
Figure 2.6.4-3: Simulation value of the lattice Figure 2.6.4-4: Simulation value of the lattice
temperature along the AIGaN layer of transistor A temperature along the AIGaN layer of transistor B
under decreasing gate-to-source bias at Vds=18V.
under decreasing gate-to-source bias at Vds=1 8V.
In these figures, we also find that the peak lattice temperature happen at the drain edge of the
gate for both transistors. The reason for this is that the peak lateral electric field in the channel
at the drain edge of the gate generates the highest heat dissipation therefore the highest lattice
temperature, as demonstrated in equation 2.4.3-3. Moreover, from the equation 2.4.3-3 and
2.4.1-2, we can see that for the same material (same thermal conductivity), the lattice
temperature is proportional to the output power in the device. Therefore, since the current of
the Transistor A is larger than that of the Transistor B under the same bias conditions, the
lattice temperature of Transistor A should be larger than that of the Transistor B. However, this
is not the case in the figures from 2.6.4-1 to 2.6.4-4, where the lattice temperatures of
Transistor A are almost the same as those of Transistor B under the same bias conditions.
Actually, this is exactly what we want to see. Due to the fact that the thermal conductivity of
SiC material is nearly four times larger than the thermal conductivity of Silicon material, heat,
is therefore more easily dissipated from the device into the substrate for Transistor A, causing
the lattice temperatures along the channel drop faster despite of the higher power.
2.7 Summary
In conclusion, by using the commercial software Silvaco Atlas, we successfully modeled and
simulated the electrical and thermal characteristics of the standard AIGaN/GaN HEMTs, which
were fabricated on wafers with different substrates (SiC and Silicon). The simulated drain
current of the devices matches perfectly with the experimental data, and the effect of the
substrate on the lattice temperatures in device performance was also simulated in the
simulations as expected. To provide more confidence in this self-consistent electro-thermal
simulation, the lattice temperatures data generated in this chapter will be compared with the
measurement results in Chapter 3.
CHAPTER 3
THERMO-REFLECTANCE MEASUREMENTS
3.1 Introduction
Thermo-reflectance microscopy is an important imaging tool for measuring surface
temperature distributions [33]. Since it does not require direct physical contact of the surface
as opposed to the use of thermocouples, and it offers better spatial resolution than IR (infrared)
thermal imaging, and micro-Raman spectroscopy [34], thermo-reflectance microscopy finds
many applications in physics and engineering, such as device failure analysis and design
optimization [35].
3.2
Theory
Thermo-reflectance microscopy is based on the fact that the reflectivity of a surface depends
weakly on its temperature. To first order, the fractional change in the sample's reflectivity ARIR
( AR refers to the change in reflectivity and R is the total reflectivity) in response to surface
temperature variations AT is proportional to AT:
A 1=
AT
where
R oT
=R4R
18AR
AR
R
R
(3.2-1)
# is the so-called thermo-reflectance coefficient, a characteristic of the specific material
[36] and wavelength of illumination [37]. Knowledge of the material-dependent thermoreflectance coefficient , which has typical value ranging from 10' to IV K-', enables the
calculation of AT from the measured ARIR.
:..............
............
. .............
3.3 Experimental Setup
The setup of the thermo-reflectance measurements is schematically shown in the figures
below:
CCD Camera
CCD Camer
LiLght
h
Light Source1
Figure 3.3-1: Schematic diagram of the thermo- Figure 3.3-2: Schematic diagram of the thermoreflectance imaging apparatus used for the reflectance imaging apparatus for the calibration of the
measurement of AIGaN/GaN transistor.
thermo-reflectance coefficient of the surface material.
A light-emitting diode (LED) is used to illuminate the surface of the tested devices. The
reflected LED light is collected through a standard reflectance-mode microscope objective and
imaged onto a CCD array with a resolution of 652x400 pixels. An optical spatial resolution of
150±10 nm is obtained using 467nm (blue) LED light, and a 100x, NA=0.8 microscope
objective, which is in quantitative agreement with Sparrow's criterion.
The temperature of the sample in Figure 3.3-1 is modulated using a square voltage source of
frequency co. The CCD camera then takes images of the sample at a frequency phase-locked
to the excitation. To detect the amplitude of Joule heating, the camera takes images of the
device at a trigger frequency of 8M, since the temperature change from this heating has a
frequency of 2w. In this case the sequential images (each separated by a difference of rr/2 of
the phase of the temperature oscillation) are accumulated in 4 image buffers, denoted as 11, 12,
13, and 14. The main quantity of interest is the magnitude normalized change in reflectance R,
denoted AR/R, and related to the image buffers by:
28
AR
zr
(I -1I3)2+(I2_) 2
R
- 2
I, + I2 + I, +
(3.3-1)
4
Once the ARIR image is obtained, it remains to calibrate the ARIR map to the temperature
scale.
The system of calibration is shown in Figure 3.3-2. A flat, uniform sample of the material of
interest (GaN cap layer for Transistor A and Transistor B) is placed on a thermo-couple
attached with a heat sink (a bulk of copper). The temperature of the thermo-couple (and the
sample) is modulated using a square voltage bias. A thermo-reflectance image of the sample
is obtained in the above manner. A small thermocouple is used in order to ensure good
thermal contact, for fast response time, and to minimize any error in the temperature
measurement caused by parasitic heat conduction through the thermocouple wires. A low
numerical aperture lens is used to avoid parasitic effects due to sample motion from thermal
expansion. The (uniform) thermo-reflectance amplitude is then divided by the amplitude of the
temperature oscillation as determined by the thermocouple, giving the thermo-reflectance
coefficient P. Thermo-reflectance maps of the material can then be easily converted to
temperature images.
3.4 Experimental Results
In this section of the chapter, the first thermo-reflectance images of AIGaN/GaN HEMTs are
demonstrated and analyzed. These high-resolution images (-100nm) of lattice temperature
provide a lot of information of the measured device including the important defects densities
and distributions, which have. traditionally been very difficult to test.
3.4.1 Calibration of Thermo-Reflectance Coefficient
Based on the fact that different materials have different thermo-reflectance coefficients [36], in
order to obtain the lattice temperature maps on the GaN cap layer of Transistor A and
Transistor B, calibration of the GaN surface material is needed. Since the thermo-reflectance
coefficient also slightly changes with temperature, we measured the variation of the thermoreflectivity as a function of the variation of the temperature at 300K, 320K and 340K. The
results are shown in the figures below respectively.
0.000s5 -
GaN @ T = 300K
0.00050
-
0.00045 -
0.00040 -
=
(2.64±0.30)x104
0.00035-
0.00030 ).4
0.6
0.8
1.0
1.2
1.4
Figure 3.4.1-1: Variation of the thermo-reflectivity as a function of the variation of the lattice
temperature measured on GaN sample and started with 300K. The slope of the fitting line is the
thermo-reflectance coefficient.
0.0011 -
GaN @ T = 320K
0.0010 -
0.0009 -
0.0008
0.00071
P=
(2.70±0.08)xlO-4
0.0006-
0.00051
,T
2.0
I
2.5
3.0
3.5
4.0
4.5
AT
Figure 3.4.1-2: Variation of the thermo-reflectivity as a function of the variation of the lattice
temperature measured on GaN sample and started with 320K. The slope of the fitting line is the
thermo-reflectance coefficient.
..................
0.0020
GaN @ T = 340K
a
0.0018-
0,0016-
0.0014 -
0.0012 -f
=
(2.80±0.83)x104
0.0010 1.0
1.5
2.0
2.5
3.0
3.5
4.0
\T
Figure 3.4.1-3: Variation of the thermo-reflectivity as a function of the variation of the lattice
temperature measured on GaN sample and started with 340K. The slope of the fitting line is the
thermo-reflectance coefficient.
We find that the linear relationship of AR/R and AT holds well for the temperature rages of
interest and the thermo-reflectance coefficient varies very little (<10%), which gives us an error
of less than 2% (-5K) in ternerature. Jherefore, it is statistically reasonable to treat the
average thermo-reflectance coefficient measured by the calibration as the theoretical one
involved in the temperature calculation. By averaging the data above, we obtain a thermoreflectance coefficient of 2.73x1 0-4 K-1 for GaN material under the 467nm (blue) LED light.
3.4.2 Lattice Temperature Distribution
Using the thermo-reflectance coefficient obtained in the calibration and converting the thermoreflectivity maps into lattice temperature, we obtained accurate data for the lattice temperature
distribution on the GaN cap layer of Transistor A and Transistor B.
Figures 3.4.2-1 to 3.4.2-12 show the lattice temperature profiles of Transistor A and Transistor
B from Vds=3V to Vds=1 8V (step 3V) at Vgs=OV. The scales of the GaN cap layer bands in
each image are 1.5 pm wide and 40 pm long and the resolution is about 150 nm.
Transistor A
Transistor B
K
TVmpr"*- /
Drain
:5
Drain
3M0
326
320
316
310
3M5
3M6
Figure 3.4.2-1: Top view of the lattice temperature
distribution on the GaN cap layer of Transistor A
at Vgs=OV, Vds=3V.
I
Drain
Figure 3.4.2-2: Top view of the lattice temperature
distribution on the GaN cap layer of Transistor B
at Vgs=OV, Vds=3V.
I
9mper1ure/K
3A5
340
Drain
3315
30
326
320
Gate
316
1U
206
Source
Figure 3.4.2-3: Top view of the lattice temperature
distribution on the GaN cap layer of Transistor A
at Vgs=OV, Vds=6V.
I
Drain
Figure 3.4.2-4: Top view of the lattice temperature
distribution on the GaN cap layer of Transistor B
at Vgs=OV, Vds=6V.
'
erx/
K
346
3410
Drain
336
3M0
326
X20
310
306
3011)
295
Figure 3.4.2-5: Top view of the lattice temperature
distribution on the GaN cap layer of Transistor A
at Vgs=OV, Vds=9V.
Figure 3.4.2-6: Top view of the lattice temperature
distribution on the GaN cap layer of Transistor B
at Vgs=OV, Vds=9V.
1Umpeture/K
Drain
3A"
340
I
Drain
336
3130
Gate
326
320
310
Source
306
Figure 3.4.2-7: Top view of the lattice temperature
distribution on the GaN cap layer of Transistor A
at Vgs=OV, Vds=1 2V.
Drain
Figure 3.4.2-8: Top view of the lattice temperature
distribution on the GaN cap layer of Transistor B
at Vgs=OV, Vds=12V.
3'46
340
I
Drain
Gate
316
310
Source
306
Figure 3.4.2-9: Top view of the lattice temperature
distribution on the GaN cap layer of Transistor A
at Vgs=OV, Vds=1 5V.
Drain
Figure 3.4.2-10: Top view of the lattice
temperature distribution on the GaN cap layer of
Transistor B at Vgs=OV, Vds=15V.
T Jvcab
340
I
Drain
326
320
315
30
Source
Figure 3.4.2-11: Top view of the lattice
temperature distribution on the GaN cap layer of
Transistor Aat Vgs=OV, Vds=1 8V.
300
Figure 3.4.2-12: Top view of the lattice
temperature distribution on the GaN cap layer of
Transistor B at Vgs=OV, Vds=1 8V.
Figures 3.4.2-13 to 3.4.2-23 below show the lattice temperature profiles of Transistor A and
Transistor B from Vgs=2V to Vgs=-3V (step -1V) at Vds=1 8V. The dimentsions of the GaN cap
layer bands in each image are also 1.5 pm wide and 40 pm long and the resolution is still
about 150 nm.
Transistor A
Drain
Gate
Source
Figure 3.4.2-13: Top view of the lattice temperature distribution on the GaN cap layer of Transistor A
at Vgs=2V, Vds=1 8V.
Drain
Gate
Source
Figure 3.4.2-14: Top view of the lattice temperature distribution on the GaN cap layer of Transistor A
at Vgs=1V, Vds=1 8V.
Temprature/ K
Drain
Gate
Source
Figure 3.4.2-1.5: Top view of the lattice temperature distribution on the GaN cap layer of Transistor A
at Vgs=0V, Vds= 18V.
Tempermur/
K
Drain
Gate
Source
Figure 3.4.2-16: Top view of the lattice temperature distribution on the GaN cap layer of Transistor A
at Vgs=-1V, Vds=1 8V.
Temperature/K
Drain
326
320
Gate
315
310
30S
Source
Figure 3.4.2-17: Top view of the lattice temperature distribution on the GaN cap layer of Transistor A
at Vgs=-2V, Vds=1 8V.
Drain
Gate
Source
Figure 3.4.2-18: Top view of the lattice temperature distribution on the GaN cap layer of Transistor A
at Vgs=-3V, Vds= 18V.
amo
Transistor B
Drain
TempetuM I
-370
Gate
Source
Figure 3.4.2-19: Top view of the lattice temperature distribution on the GaN cap layer of Transistor B
at Vgs=1V, Vds=1 8V.
Drain
Gate
Source
Figure 3.4.2-20: Top view of the lattice temperature distribution on the GaN cap layer of Transistor B
at Vgs=0V, Vds=18V.
Drain
Gate
Source
Figure 3.4.2-21: Top view of the lattice temperature distribution on the GaN cap layer of Transistor B
at Vgs=- 1V, Vds= 18V.
-"'raturef
I
37
Drain
Gate
Source
Figure 3.4.2-22: Top view of the lattice temperature distribution on the GaN cap layer of Transistor B
at Vgs=-2V, Vds=1 8V.
Dra in
Temperature
/I
-370
Gate
Source
Figure 3.4.2-23: Top view of the lattice temperature distribution on the GaN cap layer of Transistor B
at Vgs=-3V, Vds=1 8V.
The above lattice temperature distribution images of Transistor A and Transistor B have
important and interesting features:
e
e
For both Transistor A and Transistor B, the lattice temperatures in the drain-to-gate area
and gate-to-source area increase with increasing drain-to-source voltage and decrease
with decreasing gate-to-source voltage. This feature is consistent with the simulations
results we demonstrated in the Figures 2.6.4-1 to 2.6-4-4 in Chapter 2 and will be
analyzed in detail in the section 3.4.3;
For Transistor B, the lattice temperature distributions are not uniform in both the drainto-gate and gate-to-source regions compared to the fairly uniform distributions of
Transistor A. Some areas are heated as hot as 370K, but some ones are almost at the
room temperature. This interesting feature could be explained by the different defect
...
................
densities in the AIGaN layers as well as by the different thermal conductivity of the
substrate and will be discussed in detail in the section 3.5;
Comparing Transistor A and Transistor B under the same bias conditions, we find that
the lattice temperature of Transistor B is much higher (>20K) than Transistor A. This
difference is because the SiC substrate of Transistor A, with much higher thermal
conductivity than the Si substrate of Transistor B, dissipates heat more efficiently hence
cools the surface temperature of the GaN cap layer, as predicted in the simulation
results in Chapter 2.
3.4.3 Experiment vs. Simulation
Since the lattice temperature distributions of Transistor B are not uniform, in this section we
only use the experimental data of Transistor A. By averaging the lattice temperature along the
gate-width direction, we compare them with the simulation results obtained in Chapter 2 as
shown in the figures below:
3201
S315
*315
Vds=1V
E
NW
I-310
I-310-
Microns
'5
4
4 55
Microns
Figure 3.4.3-1: Measured and simulated lattice Figure 3.4.3-2: Measured and simulated lattice
temperature along the GaN cap layer in the gate-to- temperature along the GaN cap layer in the drain-tosource region of Transistor A under the decreasing Vds gate region of Transistor A under the decreasing Vds at
at Vgs=OV.
Vgs=OV.
340
Gate
Source
+--
TransistorA
335
---
@Vds=18V
-
330
-
-
experiment
simulation
325
320
S320!
IV
i~315
-L
S3101
32E e
4.5
Vp:-IV
0
05
1
15
Microns
Micrans
Figure 3.4.3-3: Measured and simulated lattice
temperature along the GaN cap layer in the gate-tosource region of Transistor A under the decreasing Vgs
at Vds=18V.
Figure 3.4.3-4: Measured and simulated lattice
temperature along the GaN cap layer in the drain-togate region of Transistor A under the decreasing Vgs at
Vds=1 8V.
330
-25
experiment
33M 330
-simulation]
-l- -experiment
-& -sirmulation
320
325
S315
320
310#0
295
296 -
290
Transistor A @ Vds=1SV
TransistorA @Vgs=OV
285j
0
2
4
6
8
10
Vds / V
12
14
16
18
26.4
-3
-2
-1
0
1
2
3
Vgs / V
Figure 3.4.3-5: Measured and simulated peak lattice Figure 3.4.3-6: Measured and simulated peak lattice
temperature on the GaN cap layer of Transistor A as a temperature on the GaN cap layer of Transistor A as a
function of Vds at Vgs=OV.
function of Vgs at Vds=1 8V.
From the Figures 3.4.3-1 to 3.4.3-4, we can see that the match between the shape of the
simulation curves of the lattice temperature distribution along the device and with the
experimental data is not perfect, but the peak temperatures near the drain edge of the gate are
still in excellent agreement with the measurements (see in the Figure 3.4.3-5 and 3.4.3-6).
......
.........
..........
. ....
The reason of the difference between experiment and simulation is possibly because of the
simplifications done to model the heat flow in AIGaN/GaN HEMTs. The heat flow is largely
influenced by the various defects and dislocations in the material. This is especially important
for AIGaN/GaN hetero-structures grown on SiC, with 109 cm- 2 defects density, and for those
grown on the Silicon substrate with even higher defect density. The variation of the thermal
conductivity of materials, the interface between AIGaN and GaN layers and the substrate also
play an important role to explain the difference between the experimental and simulated lattice
temperature distributions.
3.5 Discussion
As we mentioned in the previous section, one of the most interesting features of the
experimental results is the non-uniformity of the lattice temperature images of Transistor B and
we observed this feature in all devices fabricated on AIGaN/GaN samples grown on the Silicon
substrate. The device surface is smooth and clean, and all of the photo-resists have been
removed. Therefore, it is quite reasonable to account this non-uniformity to the higher defect
densities in Transistor B. Because defects and dislocations limit the heat flow (cool areas), hot
'islands' are created on the surface of the transistor as we observed in the lattice temperature
image below:
Possible Defects
Drain
Hot islands *_1,
G ate
Temerature/
(
Possible Defects
""7"
Hot islands *_00
Source
Figure 3.4.4-1: Top view of the lattice temperature distribution on the GaN cap layer of Transistor B at Vgs=1V,
Vds=1 8V.
This feature of the thermo-reflectance measurements for the lattice temperature, actually,
provides a very easy and direct tool for the early testing of the reliability of the AIGaN/GaN
HEMTs in the terms of the defects densities in the materials.
3.6 Summary
To summarize, in order to test the accuracy of the self-consistent electro-thermal simulations,
we took the advantage of high-resolution thermo-reflectance microscopy to measure the lattice
temperature distributions on the surface of AIGaN/GaN HEMTs. Good agreement with the
simulation results in the location and value of the peak temperatures under various bias
conditions was obtained, although an improved lattice heating model is needed to reduce the
difference between the measurements and simulations. In addition, we found non-uniformity
of the temperature distributions along the gate-width direction on wafers grown on Silicon
substrate which we associated to the effect of the large defects densities in the wafers. In
Chapter 5, we will revisit this interesting feature of the thermo-reflectance measurement and
we will use it to study degradation in GaN-based HEMTs.
CHAPTER 4
PIEZOELECTRIC-THERMAL CALCULATIONS
4.1 Introduction
Since AIGaN and GaN are both piezoelectric materials, the coupling between the electric field,
the lattice heating and the mechanical properties gives rise to variations in the strain field and
elastic energy densities, which eventually change the electrical characteristics of the
AIGaN/GaN HEMTs. This degradation mechanism, called the inverse piezoelectric effect, has
been intensively studied recently [25] [38] [39]. However, quantitative analysis of this failure
mechanism is still lacking. This chapter aims at providing new understanding of the theory of
the inverse piezoelectric-induced degradation and to provide fully-coupled piezoelectricthermal calculations of the mechanical characteristics of the AIGaN/GaN HEMTs for further
investigation.
4.2 Theory
In this section, we will establish the piezoelectric-thermal model for the calculation of the
mechanical characteristics (strain, stress and elastic energy density) in AIGaN/GaN HEMTs.
4.2.1 Fundamental Equation
To study the mechanical properties of the AIGaN/GaN HEMT, it is natural to treat it as a whole
mechanical system and to start from the fundamental equation of this system.
Using the thermodynamic method, the fundamental equation of the AIGaN/GaN heterostructure system can be written in the form of its internal energy density u as follows:
U= U(Se,,trop
e E,t
, Ezz,
Er
,
,E
D,D,,D7 )
(4.2.1-1)
where Sentropy is the entropy density, Eij (i,j=x,y,z) are the six components of the strain and Dk
(k=x,y,z) are the three components of the electric displacements in the AIGaN/GaN HEMT.
These three variables are the independent extensive parameters or the natural variables of the
system.
The first differential of u therefore has the following formulation:
du =
e ,Dk
ds+
dej + _
01
J
@
i,ja,y,z
=xy
sentropy,Dk
dDk
1
k
(4.2.1-2)
Sentop, -;
The partial derivative terms are called the intensive parameters, and have the following
conventional notations:
(4.2.1-3)
entropy
,D
T
014
d-ij
ki
(4.2.1-4)
0-ij
etrp,,Dk
8
(4.2.1-5)
= E,k
where T is the temperature, aij are the six components of the stress and
components of the electric field in the AIGaN/GaN HEMTs.
Ek
are the three
By substituting equations (4.2.1-3) to (4.2.1-5) into equation (4.2.1-2), we have:
du=Tds+ Ij(ao-Ispe + 1(Ek)dDk
i,j= x,yz
k= x,,z
This is the first derivative of the fundamental equation.
4.2.2 Equations of State
(4.2.1-6)
By expressing the intensive parameters in terms of the independent extensive parameters, we
have the equations of state:
T(T
i- = a
Ek =
E,,
- (s eD,.V, E
,Ee
DDD
(4.2.2-1)
(4.2.2-2)
,D,,Dz)
E,,,E,,ExEyz
,E
1E,
Ek(senUgxE
)
(4.2.2-3)
DDDz)
E,
4.2.3 Alternative Formulation
For thermal, electrical and mechanical systems like AIGaN/GaN HEMTs, the independent
extensive variables are temperature, strain and electric field. Therefore, we need to use them
as our natural variables in the fundamental equation.
This leads us to the fundamental equation in the form of the Helmholtz free energy density f:
f = f (T,ex,c,e z,,E Y,e,.e, E, E,E )(4231
Using Legendre transform of the internal energy density u, we have:
f
= u - Tsentropy -
EkDk
(4.2.3-2)
k= x,v,z
The first derivative is:
df= ( T
dT+
-
df
k,Ek
=-s
0)r
i,j=xY,z deNjT,Ek
entrop dT+
with the conventional notation:
k=x,y,z ek)Tejj
i, j= x'yz
Ek
des+
jo-,de
DkdEk
k=x,y,z
dEk
(4.2.3-3)
(4.2.3-4)
C
= sentropy
(4.2.3-5)
(If
)Eij,Ek
(4.2.3-6)
deNj
T,Ek
(4.2.3-7)
=Dk
Similarly, according to section 4.2.2 we have the equations of state:
'
Sentropy (T,'
Sentropy
' zz' xy' Cxz'
Syz, Ev V, E,)
(4.2.3-8)
ijO
(Tj xx, Eyy, -Ozz, -Oxy' -xz, -yz , EX ,E,, E,)
Dk
(4.2.3-9)
Dk(T,exx,e) vezzex,, exze,,,Ex,,E,, E7)
=
(4.2.3-10)
4.2.4 Material Properties
The first derivatives of the equations of state or equivalently the second derivative of the
fundamental equation gives us the material properties of the system.
Firstly, the first derivatives of the equations of state (equation 4.2.3-8 to 4.2.3-10) are:
dsentrop =
"nrp
dT +
E
(x S """
)T,
I.m=x,y 'z
mT
,Ek
)e1t1,E,
dT +
e n ,E
z-
x
k
dDk= (dI
aem,Ek
or re-written in the matrix forms:
1.m=x,y,Z
"
k=x y,z
im T,Ek
IMxy~
Im
del,+
T,Ek
k
d
deln + I
dDk )
dT+
del,, +
k=x,y,z
:
n = ,y,z
dEk
(4.2.4-1)
T ej
dEk
(4.2.4-2)
dEn
(4.2.4-3)
k TeS
dDk
TE j
d
dsentropy = -Ce,,E
d
T
[a] dT
_[C]
+
,E
[C T,E ]
_
[P a
T
-
E
dE
(4.2.4-4)
d g[e
dE
(4.2.4-5)
-
dT + [eT,E]dZ+(pe-nittivity ] dE
d =
(4.2.4-6)
(a
E!
where
-=
DJ
, E= E2 ,
, 6=
=D2
EV
6
6/
sD3
E6 )
The subscript used here means: xx--1 ,yy--.2,zz--+3,yz--4,zx--5,xy--+6 and x--1 ,y-+2,z-+3.
* Thermal Properties
** Specific Heat
C,, Ek
=
Kd
(4.2.4-7)
EmI.,Ek
4* Thermal Expansion Coefficient
aI
a2~
[a,E
=
ai=Q~&J
(4.2.4-8)
o,,~ ,Ek
* Elastic Properties
+ Elastic Compliance
[STE =
Si l
S12
S13
S14
S15
S16
S21
S22
S23
S24
S25
S26
S3 1
S32
S33
S 34
S35
S3 6
S4 1
S42
S43
544
S4 5
S46
S5 1
S52
553
S54
S55
S56
S61
S62
S63
S64
S65
S66,/
C1I
C12
C13
C14
C15
C16
C2 1
C22
C2 3
C24
C2 5
C26
C3 1
C32
C3 3
C34
C3 5
C36
C41
C42
C4 3
C44
C4 5
C46
C51
C52
C5 3
C54
C5 5
C56
C62
C6 3
C64
C6 5
C66 .1
SY= do
(4.2.4-9)
T ,E,
* Elastic Stiffness
cTE ] =
\C
61
C.. =
d I
(4.2.4-10)
j /T,E,
* Piezoelectric Properties
+ Piezoelectric Strain Constant
d11'd
[dT]=!d
2
d13
d14
d15
d16
d22 d23
d24
d25
d26
d31 d32 d33 d34 d35 d36 )
d =
I
(4.2.4-11)
dE)
+ Piezoelectric Stress Constant
])
0
-
e1 1
612
613
e14
e15
e16
21
e22
e2 3
e2 4
e 25
e 26
e31
e32
e33
e34
e 35
e36 /
Dielectric Properties
=i
(4.2.4-12)
[ Epermittivity
8
0
_
permittivity
permittivity,
1'i2
permittivity
1'i3
ermittivity
permittivity
-22
permittivity
Epermittivity
31
permittivity
32
23
permittivity
£33
J
ermittivitv
eEJ
,
=
(4.2.4-13)
Pyroelectric Properties
ODi
[p]= P2J Pi =a
(4.2.4-14)
\P3J
4.2.5 Constitutive Relations
The constitutive relations play an essential role in the piezoelectric-thermal calculations,
because they relate and couple the mechanical, electrical and thermal properties of the
materials together.
4.2.5.1 General Constitutive Relations of the Wurtzite IHI-V Nitride
For wurtzite Ill-V nitride semiconductor, based on their crystal symmetry, we can simplify the
matrixes of the elastic stiffness, piezoelectric stress constant and thermal expansion coefficient
in the following way:
0
0
0
0
0
[CT,E ] =
(4.2.5.1-1)
C6
6
('0
[eT]=
0
0
se31
0,
(4.2.5.1-2)
(a>
iai
Ia
[ao,E
(4.2.5.1-3)
=
0)
Meanwhile, we still have the basic constitutive relation for the stress of interest as the first
derivative of the equation of state:
&=-[cT,E
d0
[a
A = -[c T,E] [a]
T[C,E
d
T,E
d~ eT,E y - d$
A6-[e
T,Ei
(4.2.5.1-4)
d AE
t
(4.2.5.1-5)
Substituting equations (4.2.5.1-1) to (4.2.5.1-3) into equation (4.2.5.1-5), we get the general
constitutive relations of the wurtzite Ill-V nitride in matrix form:
AU5
0
0
0
0
0
\AU 6
C66 /
Au
Ao 2
Au
AU4
Aei-aaAT
AE,
Ae 2 - aaAT
Ags-acAT
4.2.5.2 Free-Standing and Clamped Model
AC4
Ae5
Ae6
e0
0
AE2
AEO'
(4.2.5.1-6)
.V':V:........
......
__ _
....
..
..
.......................
Since we have already obtained the electric field and lattice temperature distribution from
previous simulation data in Chapter 2, we can now calculated all the components of the strain
and stress, which are 12 unknowns.
In order to solve these 12 unknowns, for our specific case of AIGaN/GaN hetero-structures as
schematically shown in the Figure 4.2.5.2-1 below, we use free-standing and clamped model
to reduce the number of unknowns.
Figure 4.2.5.2-1
Free-standing implies no vertical (z direction) force on the AIGaN layer of interest because of
its free surface. Even if we consider the mechanical influence of the source, drain and gate on
the AIGaN layer, the regions of source-to-gate and gate-to-drain are still free-standing.
Therefore, we have:
AU3 =AU 4 =AU5 =0
(4.2.5.2-1)
Also, since the transistor is totally symmetric along the y direction as shown in the Figure
4.2.5.2-1, we must have:
AE2 = Ae 4 = AE 6 =0
(
(4.2.5.2-2)
Moreover, the clamped model indicates that the boundaries of the transistor along the channel
(x direction) are fixed, which means no displacement on x direction on the boundaries. So, we
get:
uxL = Ux L
(4.2.5.2-3)
0
where u is the displacement and L is the source-to-drain distance as shown in the Figure
4.2.5.2-1.
By Substituting equations (4.2.5.2-1) and (4.2.5.2-2) into equation (4.2.5.1-6), then we have 6
equations for 6 unknowns:
AU2
0
0
0
Au6
A1l - a
0
0
0
0
0
0
Ae3- acAT
0
0
c4
0
0
0
c11
c12
c13
0
c12
cII
c13
c13
c13
c33
0
0
0
0
0
,
0
AT
-aaAT
AE
AE2
0
(4.2.5.2-4)
AE3
AE5
0
C6 6 ,1
which can be solved explicitly as follows:
2
2
Au- =
C3 3
-e)AE3 +(2_-c
C3 3
2
Auo2 = (c12 c3)s
l-c 1 2
+( c13e33
)AE3
C
-
c13
C33
Ac
+
(4.2.5.2-5)
+
2
13
(2--_C
11 I - C12 )aaAT
e33
AE3+(2 ci3aa + a)AT
C3 3
(4.2.5.2-6)
(4.2.5.2-7)
AU =0
AE 3
)aaAT
C3 3
(4.2.5.2-8)
C33
AE5 = e15
C4 4
AE
(4.2.5.2-9)
4.2.5.3 The Initial States
Because of the lattice mismatch between AIGaN and GaN, the AIGaN/GaN hetero-structure
shows an initial strain and stress in its thin AIGaN layer, which is schematically shown in the
figure below:
H
K
A1XGajxN
AlXGal;(N
GaN
GaN
Substrate
Substrate
Figure 4.2.5.3-1: AIGaN layer initially experiences tensile strain on GaN layer because of the lattice mismatch
between them.
Therefore, the initial states of the AIGaN layer in the AIGaN/GaN hetero-structure are as follow:
0
aGaN
20
-
'61
F3
aAlGa_,N
a_
aAl Gal-N
3
-2
0
£4 =8
o0 = o = (c
(4.2.5.3-2)
614
0
(4.2.5.3-3)
G6 =
= C
+c
(4.2.5.3-1)
l
-2
(4.2.5.3-4)
C 33
(7 3 = (T4 =
E ' = E=
s= U 6 = 0
E3=0
T' = 295K
(4.2.5.3-5)
(4.2.5.3-6)
(4.2.5.3-7)
4.2.5.4 Constitutive Relations of AlGaN/GaN HEMTs
Substituting the initial state equations (4.2.5.3-1 to 4.2.5.3-7) into equations (4.2.5.2-5 to
4.2.5.2-9), we finally obtain the constitutive relations for strain and stress field in the
AIGaN/GaN HEMTs as a function of the electric field and the lattice temperature distribution:
2
2
=i (c11
C2
2
(4.2.5.4-1)
c13e33 -el)E 3 +(2 c3 c 11 -C12 )a,(T -295)+Oi
c)
C3 3
C33
C33
e2
3 )(1
eO)+(C 13e3
C 3
e3 )E3 +(2--c
=(c 12 -- )(ei -Ei )+(ci
C3 3
C33
C3 3
U3 = U 4 = (
5
E2 =
E3 = -S-3(e
C3 3
- E41)+--"-E 3 +(2
1
I -Ci 2 )a(T -295)+
2
(4.2.5.4-2)
= U6 = 0
(4.2.5.4-3)
0
2
(4.2.5.4-4)
-SL3a,+a,)(T -295)+
E
(4.2.5.4-5)
C33
C3 3
4=
E5 =
E6 = 0
(4.2.5.4-6)
5E
(4.2.5.4-7)
C44
Now, we only have one unknown variable E1, the strain in the x direction (along the channel). It
should be highlighted that E1 is not uniform in the AIGaN layer of interest, in matter of the fact
that prevous work wrongly uses the initial strain as the final strain and claims a uniform strain
field in the AIGaN layer.
4.2.6 Equilibrium Equations
Based on the fact that the transistor is in the mechanical equilibrium and no body-force in it,
Newton's second law should be obeyed. So, we have the following equilibrium equations:
6a
+
ax
a76++ a0
ay
az
-6+
ax
2 +
ay
at5 +
ax
-0
_
a_
Jz
4+
3
a
ay
(4.2.6-1)
-40_
-
0
az
By using equation (4.2.5.4-3), equation (4.2.6-1) is simplified as follows:
ta2
[',=0
aa2-0
(4.2.6-2)
This equation indicates that the stress field in the AIGaN layer is uniform, contradicting the
conclusion of previous work [38] [40] [41] that claimed that the applied electric field results in
an inhomogeneous stress field in the AIGaN layer. This wrong conclusion is mainly because
previous work neglected the mechanical equilibrium conditions of the device.
4.2.7 The Boundary Conditions Problem
Substituting equation (4.2.5.4-1) and (4.2.5.4-2) into equation (4.2.6-2), we get two partial
differential equations:
(c
(c
2
a
C2
a 2u
2u +
)c
13
c33
where D
ax
=
Jx
C33
axay
+
c33
9
C13'3 3
C33
Cle32
-e
)E
3
ax
a
+(2 c-C
E3)3 +
ay
C33
(2cy
11
c -C12
C33
e , using the strain-displacement relations.
Because of the symmetry along y direction,
-C
3T
12 )a
a
ay
=0
_
(4.2.7-1)
-0
(4.2.7-2)
32 E
S_
xy
43T
3
(4.2.7-3)
=0
y
ay
So, equation (4.2.7-2) always holds.
The problem of solving the strain and stress field in the AIGaN/GaN HEMTs, therefore,
becomes a well-defined boundary conditions problem:
(c_
u3c
{(cl C3(3 ax
c1 3e3 3
C33
_
3x
3
+(2
3
=0
C33
Since we have already obtained the distribution of
2 )aa
E3
(4.2.7-4)
and T from the simulations in Chapter 2,
equation (4.2.7-4) could be solved in Matlab using the finite difference method. As long as we
get the distribution of the displacement ux, hence the strain eI in the transistor, the other 11
unknowns of stress and strain could be easily calculated by using the equations (4.2.5.4-1) to
(4.2.5.4-7).
4.2.8 Elastic Energy Density
The elastic energy density is another important and interesting variable in AIGaN/GaN HEMTs,
because defects creation, crack formation and other mechanical failures are all related to the
elastic energy density in materials. Due to its essential role, there are numerous studies and
calculations of the elastic energy density distributions in AIGaN/GaN HEMTs. However, in this
chapter, we derive a new set formulas of the elastic energy density based on the equations we
have just established in the above section.
The elastic energy density or the mechanical work stored per unit volume in the material has
the following intuitive relation with the strain and stress:
dW =a de,+
2
de 2 +u 3 de +q 4 de4 +o 5 de5 +a 6 de
(4.2.8-1)
Substituting equations (4.2.5.4-3) and (4.2.5.4-4) into the above equation, the elastic energy
density of AIGaN/GaN HEMTs has a very simple formulation:
dW = or dei
(4.2.8-2)
Using the equation (4.2.5.2-5), we obtain a formulation of the elastic energy density as a
function of the stress, electric field and temperature:
CIAe3 _ e31
C
dW
12
=
"1
o
C1
2
2C
C13
33
C 33
C2-e1 idE-
C11
p123
C, - C12
C2
23
(4.2.8-3)
3
C3
1
aidT
C33
C33
Compared to the change of electric field and temperature from the initial state to the final state,
the change of stress is actually very small (as we will show in the latter section of this chapter),
so we can treat the stress in the last two terms of the equation (4.2.8-3) as constant with the
value of the average stress when integrating the other variables as following:
C1333_31
W
,
=
2 C11
2
2 C13
(a,+or)E3
C
C123
2 C11-C13
C33
C33
-C
C33
2 (CII -
C1
12
+$aadi+01)(T-295)+W4
(4.2.8-4)
3
C33
where
W
=
(4.2.8-5)
)2
C1 +C12 -2 C1 3
33
is the initial elastic energy density in AIGaN/GaN HEMTs.
4.3 Calculation Results
By coding the previous equations in Matlab and extracting the electric field and the lattice
temperature data from previous simulations, we solve the PDE equations (4.2.7-4) and obtain
the strain, stress and the elastic energy density in the AIGaN layer of AIGaN/GaN HEMTs.
4.3.1 Strain
Inthis section, we analyze the different components of the strain data.
4.3.1.1 X Component of Strain (i.e. strain along the channel)
-0-Change of the Peak XComponent of Strain
2
66
-- Vgs=VVds=3V
-- V=VVdS=0V
6.5
CD
/
Piezoelectric-Thermal Effect
E/
6.46 3 ;6-
sou rce
Gate ---- *
Drain -4
22
8.2
6.1
0.5
1
1.5
2
2.5
Microns
3
3.5
4
4.5
Transistor A
@Vgs=OV
//
TransistorA
0
-
5
0
2
4
8
8
10
Vds IV
12
14
16
18
Figure 4.3.1.1-1: Value of the x component of strain Figure 4.3.1.1-2: Percentage change of the peak value
along the AIGaN layer of Transistor A (SiC substrate) of the x component of strain at the drain edge of the
under increasing drain-to-source bias at Vgs=OV. The gate as a function of the drain-to-source bias at
black line indicates the initial state.
Vgs=OV (Vds=OV state to high-power state).
7
__
_
_
_
__
_
_
_
_
1U
Vs2Vds=18V
TransistorA
Vse-tVd
68
7
7 -
Inverse Pieoelectric Effect
8
-- V
-2V
Vde9V
-- Vgs--3VV-sI1V
-
7
V-'OVds-18V
-- V /Vd.=ISV
6
66
5-
Lattice Heating Expansion
O3
0E
1
15
2
TransistorA
@Vds=18V
1
-0-Change or the Peak XComponent of Strain
-20 -18
2
Miems
-16
-14
-12
-10
8
-6
4
-2
0
2
Vgs /V
Figure 4.3.1.1-3: Value of the x component of strain Figure 4.3.1.1-4: Percentage change of the peak value
along the AIGaN layer of Transistor A (SiC substrate) of the x component of strain at the drain edge of the
under decreasing gate-to-source bias at Vds=1 8V. The gate as a function of the gate-to-source bias at
black line indicates the initial state.
Vds=1 8V (high-power state to off state).
From the above figures, we find that in our fully-coupled piezoelectric-thermal model, the strain
along the channel direction in the AIGaN layer peaks at the drain edge of the gate for all of the
bias conditions, especially for the highly-off state (large reverse gate bias). The peak value can
increase up to -10% beyond the initial state (see in Figure 4.3.1.1-4).
The physics behind this effect can be explained as follows: According to the constitutive
relation (4.2.5.1-4), both the increasing vertical electric field and the increasing lattice
temperature in the AIGaN layer tend to tensile the lattice in the x direction (along the channel).
In addition, at the drain edge of the gate, as shown in the simulations in Chapter 2, both of
them reach the maximum values (Figure 2.6.3-1, 2.6.3-5, 2.6.4-1, 2.6.4-3). Therefore, the
strain in the AIGaN layer along the x direction must peak at the drain edge of the gate, in an
agreement with the calculations.
Moreover, under the conditions of increasing Vds at Vgs=OV, the peak values of the vertical
electric field and the lattice temperature both increase with the drain-to-source voltage, so we
should also observe the same trend of the peak value of the x component strain in our
. ...
....
.........
piezoelectric-thermal calculations as shown in Figure 4.3.1.1-2. Similarly, under the conditions
of decreasing Vgs at Vds=18V, we have also known from the previous simulations that the
peak value of the vertical electric field increases and the maximum lattice temperature
decreases to room temperature, therefore, the x component strain must increase as the Vgs
decreases in the off state (where no current flow in the AIGaN/GaN HEMTs) and decrease as
the Vgs decreases from the high power state to the off state because of the smaller and
smaller lattice heating expansion. This trend also matches our piezoelectric-thermal
calculations in Figure 4.3.1.1-4.
4.3.1.2 Z Component of Strain (Vertical Strain)
X10-
Piezoelectric-Thermal Effect
--- Vgs=0V Vds=18V
a
S
S4.5-
Vgs=0VVds=5V
--
--
Vs=OVVds=12V
Vgs=0V Vds=9V
-V=OVVds=6V
-- Vgs=0V Vds=3V
0,5
Transistor A
Vds=0V
-Vgs=0V
0
Transistor A
@Vgs=OV
1
1.5
2
2.5
Microns
3
3.5
$-Change ofthePeak ZComponent of Strain.1
A
A.5
5
U
2
4
6
8
10
Vds / V
12
14
16
18
Figure 4.3.1.2-1: Value of the z component of strain Figure 4.3.1.2-2: Percentage change of the downside
along the AIGaN layer of Transistor A (SiC substrate) peak value of the z component of strain at the drain
under increasing drain-to-source bias at Vgs=OV. The edge of the gate as a function of the drain-to-source
black line indicates the initial state.
bias at Vgs=OV (Vds=OV state to high-power state).
............
_
_
_
_
_
_
_
_
_
_
_
_
+Sou rce
.
35
_
-rain
-+
25
Inverse Piezoelectric Effect
-4-
20
I
01
S5
s-
v
v
18
Vgs.2VVds.18V
Veova10 :v
rTransistor
e
v
Transistor A
-- vgsIO.=18v-v
Vgs*.20VVftWSV
5
--gs
;V
-S
1.6
.attic Heating Expansion
La5c
-*
Vq=QV~1;=0-L2L
MiIS
3
Micron$V
36
4
AS
5
6
-
A
@Vds=18V
Change of the Peak 2 Component of Strain
18 -16 -14 -12 -1 18
q
-5
6 -4
2
0
2
a/
Figure 4.3.1.2-3: Value of the z component of strain Figure 4.3.1.2-4: Percentage change of the downside
across the AIGaN layer of Transistor A (SiC substrate) peak value of the z component of strain at the drain
under decreasing gate-to-source bias at Vds=1 8V. The edge of the gate as a function of the gate-to-source
black line indicates the initial state.
bias at Vds=1 8V (high-power state to off state).
The calculation results of the vertical strain are in perfect consistency with the physics of the
piezoelectric relations. Actually it is fairly intuitive that tensiling the lattice in the lateral direction
compresses it vertically and the larger the tensiling the larger the compressing. On the other
hand, for the lattice heating effect, both directions should be expanded with increasing lattice
temperature.
More importantly, as we can see from Figure 4.3.1.1-4 and 4.3.1.2-4, under larger and larger
reverse gate bias, the lattices at the drain edge of the gate would experience more and more
expansion and thinning. In the end, this process will create deep cracks at the drain edge of
the gate which have already been observed in some previous work [39] [42]. This kind of
failure mechanisms in AIGaN/GaN HEMTs would be measured and discussed in more detail in
Chapter 5.
4.3.2 Stress
The uniform planar stresses in the AIGaN layer can be calculated in the piezoelectric-thermal
model under the various bias conditions as shown in the figures below.
.....
. .......
......
3.06
-
-0 - x component of stressy component of stress
3.05
304
3.03
3.02 *
*
3.01
TransistorA
%,
'b~.~* ~
N
3
2.99
298
2.971
2.06
0
2
6
4
8
10
Vds i V
12
14
16
18
Figure 4.3.2-1: Value of the x and y component of stress in the AIGaN layer of Transistor A (SiC substrate) as a
function of the drain-to-source voltage at Vgs=OV.
3.06
-
3 05.
-x
component of stress
- -y
component of stress
3.04 -
TransistorA
3.03.
3.02 -
M
3.
2.99
297
-20
-18
-16
.14
-12
-10
-8
Vgs / V
-6
-4
-2
0
2
Figure 4.3.2-2: Value of the x and y component of stress in the AIGaN layer of Transistor A (SiC substrate) as a
function of the gate-to-source voltage at Vds=1 8V.
We can see that the changes of the stress in the AIGaN layer are actually very small compared
to the changes of the strain, the electric field and the lattice temperature, so we can treat them
as constant in the equation 4.2.8-3 in order to simplify the calculations of the elastic energy
density.
61
......................
...
4.3.3 Elastic Energy Density
Finally, the elastic energy densities under various bias conditions are calculated using the
equation 4.2.8-4. The results are mentioned in the figures below:
A.
8i
22x 10
2 15
-Vgs=VVds=12V
V9s=0VVds=9V
-Vs=OVVds=6V
Vgs=0V Vds=3V
Vgs=VVDs=OV
21
25
C
Vgs=0VVds=18V
Vs=0V Vds=15V
-
I
-'"
4
Piezoelectric-Thermal Effect
3
W 195
Ii
'A
-4 - Change of the Peak Elastic Energy Density
19
TransistorA
@Vgs=OV
TransistorA
0
0.5
1
1.5
2
2.5
Microns
3
3.5
4
4.5
5
Figure 4.3.3-1: Value of the elastic energy density
along the AIGaN layer of Transistor A (SiC substrate)
under increasing drain-to-source bias at Vgs=OV. The
black line indicates the initial state.
6
2
4
6
8
10
Vds /V
12
14
16
18
Figure 4.3.1-2: Percentage change of the peak value of
the elastic energy density at the drain edge of the gate
as a function of the drain-to-source bias at Vgs=OV
(Vds=OV state to high-power state).
10~
22
-vgs.7V vas tav
2-S
21
-- vgs1V Vers~v
--
vg-0oVvS=t8V
V--1VVds=18V
-vgsm-2VVds=1V
-- Vs-VVds13V
Vol-O 'v1don1ey
-Vgs"O
-2.0
2
TransistorA
Inverse Piezoelectric Eff
VdVe16v
Lattice Heating Expansion
S
-Source
Drain--
TransistorA
@Vds=18V
-*-Change of the Peak Elastic Energy Density
Micrns
Figure 4.3.1-3: Value of the elastic energy density
along the AIGaN layer of Transistor A (SiC substrate)
under decreasing gate-to-source bias at Vds=18V. The
black line indicates the initial state.
20
-18
-16
-14 -12
-10
-8
Vgs/V
-6
-4
.2
0
2
Figure 4.3.1-4: Percentage change of the peak value of
the elastic energy density at the drain edge of the gate
as a function of the gate-to-source bias at Vds=18V
(high-power state to off state).
4.4 Summary
In conclusion, we have rigorously derived the piezoelectric-thermal relations in the form of a
partial differential equation under the condition of a clamped and free-standing model for
AIGaN/GaN HEMTs. By using the data extracted from the previous self-consistent electrothermal simulations, we solved the PDE equation in Matlab and obtained the desired
mechanical characteristics-strain, stress and elastic energy density in the GaN-based
transistors. In the calculation results, we found that the vertical electrical field and the lattice
heating both tensile the lateral strain, but on the other hand, the vertical electrical field
compresses, the lattice heating tensiles the vertical strain in the AIGaN layer at the drain edge
of the gate, especially under pinch-off condition. This feature explains the mechanisms of
crack formation and defects creation in the AIGaN layer observed at the drain of the gate
under the off state stress testing of AIGaN/GaN HEMTs. In addition, the calculation of the
elastic energy density in devices provides important quantitative results for the prediction of the
critical voltage of the reverse-gate-bias degradation and could be further applied to the
understing of the fracture mechanisms of AIGaN/GaN HEMTs.
CHAPTER 5
5.1
REVERSE-GATE-BIAS RELIABILITY TESTING
Introduction
As we mentioned in Chapter 1, several authors have observed that significant degradation of
AIGaN/GaN HEMTs takes place when the devices are biased in the pinch-off state during the
reverse-gate-bias testing at Vds=OV state [24] [25]. In this case, the main failure phenomena
observed is a catastrophic increase in the gate leakage for gate voltage beyond a critical
voltage [43]. Inthis chapter, we report our work on the use of thermo-reflectance measumrents
to study the reverse-gate-bias reliability of GaN-based HEMTs.
5.2 Structure of Tested Transistors
The transistors we tested here were fabricated using our reliability testing mask and
passivated by A12 0 3 to reach a more reliable performance. The device structure is
schematically shown in Figure 5.2-1:
Zm
Figure 5.2-1 Schematic structure of Transistor C
..
..
......
. ...
.........
5.3 Calibration of Thermo-Reflectance Coefficient
Since the surface material of Transistor C is A1
2 03 , the calibration of the thermo-reflectance
coefficient of the new material is needed before we can convert the thermo-reflectivity maps
into the lattice temperature profiles.
0.00070 -
Al203@ T = 300K
0.00055 -
0.00060-
0.00055-
1=
(3.94±0.58)x104
0.00050
I
0.2
0.3
0.4
0.5
0.6
0.7
0.8
AT
Figure 5.3-1: Variation of the thermo-reflectivity as a function of the variation of the lattice
temperature measured on A1203 sample of 300K. The slope of the fitting line is the thermoreflectance coefficient.
As in the case of the GaN material, the calibration is fairly linear (error <2% in temperature)
and we can approve that the thermo-reflectance coefficient P of A1
203 is also approximately
constant over the temperature range of interest (300K to 400K). The analyzed result at 300K is
shown in Figure 5.3-1. The thermo-reflectance coefficient is 3.94x10-4 K- for Al20 3 material
under the 467nm (blue) LED light.
5.4 DC Measurements of Gate Current Degradation
Five AIGaN/GaN HEMTs with the same structure as Transistor C were submitted to a reversebias step stress test, keeping the source and drain grounded so that Vs=0V, Vd=0V and
applying a negative voltage to the gate from -1OV to -80V in -1OV steps for 1 minute per step.
At the end of each step, device electrical and thermal characteristics were evaluated by DC
measurements and thermo-reflectance measurements respectively. Prior to the test, we
verified that the five devices, belonging to the same wafer, presented a consistent and
reproducible behavior.
In this section, the experimental results of the drain and gate current after each step of the
stress are demonstrated. As we can see from the figures below, there is a minor degradation
for the drain current in the stressed devices but a very steep degradation of the gate current
around a critical voltage at Vgs=-40V in good agreement with other authors' observations [25]
[43] [44] [45].
700
0
fresh
stressed@Vgs=-80V
00
TransistorCC~:
~~
V s=-1V
100
1-Ves=-3V
100
0
1
2---- 3
4
5
68---- 7
8--9--10
Vds / V
Figure 5.4-1: IV curves of the drain current as a function of the drain voltage under various gate bias as for a fresh
and a reverse-gate-bias-stressed Transistor C.
10-3
--
Vgs=2VVds=IV
--
-Vgs=2V Vds=5V
-*
- Vgs=-3V Vds=10V
- 0--Vgs-3VVds=0V
~-1-
10'4
A
10'
T
Transistor C
10
10
20
30
40
50
Vsg/V
60
70
80
Figure 5.4-2: Gate current after reverse-gate-bias stress for four different bias conditions in Transistor C. The
critical voltage of gate current degradation isfound at Vgs=-40V.
5.5 Thermo-Reflectance Measurements of Degradation
This section reports the experimental results for the lattice temperature distribution after each
stress step for a typical tested device.
Temperature /
Temperatue K
3N'
,Orain
Stressed @ Vgs=-10V Vds=OV
325
315
Gate
310
Source
5 kn)
295
Figure 5.5-1: Top view of the lattice temperature image
of Transistor C (fresh) at Vgs=OV, Vds=1 8V.
Figure 5.5-2: Top view of the lattice temperature image
of Transistor C (stressed 1min @Vgs=-1 OV Vds=OV) at
Vgs=OV, Vds=18V.
......
Tmperature /K
330
Drain
Stressed
Tmperature /K
-330
Vgs=-20V Vds--OV
325
320
315
Gate
310
305
316
G10
305
Source
300
5 ini
295=
295
Figure 5.5-3: Top view of the lattice temperature image Figure 5.5-4: Top view of the lattice temperature image
of Transistor C (stressed 1min @Vgs=-20V Vds=OV) at of Transistor C (stressed 1min @Vgs=-30V Vds=OV) at
Vgs=OV, Vds=1 8V.
Vgs=OV, Vds=1 8V.
Temperature / K
Temperature/ K
330
330
Drain
Stress&d & Vgs=-40V Vds=OV
325
320
315
Gate
310
305
Source
5 pill
-------A
Iac
296
Figure 5.5-5: Top view of the lattice temperature image Figure 5.5-6: Top view of the lattice temperature image
of Transistor C (stressed 1min @Vgs=-40V Vds=OV) at of Transistor C (stressed 1min @Vgs=-50V Vds=OV) at
Vgs=OV, Vds=18V.
Vgs=OV, Vds=1 8V.
Temperature / K
330
Dra in
Gate
Temperature / K
330
Stressed @ Vgs---60V Vds=OV
325
325
320
320
315
315
310
310
305
Source
300
291=
295
Figure 5.5-7: Top view of the lattice temperature image Figure 5.5-8: Top view of the lattice temperature image
of Transistor C (stressed 1min @Vgs=-60V Vds=OV) at of Transistor C (stressed 1min @Vgs=-70V Vds=0V) at
Vgs=OV, Vds=18V.
Vgs=OV, Vds=18V.
emperature / K
Temperature / K
330
1330
Drain,
Stresse
Vgs=42V
V
325
320
315
Gate
310
305
Source
Pin
295
Figure 5.5-9: Top view of the lattice temperature image Figure 5.5-10: Top view of the lattice temperature
of Transistor C (stressed 1min @Vgs=-80V Vds=OV) at image of Transistor C (stressed 1min @ Vgs=-82V
Vds=OV) at Vgs=OV, Vds=1 8V.
Vgs=OV, Vds=1 8V.
As shown in the figures above, we find that before the stress step at Vgs=-80V, the lattice
temperature maps for the device are unchanged even after the critical voltage Vgs=-40V for
the gate current degradation, however, at and after the stress step at Vgs=-80V, some round
'defects' (the color of those defects has no relation with the color-map of the temperature
..........
n:n
-
..........
because the surface curvatures of them change the thermo-reflectance coefficient) appear at
the gate-to-source region. This interesting phenomenon is reported for the first time in this
thesis, and its origin will be discussed in details in the next section.
5.6 Discussion
In order to explain the change in the thermal map, SEM and AFM images of the stressed
device were taken in order to investigate the shape and the scale of those 'defects'. Figure 5.52 shows that those 'defects' are actually 'bumps' on the device surface with -50 nm height and
-2 pm width.
Figure 5.6-1 Top view SEM image of Transistor C after
Figure 5.6-2 3D AFM image of Transistor C after
stressed at Vgs=-80V, Vds=OV.
stressed at Vgs=-80V, Vds=OV
Secondly we took a close look at the thermo-reflectance images around Vgs=-80V. As
indicated by the arrows in Figure 5.5-3 below, we find that all the 'defects' are actually created
from blue spots (cold area) one step before the stress testing. We believe that the defect
density under the blue (cold) regions in the thermo-reflectance images is much higher than in
the red (hot) areas because the heat flow is blocked by the defects. The spot '1' in Figure 5.5-3
Aa-
Ov4ONJIMI-ft-
zkgmqwm
-
-
-
-
-
was still yellow (medium hot) after stressed at Vgs=-70V which means there was still heat
flowing under this area, but suddenly at the critical voltage Vgs=-80V, it became a blue (as
cold as room temperature) spot as indicated as '2' in Figure 5.5-4 which means defects were
created under this region and heat flow was blocked. And then, when further stressed at Vgs=82V, the same spot turned to the obvious 'bump' on the surface as indicated as '3' in Figure
5.5-6 which means the defects were growing fast and even dramatically changing the shape of
the surface.
These similar processes are observed from spot '4' and '6', which evolve into spots '5' and '7'
respectively as indicated by the arrows in the figures below.
Tempenature / K
330
Tempefature / K
Drain
Stressed @ Vgs=-BOV Vds=OV
325
320
315
Gate
310
305
'Ce
Figure 5.6-3: Top view of the lattice temperature image
Figure 5.6-4: Top view of the lattice temperature image
of Transistor C (stressed 1min @Vgs=-70V Vds=OV) at of Transistor C (stressed 1min @Vgs=-80V Vds=OV) at
Vgs=OV, Vds=1 8V.
Vgs=OV, Vds=1 8V.
Temperature I K
*Stressd@vs-o
d~v
1empMare /
D'rai n.
K
Stressed@ Vgs=-92V Vds=OV
,325
45M,
74
A1
315
GaL'C
310
Source
300
===295
Figure 5.5-4: Top view of the lattice temperature image Figure 5.5-5: Top view of the lattice temperature image
of Transistor C (stressed 1min @Vgs=-80V Vds=OV) at of Transistor C (stressed 1min @Vgs=-82V Vds=OV) at
Vgs=OV,Vds=18V.
Vgs=OV, Vds=18V.
5.7 Summary
Insummary, we have conducted reverse-gate-bias reliability testing on passivated AIGaN/GaN
HEMTs, in order to study the effect of the gate current degradation in the thermo-reflectance
measurements. Interestingly, surface 'bumps' correlated with the possible defects spots in the
lattice temperature maps were found at the critical voltage Vgs=-80V, which is much higher
than the critical voltage of the gate current degradation at Vgs=-40V. This result reinforces the
conclusion of Chapter 3 that blue spots (cold areas) relate to possible defects under the
surface. Thermo-reflectance measurement is a simple and convenient tool to show defects
distributions and early breakdown for AIGaN/GaN HEMTs as well.
CHAPTER
6.1
6
CONCLUSIONS AND FUTURE WORK
Conclusions
The basic framework developed in this thesis to study the effect of piezoelectricity in the
reliability of GaN-based HEMTs could be summarized in the following flowchart:
Reverse-Gate-Bias
Reliability Testing
Electrical Field
Drift-Diffusion Model
0N
DC Measurements
00;11
>
Critical
ITMatlab
Piezoelectric-
Self-Consistent
EectroThermama
-The rma Iha
Electro
Simulations
Gate Current
Degradation
Voltage
Programming
Strain
Elastic Energy Densities
Calculations
Critical
Voltage
Thermal-Reflectanc
Measuremen
Lattice Heating Model
Lattice Temperature
|
>
Defects Growing &
Surface Bumps Creation
Reverse-Gate-Bias
Reliability Testing
Figure 6.1-1: The thesis flowchart, describing the key models and methods that combine with simulations and
measurements for the purpose of degradation testing and reliability prediction of AIGaN/GaN HEMTs.
By using the commercial software Silvaco Atlas, we successfully modeled and simulated the
electrical and thermal characteristics of the standard AIGaN/GaN HEMTs with good agreement
with experimental results. In thermo-reflectance measurements, we found the non-uniformity
feature of the temperature distributions along the gate width direction on wafers grown on the
Silicon substrate and explained them for the effect of the large defect densities in those
devices. In addition, by rigorously deriving the piezoelectric-thermal relations of AIGaN/GaN
HEMTs, we found that the strain and elastic energy density peak both peak at the drain edge
of the gate under various bias conditions, especially under highly-pinched-off state when
nearly 20% changes can be reached. Moreover, surface 'bumps' possibly associated with
73
defects and early breakdown were found in the lattice distribution maps at the critical voltage
higher than that of the gate current degradation, which makes thermo-reflectance
measurements a potential candidate for a simple and convenient tool to show defects
distributions, study degradation mechanisms and predict reliability performance of AIGaN/GaN
HEMTs.
6.2 Future Work
Future work will be focused on the quantitative analysis needed to find the correlation between
the gate current degradation and thermo-reflectance images through the theory of defects
formation and critical elastic energy densities in the reverse-gate-bias testing.
A more systematic reliability study will be carried out on different sets of transistors. DC, RF,
thermo-reflectance and electroluminescence measurements will be conducted after each step
stress test. Statistical methods will be used to analyze the correlating patterns among them.
What is more, we will take the FIB (Focused Ion Beam) cross-sectional images of surface
'bumps' and cold spots on the lattice temperature profiles in order to provide more direct proof
for the expected defects in the materials of AIGaN/GaN HEMTs.
The ultimate goal of this work would be to be able to predict the critical voltage of the gate
current degradation of different fresh transistors by using the information extracted from the
thermo-reflectance measurements for those devices. This would provide us a fast and low-cost
way to obtain the reliability characteristics of AIGaN/GaN HEMTs.
REFERENCE
[1]
M.A. Khan, A. Bhattarai, J.N. Kuznia, and D.T. Olson, "High electron mobility transistor based
on a GaN-AlxGal-xN heterojunction," Appl. Phys. Lett., vol. 63, 1993, pp. 1214-15.
[2]
S. Nakajima, Y. Tateno, N. Ui, E. Mitani, K. Ebihara, K. Inoure, A. Kawano, "State of the art
performance for high power & high efficiency GaN HEMTs: A Japanese perspective," Proc.
WOCSDICE, 2007, pp. 323-327.
[3]
"www.eudyna.com."
[4]
"www.cree.com."
[5]
"www.nitronex.com."
[6]
"www.rfmd.com."
[7]
R. Coffie, D. Buttari, S. Heikman, and U.K. Mishra, "2.1 A/mm current density AlGaN/GaN
HEMT," Electron. Lett., vol. 39, 2003, pp. 625-626.
[8]
Y. Uemoto, D. Shibata, M. Yanagihara, H. Ishida, H. Matsuo, S. Nagai, N. Batta, M. Li, T. Ueda,
T. Tanaka, and D. Ueda, "8300V Blocking Voltage AlGaN/GaN Power HFET with Thick PolyAlN Passivation," 2007 IEEE InternationalElectron Devices Meeting, 2007, pp. 861-864.
[9]
W. Saito, Y. Takada, M. Kuraguchi, K. Tsuda, I. Omura, T. Ogura, and H. Ohashi, "High
breakdown voltage AlGaN-GaN power-HEMT design and high current density switching
behavior," IEEE Transactionson Electron Devices, vol. 50, 2003, pp. 2528-2531.
[10]
G. Steinhoff, B. Baur, G. Wrobel, S. Ingebrandt, A. Offenhadusser, A. Dadgar, A. Krost, M.
Stutzmann, and M. Eickhoff, "Recording of cell action potentials with AlGaN/GaN field-effect
transistors," Applied Physics Letters, vol. 86, 2005, p. 033901.
[11]
M. Stutzmann, G. Steinhoff, M. Eickhoff, 0. Ambacher, C. Nebel, J. Schalwig, R. Neuberger,
and G. Muller, "GaN-based heterostructures for sensor applications," Diamond and Related
Materials,vol. 11, 2002, pp. 886-891.
[12]
M. Higashiwaki, T. Matsui, and T. Mimura, "AlGaN/GaN MIS-HFETs with f/sub T/ of 163
GHz using cat-CVD SiN gate-insulating and passivation Layers," IEEE Electron Device Letters,
vol. 27, 2006, pp. 16-18.
[13]
T. Palacios, A. Chakraborty, S. Heikman, S. Keller, S. DenBaars, and U. Mishra, "AlGaN/GaN
high electron mobility transistors with InGaN back-barriers," IEEE Electron Device Letters, vol.
27, 2006, pp. 13-15.
[14]
A. Wakejima, K. Matsunaga, Y. Okamoto, Y. Ando, T. Nakayama, K. Kasahara, and H.
Miyamoto, "280 W output power single-ended amplifier using single-die GaN-FET for WCDMA cellular base stations," ElectronicsLetters, vol. 41, 2005, pp. 10-11.
[15]
Y. Wu, A. Saxler, M. Moore, R. Smith, S. Sheppard, P. Chavarkar, T. Wisleder, U. Mishra, and
P. Parikh, "30-W/mm GaN HEMTs by Field Plate Optimization," IEEE Electron Device Letters,
vol. 25, 2004, pp. 117-119.
[16]
M.J. Rosker, "The Present State of the Art of Wide-Bandgap Semiconductors and Their Future,"
Proc.IEEE Radio Freq. Integr. CircuitSymp., 2007, pp. 159-162.
[17]
G. Meneghesso, R. Pierobon, F. Rampazzo, G. Tamiazzo, E. Zanoni, J. Bernat, P. Kordos, A. F.
Basile, A. Chini, "Hot-electron-stress degradation in unpassivated GaN/AlGaN/GaN HEMTs on
SiC," Proc.IEEE Int. Rel. Phys. Symp., 2005, pp. 415-422.
[18]
G. Meneghesso, F. Rampazzo, P. Kordos, G. Verzellesi, and E. Zanoni, "Current Collapse and
High-Electric-Field Reliability of Unpassivated GaN/AlGaN/GaN HEMTs," IEEE Transactions
on Electron Devices, vol. 53, 2006, pp. 2932-2941.
[19]
A. Sozza, C. Dua, E. Morvan, M. diForte-Poisson, S. Delage, F. Rampazzo, A. Tazzoli, F.
Danesin, G. Meneghesso, E. Zanoni, A. Curutchet, N. Malbert, N. Labat, B. Grimbert, and J. De
Jaeger, "Evidence of traps creation in GaN/AlGaN/GaN HEMTs after a 3000 hour on-state and
off-state hot-electron stress," IEEE InternationalElectron Devices Meeting, 2005. IEDM
Technical Digest., vol. 00, 2005, pp. 590-593.
[20]
R. Vetury, N. Zhang, S. Keller, and U. Mishra, "The impact of surface states on the DC and RF
characteristics of AlGaN/GaN HFETs," IEEE Transactions on Electron Devices, vol. 48, 2001,
pp. 560-566.
[21]
A. Watanabe, K. Fujimoto, M. Oda, T. Nakatsuka, "Rapid degradation of WSi sel-aligned Gate
GaAs MESFET by hot carrier effect," Proc. IEEE Int. Rel. Phys. Symp., 1992, pp. 127-130.
[22]
C. Tedesco, C.Canali, F.Magistrali, A.Paccagnella, "Hot-electron induced degradation in
AlGaAs/GaAs HEMTs," Microelectron. Eng., vol. 19, 1992, pp. 405-408.
[23]
G. Meneghesso, G. Verzellesi, F. Danesin, F. Rampazzo, F. Zanon, A. Tazzoli, M. Meneghini,
and E. Zanoni, "Reliability of GaN High-Electron-Mobility Transistors: State of the Art and
Perspectives," IEEE Transactionson Device and MaterialsReliability, vol. 8, 2008, pp. 332-343.
[24]
J. Joh and J.A. del Alamo, "Mechanisms for Electrical Degradation of GaN High-Electron
Mobility Transistors," 2006 InternationalElectron Devices Meeting, 2006, pp. 1-4.
[25]
J. Joh, L. Xia, and J.A. del Alamo, "Gate Current Degradation Mechanisms of GaN High
Electron Mobility Transistors," 2007 IEEE InternationalElectron Devices Meeting, 2007, pp.
385-388.
[26]
[27]
[28]
S.M.SZE, KWOK K.NG Physics of Semiconductor Devices, 2007.
ATLAS User's Manual.
S. Tiwari, Compound SemiconductorDevice Physics,1992.
[29]
M. Farahmand, C. Garetto, E. Bellotti, K. Brennan, M. Goano, E. Ghillino, G. Ghione, J.
Albrecht, and P. Ruden, "Monte Carlo simulation of electron transport in the III-nitride wurtzite
phase materials system: binaries and ternaries," IEEE Transactions on Electron Devices, vol. 48,
2001, pp. 535-542.
[30]
T. Palacios, S. Rajan, A. Chakraborty, S. Heikman, S. Keller, S.P. Denbaars, and U.K. Mishra,
"Influence of the Dynamic Access Resistance in the g m and f T Linearity of AlGaN / GaN
HEMTs," October, vol. 52, 2005, pp. 2117-2123.
[31]
Y. Wu, M. Singh, and J. Singh, "Sources of Transconductance Collapse in III-V NitridesConsequences of Velocity-Field Relations and Source/Gate Design," IEEE Transactions on
Electron Devices, vol. 52, 2005, pp. 1048-1054.
[32]
S. Vitanov, V. Palankovski, S. Maroldt, and R. Quay, "High-temperature modeling of
AlGaN/GaN HEMTs," Solid-State Electronics, vol. 54, 2010, pp. 1105-1112.
[33]
S. Grauby, B.C. Forget, S. Hole, and D. Fournier, "High resolution photothermal imaging of
high frequency phenomena using a visible charge coupled device camera associated with a
multichannel lock-in scheme," Review of Scientific Instruments, vol. 70, 1999, p. 3603.
[34]
A. Sarua, J. Pomeroy, M. Kuball, A. Falk, G. Albright, M.J. Uren, and T. Martin, "Raman-IR
micro-thermography tool for reliability and failure analysis of electronic devices," 2008 15th
International Symposium on the Physical and Failure Analysis of Integrated Circuits, 2008, pp.
1-5.
[35]
D. LderBen, J.A. Hudgings, P.M. Mayer, R.J. Ram, and S. Hadley, "Nanoscale
Thermoreflectance With lOmK Temperature Resolution Using Stochastic Resonance,"
Symposium A QuarterlyJournalIn Modern Foreign Literatures.
[36]
S. Dilhaire, S. Grauby, and W. Claeys, "Calibration procedure for temperature measurements by
thermoreflectance under high magnification conditions," Applied Physics Letters, vol. 84, 2004, p.
822.
[37]
G. Tessier, S. Hold, and D. Fournier, "Quantitative thermal imaging by synchronous
thermoreflectance with optimized illumination wavelengths," Applied Physics Letters, vol. 78,
2001, p. 2267.
[38]
A. Sarua, H. Ji, M. Kuball, M.J. Uren, T. Martin, K.J. Nash, K.P. Hilton, and R.S. Balmer,
"Piezoelectric strain in AlGaN/GaN heterostructure field-effect transistors under bias," Applied
Physics Letters, vol. 88, 2006, p. 103502.
[39]
P. Makaram, J. Joh, J.A. del Alamo, T. Palacios, and C.V. Thompson, "Evolution of structural
defects associated with electrical degradation in AlGaN/GaN high electron mobility transistors,"
Applied Physics Letters, vol. 96, 2010, p. 233509.
[40]
B. Jogai, J.D. Albrecht, and E. Pan, "Effect of electromechanical coupling on the strain in
AlGaN/GaN heterojunction field effect transistors," Journal of Applied Physics, vol. 94, 2003, p.
3984.
[41]
B. Jogai, J.D. Albrecht, and E. Pan, "Electromechanical coupling in free-standing AlGaN/GaN
planar structures," Journalof Applied Physics, vol. 94, 2003, p. 6566.
[42]
U. Chowdhury, J. Jimenez, C. Lee, E. Beam, P. Saunier, T. Balistreri, J. Wang, M. Kim, and J.
del Alamo, "TEM Observation of Crack- and Pit-Shaped Defects in Electrically Degraded GaN
HEMTs," IEEE Electron Device Letters, vol. 29, 2008, pp. 1098-1100.
[43]
J. Joh and J.A. del Alamo, "Critical Voltage for Electrical Degradation of GaN High-Electron
Mobility Transistors," IEEE Electron Device Letters, vol. 29, 2008, pp. 287-289.
[44]
E. Zanoni, F. Danesin, M. Meneghini, A. Cetronio, C. Lanzieri, M. Peroni, and G. Meneghesso,
"Localized Damage in AlGaN/GaN HEMTs Induced by Reverse-Bias Testing," IEEE Electron
Device Letters, vol. 30, 2009, pp. 427-429.
[45]
S. Park, T. Lee, and M. Kim, "Correlation between Physical Defects and Performance in
AlGaN/GaN High Electron Mobility Transistor Devices," Transactions on Electrical and
Electronic Materials,vol. 11, 2010, pp. 49-53.