CSC Track-Finder
HW/SW Update
Bobby Scurlock, UF
Darin Acosta, UF
Alex Madorski, PNPI
Lev Uvarov, PNPI
Victor Golovtsov, PNPI
CMS Week: Trigger Meeting, June 2002. B. Scurlock, University of Florida
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New Track-Finder
Track-Finder Crate
Crate Design
Design
New
Clock and Control
Board
Muon Sorter
SR SR SR SR SR SR
/ / / / / /
SP SP SP SP SP SP
MS
CCB
Single Track-Finder Crate Design with 1.6 Gbit/s optical links
BIT3 Controller
•
SR SR SR SR SR SR
/ / / / / /
SP SP SP SP SP SP
From Trigger
Timing &
Control
SR/SP Card
(3 Sector Receivers +
Sector Processor)
(60° sector)
From MPC
(chamber 4)
From MPC
(chamber 3)
From MPC
(chamber 2)
From MPC
(chamber 1B)
From MPC
(chamber 1A)
To
Global Trigger
–
–
–
–
To DAQ
Reduces SR/SP processing time from 21 bx (old design) to 7 bx
Crate Power Consumption ~ 1000 W
16 Optical connections per SR/SP card
Custom Backplane for SR/SP ⇔ CCB and MS connection
CMS Week: Trigger Meeting, June 2002. B. Scurlock, University of Florida
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CSC Track
Track Finder
Finder Backplane
Backplane
CSC
Florida
Standard VME 64x J1/P1 backplane
SRSP 12
SRSP 11
SRSP 10
SRSP 9
SRSP 8
SRSP 7
Muon sorter
Clock and control
SRSP 6
SRSP 5
SRSP 4
SRSP 3
SRSP 2
SRSP 1
Standard VME
J2/P2 backplane
GTLP backplane
avoids latency
penalty of previous
Channel-Link
backplane (~3BX)
Rice
Design Approved
–
Technology
same as EMU
peripheral crates
Custom GTLP 6U backplane
CMS Week: Trigger Meeting, June 2002. B. Scurlock, University of Florida
These SRSP
feedthru connectors
are for DT
information
exchange via
transition board
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DT-CSC Interface
Interface Specified
Specified
DT-CSC
• DT/CSC transition board pinout specified
• Connector pinout to DT/CSC transition board defined
• Would like to specify DT/CSC cable pinout
• CMS IN 2002/040 released
DT TF→ CSC TF
CSC TF→ DT TF
CMS Week: Trigger Meeting, June 2002. B. Scurlock, University of Florida
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SR/SP 2002
2002 Board
Board Layout
Layout
SR/SP
New Mezzanine Card has 6
Connectors - Allows>800
I/O signals to the main
FPGA
From
CCB
To
Muon
Sorter
To/From
Barrel
CMS Week: Trigger Meeting, June 2002. B. Scurlock, University of Florida
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SR LUT
LUT Triad
Triad
SR
FRONT
FRONT
FPGA
FPGA
A18
CLCT PAT# - 4
Q-4
CLCT_ID - 8
L/R -1
C3
A11
PHIL LUT
256K x 18
Flow
Through
SRAM
Phi_L -10
PhiB_L - 6
PhiB_L - 6
Phi_L - 2
CSC_ID - 4
WG_ID - 7
ETAG LUT
512K x 18
Flow
Through
SRAM
PhiB_G - 5
Eta_G - 7
MAIN
MAIN
FPGA
FPGA
CSC_ID – 4
WG_ID – 7
Identical for all
tracks.
Contents depend on
Sector or Station
CSC ID - 4
CLK40P1
C3
D16
16 Bit
C2
Trans
ceiver
Phi_L - 10
WG_ID - 5
CSC_ID - 4
PHIG LUT
512K x 36
Flow
Through
SRAM
All are synchronous
GSI memories. Plan to
use same technology
for Pt LUTs.
Phi_G -12
Phi_DT - 12
To DT
C4
CLK40P2
D12
Trans
ceiver
C2
CLK40
16 Bit
Legend: A – Address Lines
D - Data Lines
C – Control Lines
CLK – Clock
CLK40
•SR now has 3 memories rather than 6 per stub [total of 45 per board]. Need to
define their contents. LUTs are created in ORCA, but have yet to be tested.
•>64 MB per board ⇒ Need high VME bandwidth, broadcast capability to identical
chips, and crate broadcast capability to SPs
CMS Week: Trigger Meeting, June 2002. B. Scurlock, University of Florida
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SR/SP 2002
2002 Design
Design Status
Status
SR/SP
• Schematics Complete:
– Sector Receiver Front FPGAs (5 total)
• Choice: XC2V1000-FF896C with 432 user I/Os
– Sector Processor Main FPGA
• Choice: XC2V4000-FF1152C with 824 user I/Os
• Placed on mezzanine card (design started)
• Firmware written in “Verilog++”, validated by simulation
– VME & control interface FPGA
• Choice: XC2V250-FG456C with 200 user I/Os
– DAQ Interface FPGA
• Choice: XC2V250-FG256C with 172 user I/Os
– SRAM:
• 51 SRAM chips (>64MB) for Look-up functionality
• May require BGA packages to allow more space for routing
• Layout to commence soon
– Board will be dense! (Merger of 4 boards, but I/O ~same)
CMS Week: Trigger Meeting, June 2002. B. Scurlock, University of Florida
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Software Update
Update
Software
• Verilog++ SP model implemented and LUTs generated in
ORCA.
• Also need to add Bunch Crossing Analyzer and Ghost
Busting [background reduction] to Verilog++ model.
• Phi and Eta SR LUT Contents Have Been Specified in
ORCA. [Thank You Slava Valouev!]
• Work underway to attach track-stub data to tracks in
Verilog++ model and in DAQ (this will be useful for L2
Trigger).
CMS Week: Trigger Meeting, June 2002. B. Scurlock, University of Florida
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Software Update
Update
Software
• Currently examining alternative bend patterns in CLCT Processor to improve
φ resolution and Pt assignment.
• First attempt will be using patterns from CMSIM100 ⇒ Bend value based only
on the number of strips extended. For example:
CMS Week: Trigger Meeting, June 2002. B. Scurlock, University of Florida
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Test Software
Software Update
Update
Test
We have started working on integrating software
written for the 2000 TF crate tests into the XDAQ
environment.
Screen shot of
the Hardware
configuration
GUI.
CMS Week: Trigger Meeting, June 2002. B. Scurlock, University of Florida
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Schedule
Schedule
• November 2002: expect to finish the SP protoype. Will
conduct single board tests
• MPC→SR/SP tests will continue through to 4/30/03.
• 5/1/03 to 9/30/03: Plan chain tests with CSC chambers and
front-end electronics using cosmic rays and test beam.
• Also plan to do DT↔CSC tests sometime after May 1 2003.
CMS Week: Trigger Meeting, June 2002. B. Scurlock, University of Florida
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Conclusions
Conclusions
• CSC TF Backplane Specified
• DT-CSC Interface Specified
• SR/SP Schematics Complete
• SR/SP Layout Started
• SR LUT Generation Completed in ORCA
• More Additions Scheduled for Verilog++ SP Model
• Work on φb Definition in Progress
CMS Week: Trigger Meeting, June 2002. B. Scurlock, University of Florida
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