Lab
21
JK and T Flip-Flops
Name _______________________________________
Objectives
Class ______________
Date
Upon completion of this laboratory exercise, you should be able to:
• Use the Quartus II Block Editor to create a circuit for an asynchronous binary
counter, using JK or T flip-flops.
• Create a simulation that verifies the operation of the counter made with
JK flip-flops.
• Test the counters on a CPLD test board.
Reference
Equipment
Required
Dueck, Robert K., Digital Design with CPLD Applications and VHDL, 2/e
Chapter 8: Introduction to Sequential Logic
8.2
NAND/NOR Latches
8.5
Edge-Triggered JK Flip-Flops
8.6
Edge-Triggered T Flip-Flops
CPLD Trainer:
Altera UP-2 circuit board with ByteBlaster Download cable, or
DeVry eSOC board with Straight-Through Parallel Port cable, or
RSR PLDT-2 circuit board with Straight-Through Parallel Port cable, or
equivalent CPLD trainer board with Altera EPM7128S CPLD
Quartus II Web Edition software
AC adapter, minimum output: 7 VDC, 250 mA DC
Anti-static wrist strap
#22 solid-core wire
Wire strippers
Experimental Notes
•
The JK flip-flop can operate in a number of synchronous modes, which include no change (JK = 00),
reset (JK = 01), set (JK = 10), and toggle (JK = 11). One of the more useful modes of the JK flipflop is the toggle mode, which allows the device to be used as an element in a binary counter. If
several flip-flops are all configured to toggle, they can be arranged so that the Q output on one
flip-flop clocks the next one. If the flip-flops are negative-edge triggered, the effect of this
arrangement is to generate a binary count sequence.
The T (“toggle”) flip-flop can fulfill the same function as a JK flip-flops. It has a synchronous
input called T, which switches the flip-flop between a toggle mode (when T = 1) and a no change
mode (when T = 0). If a T flip-flop is configured to toggle on each clock pulse, it can be directly
substituted into a circuit that uses JK flip-flops for the same function.
In addition to the synchronous JK and T inputs, both types of flip-flops have asynchronous
clear and preset functions. These functions act immediately when made LOW to set the Q output
of the flip-flop to 0 (when preset = 0) or to 1 (when clear = 0). The primary use of these functions
is to set the flip-flop to a known initial state, from which point functions are usually determined
by the state of the synchronous inputs and the clock.
175
176
Lab 21
Procedure
•
Asynchronous Counter (JK Flip-Flops): Design Entry and Simulation
1. Create a 4-bit asynchronous counter in the Quartus II Block Editor, as shown in Figure 21.1,
and save it as drive:\qdesigns\labs\lab21\asynch_ctr_JK\asynch_ctr_JK.bdf. Use the file
to create a new project.
Figure 21.1
4-Bit Asynchronous Binary Counter
2. Write a set of simulation criteria to verify the correctness of the circuit design. Use these
criteria to make a Quartus II simulation. Show the criteria and the simulation to your
instructor.
Simulation Criteria
Instructor’s Initials _________
JK and T Flip-Flops
177
Test Circuit
If we are to download the circuit of Figure 21.1 directly to a CPLD test board, we would need to
apply a clock pulse to the clock input of the circuit, either from the on-board oscillator or from a
manual pushbutton. If we did this one of two things would happen. If we used the oscillator,
which runs at several megahertz, the counter outputs would run so fast that we would not be able
to observe them change on the board LEDs. If we used the pushbutton, the counter would not
progress in a predictable fashion, due to the mechanical bounce of the pushbutton switch. This
requires us to use a clock divider or a switch debouncer for reliable operation that is slow enough
to observe visually.
The simplest means of debouncing a switch is to use a NAND latch, as described in
Section 8.2 of Digital Design with CPLD Applications and VHDL, 2/e. Unfortunately, this
requires a switch with a normally closed and a normally open contact, which is not available to us
on the CPLD test boards for which these labs are designed.
Our CPLD test boards have pushbuttons, each of which has only a single normally open
contact. This type of switch can be debounced using a clocked component called debouncer.vhd,
whose use is shown in Figure 21.2 (for the RSR PLDT-2 board) and Figure 21.3 (for the Altera
UP-2 and DeVry eSOC boards). The VHDL code for this debouncer is available on the CD that
accompanies Digital Design with CPLD Applications and VHDL, 2/e, in a folder called
Student_Lab_Files. This VHDL file can be copied to the working folder for a project and used to
make a debouncer component, as shown in Figures 21.2 and 21.3.
Figure 21.2
4-Bit Counter with Switch Debouncer (RSR PLDT-2)
Figure 21.3
4-Bit Counter with Switch Debouncer (Altera UP-2 and DeVry eSOC)
1. Modify the counter circuit shown in Figure 21.1 to make either the circuit in Figure 21.2 (for
the RSR PLDT-2 board) or Figure 21.3 (for the Altera UP-2 or DeVry eSOC board). Note
that the Q outputs in the circuit in Figure 21.3 are inverted to adapt them to the active-LOW
LEDs of the Altera UP-2 and DeVry eSOC boards.
178
Lab 21
2. Assign pin numbers to the design as follows and compile the project.
Pin Numbers
Function
pb_in
clock
reset
q3
q2
q1
q0
UP-2
11
83
1
49
50
51
52
PLDT-2
11
83
1
49
50
51
52
eSOC
70
83
1
10
11
12
15
3. Program your CPLD test board with the asynchronous counter design. Connect pb_in to a
pushbutton on the board and reset to another pushbutton. Connect the q outputs to LEDs, if
not already connected. It is not necessary to make a direct connection to pin 83 (clock), as
this connection is hardwired to the CPLD on your test board.
4. Demonstrate the operation of the counter to your instructor.
Instructor’s Initials _________
Asynchronous Counter (T Flip-Flops)
1. Replace the JK flip-flops in Figure 21.2 or 21.3 with T flip-flops. The symbol name for a
T Flip-Flop is TFF.
2. Compile the project and use it to program your board.
3. Show the modified Block Diagram File to your instructor and demonstrate the operation of
the new circuit.
Instructor’s Initials _________