CSE477
VLSI Digital Circuits
Fall 2002
Lecture 27: System Level Interconnect
Mary Jane Irwin ( www.cse.psu.edu/~mji )
www.cse.psu.edu/~cg477
[Adapted from Rabaey’s Digital Integrated Circuits, ©2002, J. Rabaey et al.]
CSE477 L27 System Interconnect.1
Irwin&Vijay, PSU, 2002
Nature of Interconnect
Local Interconnect
Global Interconnect
CSE477 L27 System Interconnect.2
Irwin&Vijay, PSU, 2002
Global Interconnect

System level signal interconnect - buses

Vdd and Gnd planes

System clock
CSE477 L27 System Interconnect.3
Irwin&Vijay, PSU, 2002
Impact of Interconnect Parasitics

Reduced reliability

Reduced performance

Classes of parasitics



CSE477 L27 System Interconnect.4
capacitive
resistive
inductive
Irwin&Vijay, PSU, 2002
System Level Signal Interconnect
Wout
Xout
Yout
Bus
receivers
Zout
Bus
Ain
Bin
Cin
Din

Many drivers - only one active at a time

Many receivers - many may be active at a time
CSE477 L27 System Interconnect.5
Tristate
Bus
drivers
Irwin&Vijay, PSU, 2002
Tristate Buffers
Three states - 0, 1, and z (high impedance)
In
Out
En
0
In
1
CSE477 L27 System Interconnect.6
1
0
!En
!In
Out
En
z (disconnected)
Irwin&Vijay, PSU, 2002
Reducing Effective Capacitance
Wout
Wout
Xout
Yout
Xout
Zout
Ain
Bin
Yout
Ain
Bin
Cin
Din
Cin

Zout
Din
Shared resources may also incur extra switching activity
CSE477 L27 System Interconnect.7
Irwin&Vijay, PSU, 2002
Driving Large Capacitances
In
Out
CL
tpHL
CL Vswing/2
= ------------Iav
Increase with transistor sizing
ID = k’/2 W/L (…)
CSE477 L27 System Interconnect.8
Irwin&Vijay, PSU, 2002
Single Inverter as buffer
A
U*A
1
u
In
Cin
CL = x. Cin
Total propogation delay = tp(inv) + tp(buffer)
tp0 - delay of minimum sized inverter with single minimum
sized inverter for fanout
tp = u. tp0 + x/u tp0
uopt = sqrt(x); tp,opt = 2 tp0. Sqrt(x)
CSE477 L27 System Interconnect.9
Irwin&Vijay, PSU, 2002
Use Cascaded Buffers
in
Cin
1
C1
3
1
uN-1
u2
u
C2
9
3
out
CL
27
9
81
27
CL = xCin = uN Cin
uopt = e
CSE477 L27 System Interconnect.11
Irwin&Vijay, PSU, 2002
tp as a Function of u and x
u/ln(u)
60.0
40.0
x=10,000
x=1000
20.0
x=100
x=10
0.0
1.0
3.0
5.0
7.0
u
CSE477 L27 System Interconnect.12
Irwin&Vijay, PSU, 2002
Impact of Cascading Buffers
x
Unbuffered
Single
Cascaded
Buffers
10
10
Buffer
6.3
100
100
20
12.5
1,000
1,000
63
18.8
chip bus
10,000
10,000
200
25
I/O pads
6.3
topt /tp0 versus x for various driver configurations
Cin = 10 fF in 1 micron CMOS
CSE477 L27 System Interconnect.13
Irwin&Vijay, PSU, 2002
Designing Large Transistors
D(rain)
S
D
G
D
S
S(ource)
G(ate)
Small transistors in parallel
CSE477 L27 System Interconnect.14
Circular transistors
Irwin&Vijay, PSU, 2002
Capacitive Coupling (Crosstalk)

Signal wire glitches as large as 80% of the supply
voltage will be common due to crosstalk between
neighboring wires as feature sizes continue to scale
Crosstalk vs. Technology
Pulsed Signal
0.12m CMOS
0.16m CMOS
Black line quiet
Red lines pulsed
0.25m CMOS
Glitches strength vs technology
0.35m CMOS
From Dunlop, Lucent, 2000
CSE477 L27 System Interconnect.15
Irwin&Vijay, PSU, 2002
Battling Capacitive Crosstalk

Avoid parallel lines

Use shielding
shielding
wire
signal
wire
GND
Vdd
shielding layer
GND
substrate (GND)
CSE477 L27 System Interconnect.16
Irwin&Vijay, PSU, 2002
Inductive Effects

When wires are sufficiently long or circuits are
sufficiently fast, inductance of the wire starts to
dominate the delay behavior
r
r
l
r
l
r
l
Vin
x
g

l
c
g
c
g
c
Vout
g
c
Must consider wire transmission line effects
Wave mode instead of diffusion equations used so far
 Signal alternately transfers energy from capacitive to
inductive modes
CSE477 L27 System Interconnect.17
Irwin&Vijay, PSU, 2002

Transmission Line Considerations

Transmission line effects should be considered when the
rise or fall time of the input signal is smaller than the
time-of-flight of the transmission line
Rule of Thumb
tr (tf) < 2.5 tflight = 2.5 L/v
CSE477 L27 System Interconnect.18
Irwin&Vijay, PSU, 2002
Power and Ground Distribution
GND
VDD
Logic
Logic
VDD
GND
(a) Finger-shaped network
CSE477 L27 System Interconnect.19
VDD
GND
(b) Network with multiple supply pins
Irwin&Vijay, PSU, 2002
Next Lecture and Reminders

Next lecture

Design for test
- Reading assignment – Rabaey, et al, xx

Reminders



Project final reports due today
Final grading negotiations/correction (except for the final
exam) must be concluded by December 10th
Final exam scheduled
- Monday, December 16th from 10:10 to noon in 118 and 121
Thomas
CSE477 L27 System Interconnect.20
Irwin&Vijay, PSU, 2002