CSE477
VLSI Digital Circuits
Fall 2002
Lecture 21: Multiplier Design
Mary Jane Irwin ( www.cse.psu.edu/~mji )
www.cse.psu.edu/~cg477
[Adapted from Rabaey’s Digital Integrated Circuits, ©2002, J. Rabaey et al.]
CSE477 L21 Multiplier Design.1
Irwin&Vijay, PSU, 2002
Review: Basic Building Blocks

Datapath

Execution units
- Adder, multiplier, divider, shifter, etc.



Control


Finite state machines (PLA, ROM, random logic)
Interconnect


Register file and pipeline registers
Multiplexers, decoders
Switches, arbiters, buses
Memory

Caches (SRAMs), TLBs, DRAMs, buffers
CSE477 L21 Multiplier Design.2
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Review: Binary Adder Landscape
synchronous word parallel adders
ripple carry adders (RCA)
carry prop min adders
T = O(N), A = O(N)
signed-digit
adders
fast carry prop
adders
residue adders
T = O(1), A = O(N)
Manchester
carry chain
T = O(N)
A = O(N)
CSE477 L21 Multiplier Design.3
carry
select
parallel
prefix
conditional
sum
T = O(log N)
A = O(N log N)
carry
skip
T = O(N),
A = O(N)
Irwin&Vijay, PSU, 2002
Multiply Operation

Multiplication as repeated additions
N
multiplicand
multiplier
partial
product
array
N
can be formed in parallel
double precision product
2N
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Shift & Add Multiplication

Right shift and add




Partial product array rows are accumulated from top to bottom
on an N-bit adder
After each addition, right shift (by one bit) the accumulated
partial product to align it with the next row to add
Time for N bits
Tserial_mult = O(N Tadder) = O(N2) for a RCA
Making it faster

Use a faster adder

Use higher radix (e.g., base 4) multiplication
- Use multiplier recoding to simplify multiple formation


Form partial product array in parallel and add it in parallel
Making it smaller (i.e., slower)

Use an array multiplier
- Very regular structure with only short wires to nearest neighbor
cells. Thus, very simple and efficient layout in VLSI
- Can be easily and efficiently pipelined
CSE477 L21 Multiplier Design.5
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Tree Multiplier Structure
0 D
Q (‘ier)
0 D
multiple
forming
circuits
0 D
0 D (‘icand)
partial
product
array
reduction
tree
fast carry
propagate
adder (CPA)
CSE477 L21 Multiplier Design.6
mux
+
reduction
tree (log N)
+
CPA (log N)
P (product)
Irwin&Vijay, PSU, 2002
(4,2) Counter

Built out of two (3,2) counters (just FA’s!)


all of the inputs (4 external plus one internal) have
the same weight (i.e., are in the same bit position)
the internal output is carried to the next higher
weight position (indicated by the
)
(3,2)
(3,2)
CSE477 L21 Multiplier Design.7
Note: Two carry outs - one
“internal” and one “external”
Irwin&Vijay, PSU, 2002
Tiling (4,2) Counters

(3,2)
(3,2)
(3,2)
(3,2)
(3,2)
(3,2)
Reduces columns four high to columns only two high


Tiles with neighboring (4,2) counters
Internal carry in at same “level” (i.e., bit position weight) as the
internal carry out
CSE477 L21 Multiplier Design.9
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4x4 Partial Product Array Reduction

Fast 4x4 multiplication using (4,2) counters
multiplicand
multiplier
partial
product
array
reduced pp array (to CPA)
double precision product
CSE477 L21 Multiplier Design.11
Irwin&Vijay, PSU, 2002
8x8 Partial Product Array Reduction
How many
(4,2)
counters
minimum
are needed
to reduce it
to 2 rows?
‘icand
‘ier
partial
product
array
Answer: 24
reduced
partial
product array
CSE477 L21 Multiplier Design.13
Irwin&Vijay, PSU, 2002
Alternate 8x8 Partial Product Array Reduction
More (4,2)
counters, so
what is the
advantage?
‘icand
‘ier
partial
product
array
reduced
partial
product array
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Array Reduction Layout Approach
multiplicand
. . .
multiple
generators
(4,2) counter slice
(4,2) counter slice
2
multiple
selection
signals
(‘ier)
(4,2) counter slice
CPA
CSE477 L21 Multiplier Design.15
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Next Lecture and Reminders

Next lecture

Shifters, decoders, and multiplexers
- Reading assignment – Rabaey, et al, 11.5-11.6

Reminders




Project final reports due December 5th
HW5 (last one!) due November 19th
Final grading negotiations/correction (except for the final
exam) must be concluded by December 10th
Final exam scheduled
- Monday, December 16th from 10:10 to noon in 118 and 121
Thomas
CSE477 L21 Multiplier Design.16
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