ECE 576
– Power System
Dynamics and Stability
Lecture 12: Exciters
Prof. Tom Overbye
Dept. of Electrical and Computer Engineering
University of Illinois at Urbana-Champaign overbye@illinois.edu
1

Announcements
•
Read Chapters 4 and 6
•
Homework 3 is posted on the web; it is due on
Thursday Feb 25
•
Midterm exam is moved to March 31 (in class) because of the ECE 431 field trip on March 17
•
We will have an extra class on March 7 from 1:30 to
3pm in 5070 ECEB
–
No classes on Tuesday Feb 23, Tuesday March 1 and
Thursday March 3
2

Self and Separated Excited Exciters
•
The same model can be used for both by just modifying the value of K
E
T
E dE fd dt
 

K
E

S
E
  
E fd

V
R
K
E self

K
E sep

1

 typically K
E self
 
.01


3

Saturation
•
A number of different functions can be used to represent the saturation
•
The quadratic approach is now quite common
S
E
( E fd
)

B E fd

A )
2
An alternative model is S
E
( E fd
)

( fd

A )
2
E fd
•
Exponential function could also be used
S
E
 

A e x x fd
4

Exponential Saturation
K
E

1 S
E

0 .
1 e
0 .
5 E fd
Steady state V
R

1 .
1 e
.
5 E fd
E fd
5

Exponential Saturation Example
Given:
K
E
 
.05
S
E

 E fd max


S
V
E
R


.75
E
 max fd max
1.0

0.27



0.074
Find:
A x
, B x and E fd max
S
E

A x e
B x
E fd
E fd max

4 .
6
A x

.
0015
B x

1 .
14
6

Voltage Regulator Model
Amplifier
T
A dV
R dt
 
V
R

K V
V
R min 
V
R

V
R max
In steady state
Big
K
A

V t
V ref

V ref

V t

V in

V
R
K
A
Modeled as a first order differential equation
There is often a droop in regulation
7

Feedback
•
This control system can often exhibit instabilities, so some type of feedback is used
•
One approach is a stabilizing transformer
Large L t 2 so I t 2

0 V
F

N
2
N
1
L tm dI t 1 dt
8

Feedback
V
F
E fd

R I t 1 t 1
 
L t 1

L tm
 dI t 1 dt dV dt
F


L t 1
R
 t 1
L tm




 
F
N
2
L tm dE fd
N R dt
1 t 1



T
1
F


L t 1
R
 t 1
L tm
 , sV
F
K
F

N
2
L tm
N R
1 t 1

1
T
F

V
F sK E
F fd


F
 sK E
F fd

V
F

1 sK
F
 sT
F
E fd
9

IEEE T1 Exciter
•
This model was standardized in the 1968 IEEE
Committee Paper with Fig 1 shown below
10

IEEE T1 Evolution
•
This model has been subsequently modified over the years, called the DC1 in a 1981 IEEE paper (modeled as the EXDC1 in stability packages)
Note, K
E in the feedback is the same as the 1968 approach
Image Source: Fig 3 of "Excitation System Models for Power Stability Studies,"
IEEE Trans. Power App. and Syst., vol. PAS-100, pp. 494-509, February 1981
11

IEEE T1 Evolution
•
In 1992 IEEE Std 421.5-1992 slightly modified it, calling it the DC1A (modeled as ESDC1A)
Same model is in 421.5-2005
Image Source: Fig 3 of IEEE Std 421.5-1992
V
UEL is a signal from an underexcitation limiter, which we'll cover later
12

Initialization and Coding: Block
Diagram Basics
•
To simulate a model represented as a block diagram, the equations need to be represented as a set of first order differential equations
•
Also the initial state variable and reference values need to be determined
•
Next several slides quickly cover the standard block diagram elements
13

Integrator Block
K
I u y s
•
Equation for an integrator with u as an input and y as an output is dy

K u
I dt
•
In steady-state with an initial output of y
0
, the initial state is y
0 and the initial input is zero
14

First Order Lag Block u
K y
Input
Output of Lag Block
•
Equation with u as an input and y as an output is dy

1 dt T

Ku
 y

•
In steady-state with an initial output of y
0
, the initial state is y
0 and the initial input is y
0
/K
•
Commonly used for measurement delay (e.g., T
R with IEEE T1) block
15

Derivative Block u
K s
D

D y
•
Block takes the derivative of the input, with scaling K
D and a first order lag with T
D
–
Physically we can't take the derivative without some lag
•
In steady-state the output of the block is zero
•
State equations require a more general approach
16

State Equations for More
Complicated Functions
•
There is not a unique way of obtaining state equations for more complicated functions with a general form

0 u
 
1 du dt
   m m d u dt m


0 y
 
1 dy dt
    n d y d y dt dt n
•
To be physically realizable we need n >= m
17

General Block Diagram Approach
•
One integration approach is illustrated in the below block diagram
Image source: W.L. Brogan, Modern Control Theory ,
Prentice Hall, 1991, Figure 3.7
18

Derivative Example
•
Write in form
K
D s
T
D
1 T
D
 s
•
Hence

0
=0,

1
=K
D
/T
D
,

0
=1/T
D
•
Define single state variable x, then dx dt
 
0 u
 
0 y
  y
T
D y
  
1 u
 
K
D u
T
D
Initial value of x is found by recognizing y is zero so x = -

1 u
19

Lead-Lag Block u

A

B y input
Output of Lead/Lag
•
In exciters such as the EXDC1 the lead-lag block is used to model time constants inherent in the exciter; the values are often zero (or equivalently equal)
•
In steady-state the input is equal to the output
•
To get equations write in form with

0
=1/T
B
,

1
=T
A

0
=1/T
B
/T
B
, 
A
T
1
B
 s
T
T
A
B
1 sT
B

1 T
B
 s
20

Lead-Lag Block
•
The equations are with

0
=1/T
B
,

1

0
=1/T
B
=T
A
/T
B
, then dx dt
 
0 u
 
0 y

1
T
B
 u
 y
 y
  
1 u
 
T
A
T
B u
The steady-state requirement that u = y is readily apparent
21

Limits: Windup versus Nonwindup
•
When there is integration, how limits are enforced can have a major impact on simulation results
•
Two major flavors: windup and non-windup
•
Windup limit for an integrator block u dv

K u
I dt
K
I s
L max
The value of v is
NOT limited, so v y its value can
"windup" beyond
L min
If L min
 v

L max else If v < L min then y = v then y = L min
, else if v > L max then y = L max the limits, delaying backing off of the limit
22

Limits on First Order Lag
•
Windup and non-windup limits are handled in a similar manner for a first order lag u
K v
L max
L min y dv

1 dt T
( Ku
 v )
If L min
 v

L max else If v < L min then y = v then y = L min
, else if v > L max then y = L max
Again the value of v is
NOT limited, so its value can "windup" beyond the limits, delaying backing off of the limit
23

Non-Windup Limit First Order Lag
•
With a non-windup limit, the value of y is prevented from exceeding its limit u
K
L max y dy

1 dt T

Ku
 y

(except as indicated below)
L min
If L min

y

L max
then normal dy

1 dt T

Ku
 y

If y

L max
then y=L max u
If y

L min
then y=L min u dy

0 dt dy

0 dt
24

Lead-Lag Non-Windup Limits
•
There is not a unique way to implement non-windup limits for a lead-lag.
This is the one from
IEEE 421.5-1995
(Figure E.6)
T
2
> T
1
, T
1
> 0, T
2
If y > A , then x = A
> 0
If y < B , then x = B
If A
 y

B , then x = y
25

Ignored States
•
When integrating block diagrams often states are ignored, such as a measurement delay with T
R
=0
•
In this case the differential equations just become algebraic constraints
•
Example: For block at right, as T

0, v=Ku
K v
L max u
1
 sT y
L min
•
With lead-lag it is quite common for T
A
=T
B
, resulting in the block being ignored
26

IEEE T1 Example
•
Assume previous GENROU case with saturation. Then add a IEEE T1 exciter with Ka=50, Ta=0.04, Ke=-0.06,
Te=0.6, Vr max
=1.0, Vr min
= -1.0 For saturation assume
Se(2.8) = 0.04, Se(3.73)=0.33
•
Saturation function is 0.1621(Efd-2.303) 2 (for Efd >
2.303); otherwise zero
•
Efd is initially 3.22
•
Se(3.22)*Efd=0.437
•
(Vr-Se*Efd)/Ke=Efd
•
Vr =0.244
•
Vref = 2.44/Ka = 0.0488 B4_GENROU_Sat_IEEET1
27

IEEE T1 Example
•
For 0.1 second fault (from before), plot of Efd and the
• terminal voltage is given below
Initial V
4
=1.0946, final V
4
=1.0973
–
Steady-state error depends on the value of Ka
Gen Bus 4 #1 Term . PU
Gen Bus 4 #1 Field Voltage (pu)
3.5
3.45
3.4
3.35
3.3
3.25
3.2
3.15
3.1
3.05
3
2.95
2.9
2.85
0 0.5
1 1.5
2 2.5
3 3.5
4 4.5
5
Time
5.5
6 6.5
7
Gen Bus 4 #1 Field Voltage (pu)
7.5
8 8.5
9 9.5
10
0.95
0.9
0.85
0.8
1.1
1.05
1
0.75
0.7
0.65
0 0.5
1 1.5
2 2.5
3 3.5
4 4.5
5
Time
5.5
6 6.5
Gen Bus 4 #1 Term. PU
7 7.5
8 8.5
9 9.5
10
28

IEEE T1 Example
•
Same case, except with Ka=500 to decrease steady-state error, no Vr limits; this case is actually unstable
Gen Bus 4 #1 Field Voltage (pu)
12
11
10
7
6
9
8
3
2
5
4
1
0
-5
-6
-7
-8
-9
-1
-2
-3
-4
0 0.5
1 1.5
2 2.5
3 3.5
4 4.5
5
Time
5.5
6 6.5
7
Gen Bus 4 #1 Field Voltage (pu)
7.5
8 8.5
9 9.5
10
Gen Bus 4 #1 Term . PU
1.15
1.1
1.05
1
0.95
0.9
0.85
0.8
0.75
0.7
0.65
0 0.5
1 1.5
2 2.5
3 3.5
4 4.5
5
Time
5.5
6 6.5
Gen Bus 4 #1 Term. PU
7 7.5
8 8.5
9 9.5
10
29

IEEE T1 Example
•
With Ka=500 and rate feedback, Kf=0.05, Tf=0.5
•
Initial V
4
=1.0946, final V
4
=1.0957
Gen Bus 4 #1 Field Voltage (pu)
8
7.5
7
6.5
6
5.5
5
4.5
4
3.5
3
0 0.5
1 1.5
2 2.5
3 3.5
4 4.5
5
Time
5.5
6 6.5
7
Gen Bus 4 #1 Field Voltage (pu)
7.5
8 8.5
9 9.5
10
Gen Bus 4 #1 Term . PU
0.75
0.7
0.65
0.9
0.85
0.8
1.1
1.05
1
0.95
0 0.5
1 1.5
2 2.5
3 3.5
4 4.5
5
Time
5.5
6 6.5
Gen Bus 4 #1 Term. PU
7 7.5
8 8.5
9 9.5
10
30