FAMU-FSU
College of Engineering
EEL 3705 / 3705L
Digital Logic Design
Spring 2007
Instructor: Dr. Michael Frank
Module #13: Latches and Flip-Flops
(Thanks to Dr. Perry for some slides)
FAMU-FSU College of Engineering
Topics covered in this Module

Topic 3. Sequential Digital Logic

Subtopic 3.1. Basic Sequential Elements:
Latches & Flip-Flops.


3.2.1. Basic (SR, D, JK) latch/FF implementations
using logic gates
3.2.2. Implementations using CMOS transmission
gates.

CIO 7. [LatchFF] Analyze characteristic tables and
timing diagram of D latches and D flip-flops.
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Outline of Lecture

Fundamental concepts of sequential logic:



Storing bits of state info. using bistable elements
Latches versus flip-flops
Sequential updating of state information


Simple latch designs

Switch-based, transmission-gate based, logic-gate based



Finite State Machine models
Distinction between static vs. dynamic latches
SR latches and D latches
Simple flip-flop designs


Transmission-gate based, logic-gate based
D flip-flops and JK flip-flops
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Combinational vs. Sequential Logic

Combinational logic circuits:

Contain no feedback loops




Contain feedback loops
Can have persistent memory

As soon as new inputs are
received, new outputs are
computed directly from them,
and the old outputs are forgotten.

Require an amount of hardware
that is proportional to the number
of operations that must be
performed in an algorithm.


Sequential logic circuits:
Have no persistent memory


Circuit outputs never “wrap back
around” to feed circuit inputs

A given piece of hardware
cannot be reused several times
during the processing of the
same piece of input data.
Can execute iterative algorithms
with low hardware cost, via
sequential reuse


Data is allowed to propagate
through the circuit as fast as it
can, with no external control
Steps of the algorithm may be
carried out by reusing the same
piece of logic hardware over and
over again
Are usually regulated by a clock

Are usually self-timed

Internal bits of state that are not
all necessarily subject to change
as soon as new inputs are
received.

This controls the timing of the
sequence of steps of the
algorithm being carried out
This minimizes the effects of
propagation delay variations
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The Ring Oscillator: The Simplest
Sequential Logic Circuit

Consider connecting three inverters
to each other in a loop, like this:

Go around and around, constantly flipping
its bits, in an infinite loop
Some problems with this circuit:

There are no inputs


1
0
What will this circuit do?


1
0
Output has limited usefulness
Its precise behavior and timing are
uncontrolled
1
0
In this lecture,
we’ll be exploring
design methodologies for building more useful,
well-controlled
sequential circuits.
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Bistable Elements

To store (remember) a bit of information,
you need a bistable element

a physical system that has (at least) two
naturally stable states


Some familiar examples:


I.e., a very slow background rate of spontaneous
transitions between states
Toggle switch, coin on a table
Of course, we can also build bistable
elements electronically!


Charge stored on an isolated capacitor
State of a logic circuit with feedback
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Concept for a Simple Capacitor-Based
Storage Element

Connect one terminal of the
capacitor to a single-pole,
double-throw switch, which
can connect to Vdd (logic high
voltage), GND (logic low
voltage), or to neither.



Connect to Vdd  Store a 1
Connect to GND  Store a 0
Disconnect 

Capacitor holds stored value, for
a time (it gradually decays)
Vdd
GND
Since the stored charge
changes dynamically (on
its own) over time, this is
called dynamic storage.
This method of information storage is the basis
of DRAM (dynamic randomaccess memory).
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Implementing the Capacitive Storage
Concept using Transistors (DRAM cell)




An externally-controlled data input
port in
Externally-controlled
complementary pair of signals p, ~p
controlling a transmission gate
out = M = in
When p=0 (~p=1), transmission gate
is off (nonconducting)

out
Transmission
gate
p
p,~p
2
Value is held capacitively.

C should be substantial
In an actual DRAM cell, the
transmission gate is usually replaced
by a single nFET transistor.

C
out = M = const.


M
in
When “pass” signal p=1 (~p=0),
transmission gate is on (conducting)


~p
Replace the SPDT switch with:
This is the simplest possible
“D latch” (data latch)
in
Dynamic
D latch
M
out
C
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What is a Latch?

A latch is a bistable storage element that
has (at least) two operating modes:

An unlatched or transparent mode, in
which changes to certain inputs are
immediately reflected at the output.

An unlatched latch allows data to pass through
it unimpeded


Like an unlatched latch on a baby gate allows
toddlers to pass through unimpeded
A latched or held mode, in which the
output remains stable (at the stored value)
regardless of what is happening to the latch
inputs.

The information is “latched in place” and is
remembered, as long as we are in this mode
My Data
FAMU-FSU College of Engineering
A Basic Static Bistable Element –
Cross-Coupled Inverters

Clearly, the logic circuit at
right has two stable states…


It can thus serve as a bistable
storage element.
0
0
1
It is called a “static” storage
element,

because the voltage levels
will remain stable
indefinitely,


1
as long as power is supplied to
the inverters.
Only question:

How do we change its state?
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A Simple Static D Latch
Using Inverters and Transmission Gates

When p=1, the input in directly connects to the
storage node M


Just like in the DRAM case.
When p=0, the input is disconnected, and M is
instead driven by the bottom inverter

And is thus maintained at the same value, ~~M = M.
p,~p
out
M
in
~p,p
~M
# of
transistors:
8 (2 in ea.
inverter &
ea. T-gate)
Compare to the dynamic D latch of a few slides back
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Characteristic Table of D Latch
p
in
out
(qt)
1
0
0
1
1
1
0
d
qt−1
output is the same
as a moment before
p
1
0
in
x
d
out
(qt)
x
qt−1
abbreviated version
transparent
latched
FAMU-FSU College of Engineering
Set-Reset (SR) Latch Using NAND Gates

Replace inverters in the previous example with NAND gates


Use extra inputs of gates, instead of T-gates, to control the latch.
If ~S (set) and ~R (reset) are never both asserted,



When ~R is asserted (0), ~M = 1, and so M=0  out.
When ~S is asserted (0), M = 1  out, and ~M = 0.
When neither is asserted (both are 1), the NANDs become equivalent
to NOTs, and the circuit holds its state like cross-coupled inverters.
out
~R
~S
M
~R
~M
~M
~S
M
the same circuit drawn in two different ways
out
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Characteristic Table of SR Latch
~S
0
1
1
0
~R
1
0
1
0
out
(qt)
1
0
qt−1
error
“set” (to 1) asserted
“reset” (to 0) asserted
not
latched
latched
Output is 1 in this particular circuit,
but will be undefined after ~S and ~R
get deasserted. Because of this, this
input case is “illegal” (disallowed).
FAMU-FSU College of Engineering
Building a D latch from an SR latch

Incorrect attempt #1: Since R=0 causes out=0, let’s rename
~R to D (data in), and generate ~S from the complement of D,
so that when D=1, we’ll get out=1.


Can you see the problem with this design?
It passes data through OK… But, this “latch” is always unlatched!

It’s logically equivalent to a wire that connects D directly to out.
D
~R
~S

~M
M
Clue: There is no
input to control
the latch mode!
out
How do we fix this problem? (See next slide.)
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Completed D-latch Design

To turn that fancy wire back into a latch, we need to add a
“latched” mode, in which both ~S and ~R are deasserted (1).


Generate ~S and ~R with two NAND gates, which will output 1
whenever the ~L “latch” input is asserted (0).
When ~L = 1 (deasserted), these NANDs act like NOTs, and copy D
and its complement over to ~R and ~S, resp.
~D
D
~L
~R
~S
~M
M
out
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Characteristic Table of This D Latch
Same as the previous D latch example,
just using different symbols for the inputs.
~L
1
0
D
x
d
out
(qt)
x
qt−1
transparent
latched
FAMU-FSU College of Engineering
Sequential Logic with Latches

Given just latches, we can directly
implement any desired sequential
algorithm as follows:

When a “clock” signal goes high, the
upper bank of latches goes transparent


Then, when the clock goes low, the
upper latches latch, and the lower bank
of latches goes transparent.


And the right-hand combinational
logic receives new inputs and
computes new outputs.
Then the left-hand combinational
logic receives new inputs and
computes new outputs
The process repeats each clock cycle,
and the data can be transformed
iteratively over many sequential steps.
clock
~L
comb.
logic
comb.
logic
~L
Possible hazard (race condition):
Both sets of latches may briefly
be transparent, just after a rising
edge… “Fast” signals through
combinational logic may circulate
all the way around & corrupt state
FAMU-FSU College of Engineering
Next Topic: Flip-Flops

A flip-flop is similar to a latch, except that:

Its state is only “unlatched” (subject to change)
for very brief periods


Usually, during a rising or falling edge of some
controlling clock signal
Depending on the particular flip-flop design, the
new output may depend on what the controlling
input was at a considerably earlier time

I.e., the flip-flop may have some significant built-in
internal delay (typically, ½ a clock cycle) between
input sampling and output modification
FAMU-FSU College of Engineering
Common Types of Flip-Flops

SR (set-reset) flip-flop:

Controlled by R and S inputs, like an RS latch


JK flip-flop:


Has inputs named J and K, similar to S and R…
Behavior is very similar to an SR flip-flop


Except that when both J and K are asserted, the flip-flop toggles its state (new
state  NOT old state) on the active clock edge.
T (toggle) flip-flop

Like a JK flip-flop, but lacks separate J and K inputs.


But, state changes are edge-triggered instead of level-enabled.
Is always toggled on the active edge, or if an optional T input is asserted.
D (data) flip-flop

Controlled by a D (data) input, like a D latch

But, state changes are edge-triggered instead of level-enabled
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More slides to come…

Show internal structure of various flip-flops…
FAMU-FSU
College of Engineering
Dr. Perry’s Slides
Following are some old slides by Dr. Perry on
Latches & Flip-Flops, left over from previous
semesters…
Memory Devices
Memory Devices


Data Latch (D-latch)
Flip-flops (edge triggered)



D-FF, D Register
JK-FF
T-FF
Latches
D-Latch Block Diagram
Symbol
D
E
Pre
D
SET
Q
Qn+1
4 inputs: D,E,Pre,Rst
One output: Q
E
CLR
Rst
Q
D = Data Input
E = Enable Input
Pre = Preset Input
Rst = Reset Input
D-Latch
Truth Table
Symbol
D
E
Pre
D
Truth Table
SET
Q
E
CLR
Rst
Q
Qn+1
D
E
Pre
Rst
Qn1
d
d
1
0
0
d
d
0
1
1
d
0
1
1
Qn
0
1
1
1
0
1
1
1
1
1
D-Latch
State Equations
Symbol
D
E
Pre
D
Truth Table
SET
Q
Qn+1
E
CLR
Q
Rst
Equation
(level clock)
Qn 1  EQn  EDn
D
E
Pre
Rst
Qn1
d
d
1
0
0
d
d
0
1
1
d
0
1
1
Qn
0
1
1
1
0
1
1
1
1
1
SR-Latch
State Equations
Symbol
S
R
Pre
S
Truth Table
SET
Q
Qn+1
R
CLR
Q
Rst
Equation
(level clock)
Qn 1  S RQn  S R
S
R
Pre
Rst
Qn1
d
d
1
0
0
d
d
0
1
1
0
0
1
1
Qn
0
1
1
1
0
1
0
1
1
1
1
1
1
1
???
Example
T-FF
D-FF
D-Latch
Simulation
Flip-Flops
D-FF Positive Edge Triggered
Block Diagram
Pre
Symbol
D
D
SET
Q
Clk
CLR
Rst
Q
Qn+1
4 inputs: D,Clk,Pre,Rst
One output: Q
D = Data Input
Clk = Clock Input
Pre = Preset Input
Rst = Reset Input
D-FF Truth Table
Pre
Symbol
D
D
SET
Q
Clk
CLR
Q
Rst
Equation
(rising clock)
Qn1  Dn
Truth Table
Qn+1
D
Clk
d
d
1
0
0
d
d
0
1
1
d
0
1
1
Pre
d
1
1
1
0
1
1
0
1
1
1
1
Rst Qn1
Qn
Qn


D-FF Truth Table
Pre
Symbol
D
D
SET
Q
Clk
CLR
Q
Rst
Equation
(rising clock)
Qn1  Dn
Truth Table
Qn+1
D
Clk
d
d
1
0
0
d
d
0
1
1
d
0
1
1
Pre
d
1
1
1
0
1
1
0
1
1
1
1
Pre= Preset Input (active low)
Rst = Reset Input (active low)
Highest priority
Rst Qn1
Qn
Qn


D-FF Truth Table
Pre
Symbol
D
D
SET
Q
Clk
CLR
Q
Rst
Equation
(rising clock)
Qn1  Dn
Truth Table
Qn+1
D
Clk
d
d
1
0
0
d
d
0
1
1
d
0
1
1
Pre
d
1
1
1
0
1
1
0
1
1
1
1
D = Data Input
Clk = Clock input
Qn = Register Output
Rst Qn1
Qn
Qn


D-FF Truth Table
Qn follows D on Rising Edge of CLK
Pre
Symbol
D
D
SET
Q
Clk
CLR
Q
Rst
Equation
(rising clock)
Qn1  Dn
Truth Table
Qn+1
D
Clk
Pre
Rst
Qn1
d
d
1
0
0
d
d
0
1
1
d
0
1
1
Qn
d
1
1
1
Qn
0


1
1
0
1
1
1
1
D = Data Input
Clk = Clock input
Qn = Register Output
T-FF (Toggle)
Changes state on every tick of CLK
Symbol
T
Pre
T
SET
Q
Qn+1
Clk
CL
R
Q
Rst
Equation
(rising clock)
Qn 1  TQn  T Qn
T
Clk
Pre
Rst
Qn1
D
d
1
0
0
D
d
0
1
1
d
0
1
1
Qn
d
1
1
1
Qn
0


1
1
Qn
1
1
1
Truth Table
Qn
SR-FF
Set =>Qn=1
Reset=>Qn=0
Symbol
Pre
S
S
SET
Q
Qn+1
Clk
R
R
CLR
Q
Rst
Equation (rising clock)
Qn 1  S RQn  S R
S
R
Clk
Pre
Rst
Qn1
d
d
d
1
0
0
d
d
d
0
1
1
d
d
0
1
1
Qn
d
d
1
1
1
Qn
0
0
1
1
Qn
0
1


1
1
0
1
0
1
1
1
1
1

1
1
???

Truth Table
JK-FF
Symbol
Pre
J
J
SET
Q
Qn+1
Clk
K
K
CLR
Q
Rst
Equation (rising clock)
Qn1  JQn  KQn
J
K
Clk
Pre
Rst
Qn1
d
d
d
1
0
0
d
d
d
0
1
1
d
d
0
1
1
Qn
d
d
1
1
1
Qn
0
0
1
1
0
1


1
1
Qn
1
0
1
1
1
1
1

1
1
Qn

Truth Table
0
Example: Design a JK-FF using
only Logic and a D-FF
Symbol
Pre
J
J
SET
Q
Clk
K
K
Rst
CLR
Q
Qn+1
J
K
Clk
Pre
Rst
Qn1
d
d
d
1
0
0
d
d
d
0
1
1
d
d
0
1
1
Qn
d
d
1
1
1
Qn
0
0
1
1
0
1


1
1
Qn
1
0
1
1
1
1
1

1
1
Qn

Truth Table
0
Example
State Table
State Diagram
Reset
J
J
S0
S1
0
1
K
Let s0=0 and s1=1
K
J
K
PS
NS
Y
0
0
0
1
1
0
0
1
1
S0
S1
S0
S1
S0
S1
S0
S1
S0
S1
S0
S0
S1
S1
S1
S0
0
1
0
1
0
1
0
1
0
0
0
1
1
1
1
JK-FF
Truth Table
Logic Equations
J
K
PS
NS
Y
0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
0
1
1
1
0
0
1
0
1
0
1
0
1
0
0
0
1
1
1
1
ns  J ps  K ps
Y  ps
Recall Moore FSM
State Equations
Next
State
Present
State
Output Vector
Input Vector
CL
CL
ns
X
F
R
E
G
ps
H
Clock
clock
Feedback
Path
reset
Reset
State Equations
ns  F  X , ps 
Y  H  ps 
Y
F Logic
JK Example
D-Register
Circuit Schematic
ns
X input
ps
CL
CL
ns
X
F
H Logic
(buffer)
R
E
G
ps
H
Y
Block Diagram
clock
reset
JK Example
Circuit Schematic
Simulation
Memory
Memory

We will add memory (or
registers) to our logic circuits.
This will allow us to design
sequential circuits.
Registers

We will represent registers with the
following block diagram
ns
R
E
G
ps
clock
reset
Clock and reset are control signals
Ns and ps are data signals