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02-Chapter 02
00002054A
0.Oertel R.Reulke R.Sandau M.Scheele
0.5 to 40 A 15 to 1000 V 0.2% DC 0.5 Hz to 100 kHz 0.5
0.5 ppm/°C, Tolerance Match of 0.01 % and
0.05uV/C max, Single-Supply CMOS Op Amps Zero
0.05 uV/C max, Single-Supply CMOS
.... .... ........ imans, Dept. Committee an E~QUIREM~VTS
- SelectedWorks
- Sacramento
- Nottingham ePrints
- Maynooth University ePrints and eTheses Archive
- Harting
A 76.2–89.1 GHz Phase-Locked Loop With 15.6% Tuning Range in
A 7-Level Single DC Source Cascaded H
A 300nW, 12ppm/°C Voltage Reference in a Digital 0.35 µm CMOS
A 270-MHz to 1.5-GHz CMOS PLL clock generator with
a 23 ns and 65 ns Low Voltage Comparators CMP401/CMP402
a 2.5 V to 5.5 V, 500 Quad Voltage-Output 8-/10-/12-Bit DACs AD5334/AD5335/AD5336/AD5344*
A 106-dB SNR Hybrid Oversampling Analog-to
A 1.6nJ/bit, 19.9µA Peak Current Fully Integrated 2.5mm Inductive
A 1-Gb/s, 0.7-/spl mu/m CMOS optical receiver with full rail-to
a Engineer-to-Engineer Note EE-340
a Engineer-to-Engineer Note EE-240
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