Models for the Performance of Clustered
Photolithography Tools with Applications
James R. Morrison
Associate Professor
Industrial & Systems Engineering
©2014 –James R. Morrison – ISMI Keynote II – August 17, 2014 – 1
Presentation Overview
• Motivation
• System description (CPT)
• Models for CPTs
• Some recent flow line theory
• Application opportunities
• Where next?
• Concluding remarks
Clustered
Linear
Photolithography
Affine
TExact
ool (Ax+B)
decomposition
Flow line
Exit recursions
Detailed
Capacity
increase
Markovian
models
Toolset agility
Industry interaction
Fab simulation components
Next development steps
©2014 –James R. Morrison – ISMI Keynote II – August 17, 2014 – 2
Acknowledgements
• Much of the work discussed here was developed with
–
–
–
–
Dr. Kyungsu Park
Dr. Woo-sung Kim
MS student John Park
BS student Hyunsuk Baek
• Several of the slides were prepared by
–
–
–
–
Dr. Kyungsu Park
Dr. Woo-sung Kim
MS student John Park
BS student Hyunsuk Baek
©2014 –James R. Morrison – ISMI Keynote II – August 17, 2014 – 3
Presentation Overview
• Motivation
• System description (CPT)
• Models for CPTs
• Some recent flow line theory
• Application opportunities
• Where next?
• Concluding remarks
©2014 –James R. Morrison – ISMI Keynote II – August 17, 2014 – 4
Motivation (1)
• Semiconductor manufacturing
– Global revenue in 2013: NT$ 9,540 billion (US$ 318 billion)
[1]
• Construction costs
– 300 mm wafer fab:
– 450 mm wafer fab:
NT$150 billion
NT$300-450 billion
(US$ 5 billion [2])
(US$10-15 billion)
• Significant value for improvements
– 1996-1999: Fab production control method earned Samsung NT$ 15
billion (US$ 1 billion [3]) additional revenue
– 2005: IBM’s 30 independent supply chains merged into a single global
system and saved NT$ 180 billion (US$ 6 billion [4])
– …
©2014 –James R. Morrison – ISMI Keynote II – August 17, 2014 – 5
Motivation (2)
• Clustered photolithography tools (CPT)
–
–
–
–
Purchase cost of NT$ 0.6-3 billion (US$ 20-100 M [5])
The most expensive tool in a fabricator
Typically the bottleneck of the fabricator
Key yield and cycle time contributor
[5]
©2014 –James R. Morrison – ISMI Keynote II – August 17, 2014 – 6
Motivation (3)
CPT Vendor: “Our CPTs can run at 120 wph” 
Fab analyst: “Your CPTs can run at 80 wph” 
Who is right?
Exhaustive and exhausting
tool log analysis…
CPT Vendor: “Our CPTs are awesome” 
Fab analyst: “We are disappointed” 
©2014 –James R. Morrison – ISMI Keynote II – August 17, 2014 – 7
Motivation (4)
• Want: Models for CPTs
– Accurate:
Predict throughput with less than 1% error
– Expressive:
Incorporate fundamental behaviors
– Computationally tractable: Very quick to calculate results
• For the purpose of:
–
–
–
–
Understanding toolset performance
Enabling capacity optimization
Toolset scheduling or optimization
Improving the quality of fab simulation models
Discuss in the
application section
©2014 –James R. Morrison – ISMI Keynote II – August 17, 2014 – 8
Presentation Overview
• Motivation
• System description (CPT)
• Models for CPTs
• Some recent flow line theory
• Application opportunities
• Where next?
• Concluding remarks
©2014 –James R. Morrison – ISMI Keynote II – August 17, 2014 – 9
System Description: CPT (1)
[6]
Scanner
Clustered
Photolithography
Tool
•
•
•
•
•
•
Multi-cluster tool, robot in each cluster, IF buffers, STK buffer
Scanner is often the CPT bottleneck
Largely deterministic process times
Process time can vary by product
Setups between lots (reticle changes, pre-scan setup, …)
Wafer handling robot decision policy & deadlock prevention
©2014 –James R. Morrison – ISMI Keynote II – August 17, 2014 – 10
System Description: CPT (2)
Conceptual diagram of a CPT (slightly simplified)
Pre-scan processes
P1
Wafers
Enter
P1
P2
P2
Buffer
Scanner
P6
P4
P3
P5
P4
P2
Wafer handling robots
P11
Wafers
Exit
P11
P8
P9
P10
P8
P9
P11
P7
P8
Post-scan processes
Conceptual diagram of a CPT (robots “removed”)
buffer
buffer
Wafers
Enter
P1
P1
P2
P2
P2
Post-scan
processes
…
Pre-scan
processes
…
buffer
buffer
buffer
buffer
Scanner
P6
P11
…
P11
P11
©2014 –James R. Morrison – ISMI Keynote II – August 17, 2014 – 11
Wafers
Exit
System Description: Performance Metrics
• Notation
– al: arrival time of lot l to the tool queue
– Sl : start time of lot l on a tool
– Cl : completion time of lot l on a tool
– Wl : wafers in lot l
• Performance measures
Computation time
– Cycle time of lot l:
TlCT := Cl - al
– Process time of lot l:
TlPT := Cl - Sl
– Throughput time of lot l: TlTT := min{ TlPT, Cl – Cl-1 }
T1TT
T2TT
T3TT
Lot 1
Lot 2
Lot 3
Time
©2014 –James R. Morrison – ISMI Keynote II – August 17, 2014 – 12
Presentation Overview
• Motivation
• System description (CPT)
• Models for CPTs
• Some recent flow line theory
• Application opportunities
• Where next?
• Concluding remarks
©2014 –James R. Morrison – ISMI Keynote II – August 17, 2014 – 13
Models for CPTs
• Models with various levels of detail
Detailed Model
Linear Model
“Everything”
A(k1)
A(k1), B
Affine Models
A(k1), B(k1)
A(k1), B(k1, k2)
Flow Line
Models
Parametric flow lines
Empirical flow lines
Collect
Tool Log Data
Train a set of
parameters
With complete tool log data
Exit Recursion
Models
With wafer in/out log data
With lot in/out log data
Simulate
models
©2014 –James R. Morrison – ISMI Keynote II – August 17, 2014 – 14
Linear Model
Ax Model for lot cycle time in a one machine tool
Wafers
enter
Wafers
exit
m
Al
•
Referred to as the Ax equipment model or linear model
Pros:
•
•
between
wafer completions:
–TimeSimple
to understand
estimation:
–Process
Fasttime
computation
•
Cons:
Al
PT
Ak1 ∙ w(l)
( w(l):tothe
number
wafers
–Tl =
Exactly
matched
single
waferoftool,
notof
tolot
CPTl )
𝐴 𝑘1 =
𝑙∈𝛺(𝑘1)[𝐶𝑀,𝛺(𝑙,𝑤 𝑙 ) −𝑆(𝑙)]
Complete Model:
𝑆l = max{ al , 𝑉l-1 }
𝐿l = 𝑆l
𝐶 l = 𝑆l + Ak1 ∙ w(l)
𝑉l = 𝐶 l
𝑙∈𝛺(𝑘1) 𝑤(𝑙)
©2014 –James R. Morrison – ISMI Keynote II – August 17, 2014 – 15
Affine Models
𝐴 𝑘1 =
𝑙∈𝛺(𝑘1)[𝐶𝑀,𝛺(𝑙,𝑤 𝑙 )
𝐵=
𝑙∈𝛺(𝑘1)[𝑤
𝑙∈𝛺[𝐶𝑀,𝛺(𝑙,1)
− 𝐶𝑀,𝛺(𝑙,1) ]
𝑙 − 1]
− 𝑆(𝑙)]
𝑙∈𝛺 1
B can be generalized to B(k1), B(k1, k2)
•
Pros:
Complete model:
𝑆l = max{ al , 𝑉l-1 }
𝐿l = 𝑆l
𝐶 l = 𝑆l + B + Ak1 ∙ (w(l) - 1)
𝑉l = 𝐶 l
Simpletotoasunderstand
– • Referred
the Ax+B model
computation
– • FirstFast
wafer
delay:
Bl
Time between wafer completions:
Al
•– Cons:
– • Process
estimation:
Only time
one module
per process, so not matched to CPT
= Ak1
∙ (w(l)
1) +when
Bl the
( w(l)
: the
number of wafers of lot l )
• TlPTNew
lots
enter–only
tool
is empty
©2014 –James R. Morrison – ISMI Keynote II – August 17, 2014 – 16
Flow Line Models – Elementary Evolution Equations
Process i
W
W-1
• Notation
– aw : Arrival time of wafer w to the tool, aw≥ aw-1
– Xi(w) : Entry time of wafer w into process i of the tool
– 𝜏𝑖 : Deterministic process time for process i
• Elementary Evolution Equations (EEEs)
– X1(w) = max{aw , X2(w-1) }
– Xi+1(w) = max{Xi(w) + 𝜏𝑖 , Xi+2(w-1) }
– XM(w) = max{XM-1(w) + 𝜏𝑀−1 , XM(w-1) + 𝜏𝑀 }
(M is the last process)
©2014 –James R. Morrison – ISMI Keynote II – August 17, 2014 – 17
Flow Line Models
Wafers
enter
Wafers
exit
• Elementary Evolution Equations (EEEs) can be generalized to allow:
–
–
–
–
Different classes of wafer to be produced
Multiple modules per process
Consider robotic workload in process times of modules
Consider setups – reticle setup, pre-scan setup
• Parameter extraction
– Parametric flow line model – Known process times, robot times, and setup times
– Empirical flow line model – Parameters extracted from wafer advancement data
©2014 –James R. Morrison – ISMI Keynote II – August 17, 2014 – 18
Exit Recursion Model (1)
• Extend affine models to allow for flow line style behaviors
• Idea:
– Bottleneck analysis approach
– Obtain parameters from limited population
– Example

~
~
Ci  max ai  FWD k (i )  A1k(i)  (Wi  1), Ci 1  A2k(i),k(i 1)  (Wi  1)  B k (i ),k (i 1)
No Contention at bottleneck
Contention at bottleneck
• For only wafer or lot in/out log data,
– Restrict population to account for desired parameter meaning
– Least square method (LSM) to obtain parameters
©2014 –James R. Morrison – ISMI Keynote II – August 17, 2014 – 19

Exit Recursion Model (2)


~
~
~
k(i)
k(i),k(i1)
Ci  max Si  FWDk(i)  A1  (Wi  1), Ci 1  A2
 (Wi  1)  Bk(i),k(i 1)
~
~
k(i),k(i 1)
Si  Li  E

~
~
Li  max ai , Vi 1

~ ~
k(i),k(i 1)
Vi  Ci  D
where
FWD k 

1
FWD(l)
Φ1(k) lΦ (k)
k
A1 
1
B
k1 ,k 2

1
Φ2(k1,k 2 )
 B(l)
lΦ2(k1 ,k 2 )

l Φ1(k)
D
k1 ,k 2


1
A (l )
Wl  1 lΦ (k) 1
1
Φ0 (k1,k2 )
k
A2 
1
 D(l)
lΦ0(k1 ,k 2 )

l Φ 2(k)
E
k1 ,k 2


1
A (l )
Wl  1 lΦ (k) 2
1
Φ0(k1,k2 )
©2014 –James R. Morrison – ISMI Keynote II – August 17, 2014 – 20
2
 E(l)
lΦ0(k1 ,k 2 )
Exit Recursion Model (3)
©2014 –James R. Morrison – ISMI Keynote II – August 17, 2014 – 21
Computational Comparison
Relative Computation Time
Linear Model
0.5
Affine Model
1
ER Model
2.4
FL Model
120
Detailed Simulation
13,000
©2014 –James R. Morrison – ISMI Keynote II – August 17, 2014 – 22
Accuracy Assessment
Different Sample &
Different Parameter
Linear Model
CT
PT
TT
Affine Models
CT
PT
TT
ER Models
CT
PT
TT
Flow Line Models
CT
PT
TT
• Errors relative to detailed model
– Error of 20%+
– Error 5-20%
– Error 0-5%
©2014 –James R. Morrison – ISMI Keynote II – August 17, 2014 – 23
Presentation Overview
• Motivation
• System description (CPT)
• Models for CPTs
• Some recent flow line theory
• Application opportunities
• Where next?
• Concluding remarks
©2014 –James R. Morrison – ISMI Keynote II – August 17, 2014 – 24
Some Recent Flow Line Theory (1): Exit Recursions
• Exit recursions describe wafer flow using a single equation
• Avi-Itzhak, Friedman in 1965 ([7, 8])
…
…
– Random customer arrivals and deterministic service times
P1
Wafer Lots
Arrive
P2
P3
PM
…
t1
t2
t3
tM
Wafer Lots
Exit
• Theorem: Exact recursion for customer completion (exit) times
M


cM k  1  max ak 1  t m , cM k   t B 
m 1


– cM(k) is the completion time of wafer k from process M
– aK is the arrival time of wafer k to the system
– tB is the bottleneck process time
©2014 –James R. Morrison – ISMI Keynote II – August 17, 2014 – 25
Some Recent Flow Line Theory (2): Exit Recursions
…
…
• Multiple servers per process in 2010 ([9])
P1
R1=2
Customers
Arrive
P2
R2=1
P3
R3=3
PM
RM=2
Customers
Exit
…
t1
t2
tM
t3
• Theorem: Recursive bound for customer completion (exit) times
M

(i ) 
C (k )  max ak  t m , max C (k  i )  t max 
iN
m 1




– t(i)max is the bottleneck process time for those processes with i servers
– Conjecture that this is an exact result
©2014 –James R. Morrison – ISMI Keynote II – August 17, 2014 – 26
Some Recent Flow Line Theory (3): Exact Decompositions
• Theorem: Exact channel decomposition in 2010, 2011 ([10, 11])
Channel 1
P1
t1
Channel 2
P2
P3
t2
t3
P4
t4
P5
t5
Channel 3
P6
t6
P7
P8
P9
t7
t8
t9
P10
t10
P11
t11
• Theorem: Can be modeled as a Markov chain in 2014 ([12])
• Theorem: Systems with setups (as in semiconductor
manufacturing) can be modeled and optimized in 2014 ([13])
©2014 –James R. Morrison – ISMI Keynote II – August 17, 2014 – 27
Presentation Overview
• Motivation
• System description (CPT)
• Models for CPTs
• Some recent flow line theory
• Application opportunities
• Where next?
Capacity increase
Toolset agility
Fab modeling components
• Concluding remarks
©2014 –James R. Morrison – ISMI Keynote II – August 17, 2014 – 28
Application Opportunities: Capacity Increase
• Fundamental process/robot bottleneck analysis & mitigation
buffer
buffer
Wafers
Enter
P1
P1
P2
P2
Post-scan
processes
…
Pre-scan
processes
…
P2
buffer
buffer
buffer
buffer
Scanner
P6
P11
…
P11
P11
• More complicated analysis
– Buffer size implications
– Manufacturing environment & mitigation
– Penultimate dominating process
©2014 –James R. Morrison – ISMI Keynote II – August 17, 2014 – 29
Wafers
Exit
Application Opportunities: Toolset Agility
• Wafers are commonly admitted to a CPT as soon as possible
– Deployment opportunity of the lot is reduced
– High priority hot lots experience additional queueing
– Lot/wafer residency time and buffer level greater than required
• Question: When should wafers be admitted to the CPT?
– Maintain throughput capacity
– Minimize residency time and thereby increase agility
©2014 –James R. Morrison – ISMI Keynote II – August 17, 2014 – 30
Application Opportunities: Toolset Agility (2)
Lexicographic Multi-Objective
Linear Program (LMOLP) ([14])
©2014 –James R. Morrison – ISMI Keynote II – August 17, 2014 – 31
Application Opportunities: Toolset Agility (3)
• Results: Detailed CPT model
*
a=0
Lot
Wafer
Hot Lot
Residency Residency Cycle Time
Time (min) Time (min)
(min)
Average
Bufer
Level
Opp.
93.07
57.58
115.47
6.69
Heur.
72.61
31.63
99.50
3.09
Improvement
21.98%
45.06%
13.83%
53.87%
*
Opp.
JIT
Trade-off between
throughput and wafer
residency time
©2014 –James R. Morrison – ISMI Keynote II – August 17, 2014 – 32
Application Opportunities: Fab Simulation/Modeling
• Equipment and fabricator simulations are used to
– Predict value of changes to fabricator capacity
– Predict value of changes to fabricator production control policies
– Predict capacity of fabricators
• Want expressive, accurate and computationally tractable
models to help make decisions on US$ billions
– Future manufacturing facilities will cost US$15 billion
– High quality models enable improved decisions
©2014 –James R. Morrison – ISMI Keynote II – August 17, 2014 – 33
Application Opportunities: Fab Optimization
• Can also be used for model based optimization
– Local toolset production control
– Global fab production control
©2014 –James R. Morrison – ISMI Keynote II – August 17, 2014 – 34
Presentation Overview
• Motivation
• System description (CPT)
• Models for CPTs
• Some recent flow line theory
• Application opportunities
• Where next?
• Concluding remarks
©2014 –James R. Morrison – ISMI Keynote II – August 17, 2014 – 35
Where next?
• Industry application
–
–
–
–
Model based CPT capacity optimization
Toolset agility improvement via judicious CPT wafer release
Improved fab simulation models
Incorporation of improved models into fab scheduling
• Model development
– Flow line theories
– Improved Exit Recursion models
– Analytic methods for CPT capacity optimization
©2014 –James R. Morrison – ISMI Keynote II – August 17, 2014 – 36
Presentation Overview
• Motivation
• System description (CPT)
• Models for CPTs
• Some recent flow line theory
• Application opportunities
• Where next?
• Concluding remarks
©2014 –James R. Morrison – ISMI Keynote II – August 17, 2014 – 37
Concluding Remarks
• How to understand clustered photolithography tools?
• Models for CPTs
– Linear/Affine
– Flow line based
• Some recent flow line theory
• Application opportunities
Can these models be used to
help improve real fab
performance?
©2014 –James R. Morrison – ISMI Keynote II – August 17, 2014 – 38
Models for the Throughput of Clustered
Photolithography Tools with Applications
James R. Morrison
Email: james.morrison@kaist.edu
Homepage: http://xS3D.kaist.edu
©2014 –James R. Morrison – ISMI Keynote II – August 17, 2014 – 39
References
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
HIS iSuppli April 2011
Elpida Memory, Inc., available at http://www.eplida.com,
Leachman, Robert C., Jeenyoung Kang, and Vincent Lin. "SLIM: Short cycle time and low inventory in manufacturing at samsung
electronics." Interfaces32.1 (2002): 61-77
http://www.forbes.com/forbes/2003/0811/076.html
Roger H. French and V. Hoang, “Immersion Lithography: Photomask and Wafer-Level Materials,” Tran. Annual Review of Materials Research, Vol.
39, 93-126
Hyun Joong Yoon and Doo Yong Lee, “Deadlock-free scheduling of photolithography equipment in semiconductor fabrication,” IEEE Trans. Semi.
Mfg., vol. 17, no. 1, pp. 42-54, 2004
Avi-Itzhak, B. "A sequence of service stations with arbitrary input and regular service times." Management Science 11.5 (1965): 565-571
Friedman, Henry D. "Reduction methods for tandem queuing systems." Operations Research 13.1 (1965): 121-131
Park, Kyungsu, and James R. Morrison. "Performance evaluation of deterministic flow lines: Redundant modules and application to semiconductor
manufacturing equipment." Automation Science and Engineering (CASE), 2010 IEEE Conference on. IEEE, 2010
Morrison, James R. "Deterministic flow lines with applications." Automation Science and Engineering, IEEE Transactions on 7.2 (2010): 228-239
Morrison, James R. "Multiclass flow line models of semiconductor manufacturing equipment for fab-level simulation." Automation Science and
Engineering, IEEE Transactions on 8.1 (2011): 81-94
Kim, Woo-sung, and James R. Morrison, “On the steady state behavior of deterministic flow lines with random arrivals.” Accepted June 14, 2014
for IEEE Transactions on Automation Science and Engineering (IEEE)
Kim, Woo-sung and James R. Morrison, “The throughput rate of serial production lines with regular process times and random setups: Markovian
models and applications to semiconductor manufacturing,” Computers & Operations Research (Elsevier), Online at
http://dx.doi.org/10.1016/j.cor.2014.03.022, April 4, 2014.
Park, Kyungsu and James R. Morrison, “Controlled wafer release in clustered photolithography tools: Flexible flow line job release scheduling and
an LMOLP heuristic,” IEEE Transactions on Automation Science and Engineering (IEEE), Online at http://dx.doi.org/10.1109/TASE.2014.2311997,
April 7, 2014.
Longest waiting pair: [7] Geismar, H.N.; Sriskandarajah, C.; Ramanan, N., "Increasing throughput for robotic cells with parallel Machines and multiple
robots," IEEE Trans. Auto. Sci. and Eng., vol.1, no.1, pp.84,89, Jul 2004
©2014 –James R. Morrison – ISMI Keynote II – August 17, 2014 – 40