Department of Electrical & Electronic Engineering
ORT Braude College
Advanced Laboratory for Characterization of Semiconductor Devices - 31820
MOSFET
(metal-oxide-semiconductor
field effect transistor)
March 22, 2016
Dr. Radu Florescu
Dr. Vladislav Shteeman
Department of Electrical and Electronic Engineering
ORT Braude College of Engineering
Advanced Laboratory for Characterization of Devices – 31820
The goal.
The goal of the laboratory is to investigate the operation of the real long-channel nMOSFET
device. You will measure and estimate the following characteristics of the transistor:
1. Output characteristics: I DS VDS ,VGS 
1.1. Channel conductance g d in the linear region.
1.2. Threshold voltage VT .
1.3. Effective carrier mobility  eff (as a function of VGS  VT ).
1.4. Channel-length modulation parameter (  ) in the saturation region.
1.5. Effective channel length Leff (as a function of VDS ).
2. Transfer characteristics: I DS VGS  and transconductance g m VGS  in the linear region.
2.1. Threshold voltage VT .
2.2. Effective carrier field effect mobility  eff .
3. Optoelectronic characteristics (optional):
3.1. Output characteristics family I DS VDS ,VGS 
3.2. Threshold voltage VT (from the transconductance g m VGS  ) for 3 different lightening
conditions: darkness, moderate lightening and strong lightening.
Dr. Radu Florescu
Dr. Vladislav Shteeman
2
Department of Electrical and Electronic Engineering
ORT Braude College of Engineering
Advanced Laboratory for Characterization of Devices – 31820
Short theoretical background.
MOSFET [1](metal-oxide-semiconductor field-effect transistor) is a three-terminal device, which enables
to use one electrical signal to control (amplify) another signal. This device belongs to the class of field-effect
transistors. Depending of the conductivity type (electrons or holes) and corresponding conductive channel,
there are 2 kinds of MOSFETs: nMOSFET and pMOSFET.
Figure 1. Sketch of MOSFET transistor (after [1]).
nMOSFET transistor consists of two regions (Figure 1): the source and the drain of n-type conductivity
silicon, embedded in a body of the p-type conductivity Si. The space between the source and the drain is
covered by a thin layer of silicon dioxide (SiO2, silica) formed by heating the silicon in an oxidizing
atmosphere. A third part of the device, the gate, is a thin layer of polysilicon (playing a role of metal),
deposited on the silicon dioxide.
The source of nMOSFET is generally used as the voltage reference and is grounded (Figure 2). When no
voltage is applied to the gate, the source-to-drain electrodes correspond to two p-n junctions connected
back to back. The only current that can flow from source to drain is a small leakage current. When a high
positive bias is applied to the gate, a large number of electrons will be attracted to the semiconductor
Dr. Radu Florescu
Dr. Vladislav Shteeman
3
Department of Electrical and Electronic Engineering
ORT Braude College of Engineering
Advanced Laboratory for Characterization of Devices – 31820
surface and form a conductive layer just underneath the oxide. The n+ source and n+ drain are now
connected by a conducting surface n layer (or channel) through which a large current can flow. The
conductance of this channel can be modulated by varying the gate voltages; the conductance also can be
changed by the substrate bias.
Figure 2. nMOSFET transistor sketch (after [1]).
MOSFET was invented in 1959 by D. Kahng and M. Atalla at Bell Labs (USA). Currently, MOSFET is the most
important device for very-large-scale integrated circuits.
There are 3 main reasons why the MOSFET has surpassed the bipolar transistor and become the dominant
device for very-large-scale integrated circuits are:
1. MOSFET can be easily scaled down to smaller dimensions;
2. MOSFET consumes much less power than its bipolar counterpart;
3. MOSFET has relatively simple processing steps. This results in a high manufacturing yield (i.e. high
ratio of good devices to the total number of manufactured transistors).
Dr. Radu Florescu
Dr. Vladislav Shteeman
4
Department of Electrical and Electronic Engineering
ORT Braude College of Engineering
Advanced Laboratory for Characterization of Devices – 31820
1. MOSFET operation modes [2].
VGS > VT
VDS = (VGS-VT)
Drain current IDS [μA]
VGS > VT
VDS << (VGS-VT)
VGS > VT
VDS > (VGS-VT)
Drain-to-source voltage VDS [V]
Figure 3. Family of nMOSFET output I-V characteristics (after [25]).
[1]
Cutoff mode (sub-threshold or weak-inversion mode).
Figure 4. Cutoff mode of nMOSFET transistor (after [2]).
When VGS  VT ,(Figure 4) transistor is turned off, and there is no conduction between the drain and the
source. In the reality, the Boltzmann distribution of electron energies allows some of the more energetic
electrons at the source to enter the channel and flow to the drain, resulting in a sub-threshold current that
is an exponential function of gate–source voltage. While the current between drain and source should
ideally be zero when the transistor is being used as a turned-off switch, there is a weak-inversion current,
sometimes called sub-threshold leakage.
Dr. Radu Florescu
Dr. Vladislav Shteeman
5
Department of Electrical and Electronic Engineering
ORT Braude College of Engineering
Advanced Laboratory for Characterization of Devices – 31820
[2]
Linear mode (triode or ohmic mode).
Figure 5. Linear mode of nMOSFET transistor (after [2]).
When VGS  VT and VDS  VGS  VT  (Figure 5), transistor is turned on, and the channel is created. The
MOSFET operates like a resistor controlled by the gate voltage relative to both the source and drain
voltages (Figure 6):
Drain - Source current IDS [A]
IDS - VDS characteristics for nMOSFET
in the linear region: VDS < 0.5 [V].
4.0E-05
3.5E-05
Vgs = 3 [V]
3.0E-05
Vgs = 4 [V]
2.5E-05
Vgs = 5 [V]
2.0E-05
Vgs = 6 [V]
1.5E-05
Vgs = 7 [V]
1.0E-05
Vgs = 8 [V]
5.0E-06
0.0E+00
0.0
0.2
0.4
Drain - Source voltage VDS [V]
Figure 6. Example of I-V characteristics of nMOSFET in the linear region (VGS < 0.5 [V]).
In the linear region, for which holds VDS  VGS  VT  ), the drain-source current I DS can be written as:
I DS
2


W
VDS

 eff C 'OX  VGS  VT VDS 
L
2 

linear ,
VDS  VGS  VT 
(1)
where  eff is a surface mobility (holes for pMOS and electrons for nMOS), W & L are width and length of
the channel and C'OX is an oxide layer capacitance per unit area (see List of symbols in Appendix 1).
Dr. Radu Florescu
Dr. Vladislav Shteeman
6
Department of Electrical and Electronic Engineering
ORT Braude College of Engineering
Advanced Laboratory for Characterization of Devices – 31820
Furthermore, if VDS
2
VDS
 VGS  VT  , the
in the equation above can be neglected, thus I DS becomes a
2
linear function of VDS :
I DS 
W
eff C 'OX VGS  VT VDS
L
linear ,
VDS  VGS  VT 
(2)
[3] Saturation mode (active mode).
Figure 7. Saturation mode of nMOSFET transistor (after [2]).
When VGS  VT and VDS  VGS  VT  (Figure 7), transistor enters into the saturation mode.
Drain - Source current IDS [A]
IDS - VDS characteristics for nMOSFET
in the saturation region: VDS ≥ (VGS - VT).
1.6E-04
1.4E-04
1.2E-04
1.0E-04
8.0E-05
6.0E-05
4.0E-05
2.0E-05
0.0E+00
Vgs = 3 [V]
Vgs = 4 [V]
Vgs = 5 [V]
Vgs = 6 [V]
Vgs = 7 [V]
Vgs = 8 [V]
0
2
4
6
8
Drain - Source voltage VDS [V]
Figure 8. Example of I-V characteristics of nMOSFET in the saturation region: VGS ≥ (VDS - VT).
Dr. Radu Florescu
Dr. Vladislav Shteeman
7
Department of Electrical and Electronic Engineering
ORT Braude College of Engineering
Advanced Laboratory for Characterization of Devices – 31820
In this case (Figure 8)
I DS  
saturation,
W
eff C 'OX (VGS  VT ) 2
2L
VDS  (VGS  VT )  (+ for nMOS, - for pMOS)
(3)
Note, that because of so-called “body effect” (see explanation below and Appendix 1), the threshold voltage
VT in our measurements is large than expected for the grounded device ( VT  1.81V ) and I DS (VDS ,VGS )
characteristics family is “lower” than that expected for grounded transistor.
Drain - Source current IDS [A]
IDS,sat - VDS,sat characteristics of nMOSFET
1.6E-04
1.4E-04
1.2E-04
Vgs = 3 [V]
1.0E-04
Vgs = 4 [V]
8.0E-05
Vgs = 5 [V]
6.0E-05
Vgs = 6 [V]
4.0E-05
Vgs = 7 [V]
2.0E-05
Vgs = 8 [V]
0.0E+00
I sat - V sat
0
2
4
6
8
Drain - Source voltage VDS [V]
Figure 9. Body effect influence on the IDS,sat - VDS,sat characteristics of nMOSFET transistor.
Dr. Radu Florescu
Dr. Vladislav Shteeman
8
Department of Electrical and Electronic Engineering
ORT Braude College of Engineering
Advanced Laboratory for Characterization of Devices – 31820
2. Body effect [5] .
(see also List of definitions in Appendix 1)
Normally, the MOSFET body is connected to the lowest voltage potential of the circuit (usually the source)
(Figure 10).
Figure 10. nMOSFET with grounded body (no body effect) (after [5]).
Nevertheless, if the body is left unconnected, it affects the threshold voltage VT and I DS (VDS ,VGS )
characteristics of the device, biased in linear and saturation regimes.
Specifically, channel voltage Vchannel  y  depends on position y along the channel (Figure 11).
Figure 11. Channel voltage Vchannel  y  dependence on position y along the channel (after [5]).
In this case, threshold voltage VT  y  also becomes y-dependent (namely, it increases along y).
Dr. Radu Florescu
Dr. Vladislav Shteeman
9
Department of Electrical and Electronic Engineering
ORT Braude College of Engineering
Advanced Laboratory for Characterization of Devices – 31820
Figure 12. In case of Body effect, threshold voltage increases along the channel (after [5]).
Dependence of VT  y  further debiases transistor: I DS becomes lower than ideal and VDS ,sat becomes
IDS (arbitrary units)
lower than ideal (Figure 13).
Figure 13. Body effect influence on the family of characteristics I DS (VDS ,VGS ) (after [5]).
Three noticeable features:
1. for all values of VGS and VDS , body effect reduces I DS
2. for given VGS , body effect reduces V DS , sat
3. body effect goes away as transistor is turned off
Dr. Radu Florescu
Dr. Vladislav Shteeman
10
Department of Electrical and Electronic Engineering
ORT Braude College of Engineering
Advanced Laboratory for Characterization of Devices – 31820
3. Channel length modulation effect [10] .
(see also List of definitions in Appendix 1)
Above the “pinch-off” voltage (i.e. for VDS  VDS , sat (where VDS , sat  VGS  VT )) the physical channel length
L is reduced by a value L (Figure 14).
Figure 14. Channel length L and effective channel length Leff in saturation region for VDS  VDS , sat (after [10]).
In this case, the expression for I DS (for VDS  VDS , sat ) (without body effect) becomes [10]:
I DS  
W
W
eff C 'OX (VGS  VT )2 1  VDS   
eff C 'OX (VGS  VT )2 (+ for nMOS, - for pMOS)
2L
2 Leff
(4)
Accounting for body effect (specifically, for VDS , sat  VGS  VT ) results in the following correction to Eq. (4):
I DS  
W
W
2
2
eff C 'OX VDS
eff C 'OX VDS
, sat 1  VDS   
, sat (+ for nMOS, - for pMOS)
2L
2 Leff
(5)
(This is the relevant expression for I DS in our case)
In Eqs. (4)-(5), effective channel length Leff relays to physical length L and channel length modulation
parameter,
Leff 
 , as follows:
L
L
1  VDS
Dr. Radu Florescu
(6)
Dr. Vladislav Shteeman
11
Department of Electrical and Electronic Engineering
ORT Braude College of Engineering
Advanced Laboratory for Characterization of Devices – 31820
The fact, that Leff  L , results in a small increase of I DS with increasing of VDS in saturation region (Figure
15). Channel length modulation parameter ,  , corresponds to the point of intersection of the tangent to
the I DS VDS  curve in saturation region with the VDS axis.
Figure 15. Graphical illustration to definition of channel length modulation parameter
 .
 can be calculated (separately for each gate VGS ) from the I  V characteristics of MOSFET in saturation
region (Figure 16). Namely, for each gate VGS , one should find (using trendline) the linear equation of the
I DS VDS  curve in saturation region. If a free term and a slope of the linear equation are known,

slope
.
free term
Figure 16. Illustration to calculation of
Dr. Radu Florescu
 from I  V characteristics of nMOSFET in saturation region.
Dr. Vladislav Shteeman
12
Department of Electrical and Electronic Engineering
ORT Braude College of Engineering
Advanced Laboratory for Characterization of Devices – 31820
If
 is known - Leff can be found (separately for each gate VGS ) from Eq. (6).
4. Effective mobility [12] .
(see also List of definitions in Appendix 1)
Figure 17. nMOSFET structure and coordinate orientation, assumed in the quantitative analysis of
effective mobility (after [12]).
In the semiconductor bulk, i.e. at a point far removed from the semiconductor surface, the carrier mobilities
(namely, bulk mobilities  hole and  e ) are determined by the amount of lattice scattering and ionized
impurity scattering, taking place inside the material. For a given temperature and doping, those bulk
mobilities,  hole and  e , are well-defined.
Carrier motion in MOSFET, however, takes place in an inversion layer at the interface between Si and
SiO2 . Due to additional lattice defects, associated with the Si  SiO2 interface, and due to the quantum
confinement of the carriers in the triangular quantum well of MOS structure, carriers mobility in the
channel differs significantly from that of bulk. Note that the channel is located under the gate, where the
gate-induced electric field acts so as to accelerate the carriers towards the surface. The inversion layer
carriers therefore experience motion impending collisions with the Si interface in addition to surface and
impurity scattering (see Figure 18). This lowers the mobility of the carriers, with the carriers constrained
nearest the Si surface experiencing the greatest reduction in mobility. The resulting average mobility of
the inversion layer is called the effective mobility  eff . Obviously, eff  hole(e ) always holds.
Dr. Radu Florescu
Dr. Vladislav Shteeman
13
Department of Electrical and Electronic Engineering
ORT Braude College of Engineering
Advanced Laboratory for Characterization of Devices – 31820
Figure 18. Visualization of surface scattering at the Si  SiO2 interface (after [12]).
Relative to the dependence of  eff on the gate voltage VGS , increased inversion biasing increases the xdirection electric field acting on the carriers closer to the Si  SiO2 interface. Surface scattering is
enhanced and  eff therefore decreases. Usually (at least for long-channel devices) the dependence of  eff
vs VGS can be described by the following empirical expression:
 eff 
0
(7)
1   VGS  VT 
where  0 (called surface carrier’ mobility) and  (called mobility degradation factor) are constant.
Figure 19. Experimental curve of  eff vs VGS  VT for nMOSFET N1 (see Appendix 2 for details).
Dr. Radu Florescu
Dr. Vladislav Shteeman
14
Department of Electrical and Electronic Engineering
ORT Braude College of Engineering
Advanced Laboratory for Characterization of Devices – 31820
5. Optoelectronic effects in MOSFETs.
Parasitic currents can be generated in transistors by external lighting. The origin of this current is the
carriers, excited by light at the p-n junctions, which are the essential part of the MOSFET technology. Those
currents may affect performances of MOSFET and should be avoided. The best way to do this – is to black
out the device.
In our chip, the transistor most greatly affected by light induced currents is N4. This occurs when pin 11 is
the source and pin 6 is the grain (see Appendix 2 for the chip details). A current of ~ 200 A may be
produced. Light induced currents of ~ 20 A may affect also the transistors P2 and P3. The only effective
cure is blackout.
See Appendix 5 for the expected results of the light influence on the n-MOSFET performances.
Dr. Radu Florescu
Dr. Vladislav Shteeman
15
Department of Electrical and Electronic Engineering
ORT Braude College of Engineering
Advanced Laboratory for Characterization of Devices – 31820
Experimental set-up.
The experimental setup includes:
[1] Test fixture Probe station with dual in-line package (18 pins), connected (by the triax cables No
9,10,11,12) to the Keithley matrix.
Figure 20.Test fixture Probe station with dual in-line package (18 pins)
[2] External voltage supply device. This supply must be connected to the pins 8 (external ground, V=0)
and 16 (Vcc = +10 V) of the chip in order to “tell” him the range of the voltage variation. (See also
“Information on usage” in the Additional details of Appendix 2).
Figure 21. External voltage supply device.
See Appendix 6 for pin connections scheme for the N1 transistor.
Dr. Radu Florescu
Dr. Vladislav Shteeman
16
Department of Electrical and Electronic Engineering
ORT Braude College of Engineering
Advanced Laboratory for Characterization of Devices – 31820
Assignments and analysis.
Note: after executing the room temperature measurements (Parts I and II below) and before
processing the acquired data, save this
Excel template on your computer (double click on the
data processing
nMOSFET (empty) (new).xlsx
Excel icon  File  Save as … ). Then close the Excel template and open the Excel file, saved recently.
Copy the results of the measurements (located in the measurements folder of Keithley in the
subdirectory “tests/data”), namely, data from the files “vds-id#1@1.xls” and “vgs-id#1@1.xls” to the
Excel template, saved on your computer.
Part I. Output characteristics I DS VDS ,VGS  (at the room temperature)
Measurements:
Acquire the family of the output characteristics I DS VDS ,VGS  for the nMOS transistor N1 for 15
different values of VGS , namely:
 VGS voltage must vary in the range from 3 to 10 V (step 0.5 V);
 for each of the VGS voltages, V DS voltage must vary from 0 to 9 V (step 0.05 V) (see Appendix 3
for the ranges of VDS and VGS values).
linear domain
VDS < 0.5 [V]
Dr. Radu Florescu
Dr. Vladislav Shteeman
17
Department of Electrical and Electronic Engineering
ORT Braude College of Engineering
Advanced Laboratory for Characterization of Devices – 31820
Data processing and analysis:
After finishing all the measurements, transfer the acquired data (file “vds-id#1@1.xls”, located in the
measurements folder of Keithley in the subdirectory “tests/data”) to the Excel template.
[1] Compute
C 'OX 
C'OX
 0 ox
tox
 F
 cm 2
gate
or
oxide
capacitance
per
unit
area
according
to
the
formula
F
(see C'OX definition in the List of symbols in Appendix 1).
m2 
[2] Plot the family of output characteristics I DS VDS ,VGS  .
[3] Estimate the conductance g d . Using the linear fit (linear trend-line) for the linear parts of the graphs
I DS VDS ,VGS  ( 0  VDS  0.5 ) and find the conductance g d 
I DS ,lin
for each of the VGS values.
VDS
Note that according to the model, g d is a linear function of the VGS : g d 
W
eff C 'OX VGS  VT 
L
[4] Plot g d as a function of VGS . Is the graph looks linear as expected from the long channel model?
(explain).
[5] Find the threshold voltage VT . To do this, from the same linear fit g d vs VGS , extract the value of VT ,
being an intersection of the fitting line with the VGS axis.
[6] Return to the graph of family of output characteristics I DS VDS ,VGS  . From the graphs I DS VDS  ,
measure the I DS , sat value corresponding to the VDS , sat  VGS  VT for the different VGS values and fill
in the calc table. Add this graph to the plot.
[7] Evaluate the effective mobility  eff . To do this:
 Fill in the calc table with the VGS  VT values.
 Evaluate the effective mobility  eff for each of the g d and VGS  VT  pairs using the formula:
W
eff C 'OX VGS  VT  . Fill in the column  eff (experimental).
L
 Plot graph g d vs VGS  VT  . Add linear trendline to the graph and find its slope. This slope is
gd 
nothing but
W
eff C 'OX .
L
 In the calc table, fill in the cell corresponding to a single, average value of  eff :
eff 
trendline ' slope
W
C 'OX
L
[8] Determine the 0 (surface carriers’ mobility in Si at 300 K) and the degradation factor  . To do this:
Dr. Radu Florescu
Dr. Vladislav Shteeman
18
Department of Electrical and Electronic Engineering
ORT Braude College of Engineering
Advanced Laboratory for Characterization of Devices – 31820

In the calc table, fill in the column 1 
 Plot graph VGS  VT  vs 1 
.
eff
. Add linear trendline to the graph and find its slope and free
eff
term.
 According to the model, eff 
words, 1 
eff
0
1   VGS  VT 
(see List of symbols in Appendix 1). In other
should be a linear function of the VGS  Vth parameter: VGS  VT 
From the slope and free term of the trendline of 1 
eff
0 1 1
 .
 eff 
vs. VGS  Vth  , find the values of 0 and
 . Explain why the surface mobility is different from the bulk mobility.
[9] Estimate the effective channel length Leff . From the saturation regions of the family of
I DS  f VDS ,VGS  graphs, one can calculate (using Eq. 3) the effective channel’ length Leff . Make a
plot Leff VGS  .
[10] Determine channel length modulation parameter,
 , for different gates VGS . To do this, make a plot
I DS  VDS in the saturation region (say, between the points VDS  5 V and VDS  10 V ) for each of
the VGS values. Then add a linear trendline (and its equation) to each of the curves.
intersection between the trendline and the x-axis. Put
 is a point of
 values in the calc table. Make a plot  VGS  .
Final report must include the following graphs (appearing in the Excel template) with explanations:
[1] Family of I DS VDS  for different VGS
[2] g d vs VGS
[3]
eff vs VGS  VT 
[4] VGS  VT  vs 1
eff
[5] Leff vs VGS
[6]  vs VGS
Dr. Radu Florescu
Dr. Vladislav Shteeman
19
Department of Electrical and Electronic Engineering
ORT Braude College of Engineering
Advanced Laboratory for Characterization of Devices – 31820
Part II. Transfer characteristics I DS VGS  (at the room temperature)
Measurements:
Acquire the transfer characteristics I DS VGS  and transconductance
g m VGS  (for constant
VDS  0.1 V  ) for the nMOS transistor N1 (see Appendix 3 for the measurement settings).
Data processing and analysis:
Formula
development.doc
[1]
Explain why the transconductance, g m , has maximum in the linear region.
[2]
Consider Eq. 1, giving I DS as a function of VDS and VGS in the linear region. Find the
differential
I DS
(i.e. find transconductance g m (see List of symbols in Appendix 1)) and show
VGS
that :
VGS ,i  VGS ,max 
I DS , max  
I DS ,max
g m,max
W
eff Cox VGS , max  VT  VDS / 2 VDS
L
where I DS , max and VGS , max are the current and the voltage corresponding to the g m ,max , and
VGS , i gate-source voltage (expected) intersection with the x-axis (“Gate voltage”) on the graph
I DS  f VGS  (i.e. VGS expected value for I DS  0 )
Dr. Radu Florescu
Dr. Vladislav Shteeman
20
Department of Electrical and Electronic Engineering
ORT Braude College of Engineering
Advanced Laboratory for Characterization of Devices – 31820
VGS ,i
[3]
Show that the extrapolated (measured) value of the intersection voltage VGS , i equals to the
VT  VDS / 2 .
[4]
Estimate the VT from the VGS , i .
After finishing all the measurements, transfer the acquired data (file “vgs-id#1@1.xls”, located in the
measurements folder of Keithley in the subdirectory “tests/data”) to the Excel template.
[5]
Fill the calc table with the g m and VGS  VT  values.
[6]
Calculate  FE   eff
 FE  eff 
[7]
in the calc table from the g m value using the following definition:
Lgm
. Plot a graph  eff vs VGS  VT  .
WC 'OX VDS
Fill the calc table with the 1 eff values. Plot a graph VGS  VT  vs 1 eff (only the part,
corresponding to the monotonic decreasing section of  eff vs VGS  VT  , i.e. to the range of
voltages 1  VGS  VT   6 ).
[8]
Assume that  FE  eff 
0
1   VGS  VT 
. Use the linear regression fit to the graph above to
find the parameters 0 and the degradation factor  .
Dr. Radu Florescu
Dr. Vladislav Shteeman
21
Department of Electrical and Electronic Engineering
ORT Braude College of Engineering
Advanced Laboratory for Characterization of Devices – 31820
[9]
Extract the surface mobility of carriers, 0 , and the degradation factor,  , for high VGS values.
[10] Compare to values obtained for 0 in the Part I and explain the difference.
Final report must include the following graph (appearing in the Excel template) with explanations:
[1] I DS VGS  and gm VGS  (a single plot)
[2]
eff vs VGS  VT 
[3] VGS  VT  vs 1
eff
Part III. Output characteristics I DS VDS ,VGS  (under heating conditions)
Acquire the families of the output characteristics I DS T   f VDS T ,VGS T  of the nMOS transistor



N1 in the temperature range from 25 C to 75 C (with the steps of approximately 10 C ). Similarly
to the assignment of the Part I, for each of the temperatures acquire the family of I DS  f VDS , VGS 
characteristics for 15 different values of VGS , namely:
 VGS voltage should vary in range from 3 to 10 V (step 0.5 V);
 for each of the VGS voltages, VDS voltage should vary in range from 0 to 10 V (step 0.05 V);
Important: execute the 1st measurement (under room temperature) using the green button
, and all the
rest of the measurements (under heating conditions, for 4-6 different temperatures) using the yellow-greed
button
(“append”). DO NOT use the green button
for the measurements under heating conditions:
it will override all your previous measurements.) After each measurement save the data in the Keithley
program.
After finishing the measurements, you should process the data using a Matlab program. To do this:
Dr. Radu Florescu
Dr. Vladislav Shteeman
22
Department of Electrical and Electronic Engineering
ORT Braude College of Engineering
Advanced Laboratory for Characterization of Devices – 31820
1. Double-click on the zip-file
icon
2. In the dialog window press “open”.
3. In the newly opened window, the folder named “MOSFET heating processing” will appear.
4. Drag this folder to the Desktop of your computer.
5. In the Keithley measurements folder (subfolder tests/data) find the files vds-id#1@1.xls (
I DS VDS , VGS  data) & vgs-id#1@1.xls ( I DS VGS  data)
Dr. Radu Florescu
Dr. Vladislav Shteeman
23
Department of Electrical and Electronic Engineering
ORT Braude College of Engineering
Advanced Laboratory for Characterization of Devices – 31820
6. Copy the files vds-id#1@1.xls & vgs-id#1@1.xls to the folder “MOSFET heating processing”:
7. Double-click on the file processed_data_MOSFET_sf.m in the directory
“MOSFET heating processing”. This will start Matlab. Wait for 1-2 minutes to
allow Matlab start.
8. Go to the Matlab Editor window and run the file rocessed_data_MOSFET_sf.m
(press F5 or Debug Run on the Editor menu bar).
Dr. Radu Florescu
Dr. Vladislav Shteeman
24
Department of Electrical and Electronic Engineering
ORT Braude College of Engineering
Advanced Laboratory for Characterization of Devices – 31820
9. The program will ask you to input the temperatures, at which you measured the transistor. Input
the temperatures in the square parentheses with the spaces between the different values, e.g. [25
35 45 55 65 75]. Press Enter to continue.
10. Wait for 1-2 minutes until the program will finish the processing of the measured data.
11. The results of the computations (Excel file processed_data.xls, Matlab files and figures) are located
in the subfolder Results.
Dr. Radu Florescu
Dr. Vladislav Shteeman
25
Department of Electrical and Electronic Engineering
ORT Braude College of Engineering
Advanced Laboratory for Characterization of Devices – 31820
Final report must include the following graphs with explanations:
[1] The graph of the saturation current as a function of the temperature,
I DS ,sat (T ) for each of the 15 different VGS values. (Single figure, 15
different curves, each curve should contain 6 points (according to the
number of different temperature values)).
[2] The graph of the conductance as a function of the temperature g d T 
for each of the values VGS . (Single figure, 15 different curves, each curve
should contain 6 points, corresponding to the 6 different temperatures).
[3] The graph of the threshold voltage as a function of the temperature, VT T  .
[4] The graph of the max transconductance value as a function of the
(max)
temperature, g m T  .
[5] The graph of the drain current as a function of the pinch-off voltage
I DS VDS  VGS  VT  (where pinch-off voltage is a VDS voltage, for which
Dr. Radu Florescu
Dr. Vladislav Shteeman
26
Department of Electrical and Electronic Engineering
ORT Braude College of Engineering
Advanced Laboratory for Characterization of Devices – 31820
holds VDS  VGS  VT  ) for all the temperature values. (Single figure, 6 different curves for 6 different
temperatures, each curve should contain 15 points (according to the number of the different VGS
values)).
Dr. Radu Florescu
Dr. Vladislav Shteeman
27
Department of Electrical and Electronic Engineering
ORT Braude College of Engineering
Advanced Laboratory for Characterization of Devices – 31820
Acknowledgement
Electrical Engineering Department of Braude College would thank to Mr. David Furman for his extensive
help and support in preparation of this laboratory work.
Some parts of this guide were adapted from the MOSFET guide of the Advanced Semiconductor Devices Lab
(83-435) of School of Engineering of Bar-Ilan University. We would like to thank Dr. Abraham Chelly for the
granted manual.
Dr. Radu Florescu
Dr. Vladislav Shteeman
28
Department of Electrical and Electronic Engineering
ORT Braude College of Engineering
Advanced Laboratory for Characterization of Devices – 31820
Appendix 1 : List of symbols and definitions
List of symbols

 cm 2 
,
V

sec


hole(e ) - bulk mobility of carriers (holes in pMOS and electrons in nMOS) (for Si, hole  471 
 cm 2 
 )
V  sec 
e  1350 










 eff - effective (acquired from the experimental measurements) mobility of carriers in the channel;
eff  hole(e ) always holds.  eff is influenced both by the fact, that the channel located at the interface
between Si and SiO2 (with associated lattice defects) and by the quantum confinement of the carriers
in the triangular quantum well of MOS structure.
W, L – channel width and length. For our transistors: L  100 m , W varies from transistor to
transistor (see Appendix 2 for details)
Leff - effective channel length modulated by VDS.
 
λ - channel length modulation parameter 0    1
t ox - oxide layer’ thickness. For our transistors tox  100 nm (see Appendix 2 for details)
 ox - oxide layer’ (relative) dielectric constant.  ox  3.9 (see Appendix 2 for details)
 0 - permittivity of vacuum.  0  8.85  10-14 F cm  8.85  10-12 F m
  F
F
Cox - gate oxide capacitance (per unit area): Cox  0 ox  2 or
.
tox  cm
m2 
VGS ,VDS - gate-source and drain-source voltage
VGS , i gate-source voltage (expected) intersection with the “Gate voltage” axe VGS  (x-axe) on
 
 
the graph I DS  f VGS  (i.e. expected VGS value for I DS  0 )

VT - threshold voltage (the gate-source voltage at which a transistor starts to conduct)
 VT  y  - position-inside-channel dependent threshold voltage (as the result of Body effect)
 VT 0  VT 0 - threshold voltage at the beginning of the channel (for position-inside-channel dependent
threshold voltage VT  y  )



VDS , sat saturated drain-source voltage VDS , sat  VGS  VT
Vchannel  y  MOSFET channel voltage (position-dependent because of Body effect)
g m - transconductance of the channel (depends on VGS ):
W
 L  eff  Cox  VDS (linear region )

I
.
g m  DS

VGS V  const 
DS
W
  eff  Cox  VGS  VT  ( saturation)
L
Dr. Radu Florescu
Dr. Vladislav Shteeman
29
Department of Electrical and Electronic Engineering
ORT Braude College of Engineering
Advanced Laboratory for Characterization of Devices – 31820
Lg m
0
WC oxVDS

 FE  eff field effect mobility:  FE   eff 

g d - channel conductance in the linear region: gd 

 eff - effective mobility of carriers in the channel (holes in pMOS and electrons in nMOS). According to
I DS ,lin
W
  eff Cox VGS  VT   0
VDS
L
the empirical model, for sufficiently small VDS
eff 
values (namely,
VDS
2
 VGS  VT  ) holds:
Lgd
0

. Here,  and 0 are the mobility degradation factor (see below)
WQhole( e ) 1   VGS  VT 
and the surface carrier’ mobility in Si at 300 K (see also below). In the short channel device,  eff is a
function of VGS , while in the long channel devices, examined here, it is assumed to be a constant.

Qhole(e ) mobile dominant carrier’ (hole for pMOS or electron for nMOS) channel charge density [C/cm2


or C/m2 ]: Qhole( e )  Cox VGS  VT 
VDS 
g
2 

0 surface mobility of carriers (holes in pMOS and electrons in nMOS) in Si at 300 K (e.g. for holes

0 ~ 160 
)
Volt  sec 
 - mobility degradation factor [Volt-1] (   0 for nMOSFET,   0 for p-MOSFET)1. Theory predicts,
 cm2
that  ~


1
0.42  tox [nm ]
VGS ,i - gate-source voltage (expected) intersection with the x-axis (“Gate voltage”) on the graph of
I DS  f VGS  (transfer characteristics)
List of definitions
Threshold voltage VT - the gate-source voltage at which a transistor starts to conduct.
Bulk (body)- back contact of a MOSFET also referred to as the substrate contact.
Body effect – normally, the MOSFET body is connected to the lowest voltage potential of the circuit (usually
the source). However if is left unconnected, it affects the threshold voltage VT and I DS (VDS ,VGS )
characteristics of the device. Namely,
 VT increases with increasing bulk voltage

for all values of VGS and VDS , body effect reduces I DS
1 See ref. 11 p.455-456 to get a theoretical value.
Dr. Radu Florescu
Dr. Vladislav Shteeman
30
Department of Electrical and Electronic Engineering
ORT Braude College of Engineering
Advanced Laboratory for Characterization of Devices – 31820

for given VGS , body effect reduces V DS , sat




n+ (n-)semiconductor n-type semiconductor with high donor density ( N D  1019 cm 3 ) and with low

donor density ( N D  10 cm
16
3
) correspondingly. Here, N
D
is a donor density.
p+ (p-) semiconductor p-type semiconductor with high acceptor density ( N A  1019 cm 3 ) and with low

acceptor density ( N A  10 cm
16
3
) correspondingly. Here, N
A is
an acceptor density.
Mobility - the ratio of the carrier velocity to the applied electric field.
Inversion - change of carrier type in a semiconductor obtained by applying an external voltage. In a
MOSFET, inversion creates the free carriers, which cause the drain current. Inversion layer - the layer of
free carriers of opposite type at the semiconductor-oxide interface of a MOSFET.
Depletion - removal of free carriers in a semiconductor
Channel length modulation - variation of the channel due to an increase of the depletion region when
increasing the drain voltage. A reduction of the channel yields a higher current.
Transfer characteristic - output current of a device plotted as a function of the input voltage.
Transconductance is a ratio of output current variation to the input voltage. Transconductance variation of
MOSFET defines its gain. It is proportional to hole (electron) mobility (depend on the device type, pMOS or
nMOS), at least for low drain voltages. As MOSFET size is reduced, the fields in the channel increase and the
dopant impurity levels increase. Both changes reduce the carrier mobility, and hence the transconductance.
As channel lengths are reduced without proportional reduction in drain voltage, raising the electric field in
the channel, the result is velocity saturation of the carriers, limiting the current and the transconductance.
Dr. Radu Florescu
Dr. Vladislav Shteeman
31
Department of Electrical and Electronic Engineering
ORT Braude College of Engineering
Advanced Laboratory for Characterization of Devices – 31820
Appendix 2 : Teaching chip № 2 details.
Chip layout
Chip appearance
Photomicrograph of the chip.
Dr. Radu Florescu
Dr. Vladislav Shteeman
32
Department of Electrical and Electronic Engineering
ORT Braude College of Engineering
Advanced Laboratory for Characterization of Devices – 31820
Additional details:
Dr. Radu Florescu
Dr. Vladislav Shteeman
33
Department of Electrical and Electronic Engineering
ORT Braude College of Engineering
Advanced Laboratory for Characterization of Devices – 31820
Appendix 3 : Kite settings for nMOSFET.
Output characteristics: I DS VDS ,VGS 
Connect pins:
ITM module:
Dr. Radu Florescu
Dr. Vladislav Shteeman
34
Department of Electrical and Electronic Engineering
ORT Braude College of Engineering
Advanced Laboratory for Characterization of Devices – 31820
Expected results:
Transfer characteristics: IDS=f(VGS) and Transconductance gm= f(VGS) in the
linear region.
ITM module:
Dr. Radu Florescu
Dr. Vladislav Shteeman
35
Department of Electrical and Electronic Engineering
ORT Braude College of Engineering
Advanced Laboratory for Characterization of Devices – 31820
Formulas for automatic
differentiation
I DS ,lin
VGS
and finding VGS ,i
Expected results:
Dr. Radu Florescu
Dr. Vladislav Shteeman
36
Department of Electrical and Electronic Engineering
ORT Braude College of Engineering
Advanced Laboratory for Characterization of Devices – 31820
Appendix 4 : Kite settings for pMOSFET.
Output characteristics: I DS VDS ,VGS 
Connect pins:
ITM settings
CAUTION: Do not set values exceeding the assigned values!
Dr. Radu Florescu
Dr. Vladislav Shteeman
37
Department of Electrical and Electronic Engineering
ORT Braude College of Engineering
Advanced Laboratory for Characterization of Devices – 31820
Expected results
Transfer characteristics: IDS=f(VGS) and Transconductance gm= f(VGS) in the
linear region.
Dr. Radu Florescu
Dr. Vladislav Shteeman
38
Department of Electrical and Electronic Engineering
ORT Braude College of Engineering
Advanced Laboratory for Characterization of Devices – 31820
CAUTION: Do not set values exceeding the assigned values!
Expected results
Dr. Radu Florescu
Dr. Vladislav Shteeman
39
Department of Electrical and Electronic Engineering
ORT Braude College of Engineering
Advanced Laboratory for Characterization of Devices – 31820
Appendix 5: expected results of the light influence on the
n-MOSFET performances.
Darkness
I DS  40.3003 A
VT  1.80788 V
Moderate lightening
I DS  40.2978  106 A
VT  1.81243 V
Strong lightening
I DS  39.3075 A
VT  2.41915 V
Dr. Radu Florescu
Dr. Vladislav Shteeman
40
Department of Electrical and Electronic Engineering
ORT Braude College of Engineering
Advanced Laboratory for Characterization of Devices – 31820
Appendix 6: Pin connections for N1 transistor.
Note: Our chip has 16 pins, while the socket of the Test fixture – 18 contacts. Thus, 1-8 pins of the chip
correspond to 1-8 contacts of the socket, while 9-16 pins of the chip correspond to 11-18 contacts of the
socket.
Keithley SMU 1
(source)
chip’ pins
Source
socket’
contacts
18
Vcc=+10 V from the
external source
17
16 Gate
15 Drain
14
13
12
11
GND (V=0) of the
external source
Keithley SMU 2
(drain)
Keithley SMU 3
(gate)
Dr. Radu Florescu
Dr. Vladislav Shteeman
41
Department of Electrical and Electronic Engineering
ORT Braude College of Engineering
Advanced Laboratory for Characterization of Devices – 31820
Bibliography and internet links
1. MOSFET at Britannica:
http://www.britannica.com/EBchecked/topic/533976/semiconductor-device/34333/Metaloxide-semiconductor-field-effect-transistors#ref71251
2. MOSFET at wikipedia: http://en.wikipedia.org/wiki/MOSFET
3. B. Van Zeghbroeck, “Principles of semiconductor devices”, Lectures – Colorado University,
2004.
4. A. Chelly, “MOS – field effect transistor”, Lab manual - Advanced Semiconductor Devices Lab
(83-435), School of Engineering of Bar-Ilan University.
5. A. del Alamo. “Integrated microelectronic devices” course (6.720J / 3.43J), lecture 27: “The
”Long” Metal-Oxide-Semiconductor Field-Effect Transistor”, MIT, 2002.
6. B. Streetman, S. Banerjee, “Solid state electronic devices” (6th edition), Prentice Hall, 2005.
7. J. Singh, “Semiconductor devices: basic principles”, Whiley, 2001.
8. MOSFET Simulation using Java Applet:
http://jas2.eng.buffalo.edu/applets/education/mos/mosfet/mosfet.html
9. Gate Dielectric Capacitance-Voltage.
www.keithley.com/data?asset=3580
Characterization
Using
the
Model
4200:
10. Alan
Doolittle.
Lectures
on
course
Semiconductor
devices:
http://users.ece.gatech.edu/~alan/ECE3040/Lectures/Lecture25-MOSTransQuantitativeIdVd-Vg.pdf
11. D.K. Schroder, "Semiconductor material and device characterization", Chapter 7; Wiley,
1998. Library code: 621.38152 SCHR (advanced level).
12. R. Pierret. Semiconductor Device Fundamentals, Addison-Wesley, 1996
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Dr. Vladislav Shteeman
42
Department of Electrical and Electronic Engineering
ORT Braude College of Engineering
Advanced Laboratory for Characterization of Devices – 31820
Preparation Questions
1. Explain (in short) what is MOSFET transistor and its principles of work.
2. What is the family of the output characteristics I DS  f VDS ,VGS  ?
3. How can you measure
 channel conductance g d in the linear region.
 threshold voltage VT .
 effective mobility  eff as a function of VGS  VT .
on the basis of the family of the output characteristics I DS  f VDS ,VGS  ?
4. What is the transfer characteristics I DS  f VGS  and transconductance g m  f VGS  ?
5. How can you measure
 threshold voltage VT
 effective mobility  eff .
on the basis of I DS  f VGS  and g m  f VGS  ?
6. Explain (in short), what is the reason for light influence on MOSFET performances.
Dr. Radu Florescu
Dr. Vladislav Shteeman
43