Daniel Bernard
ECE 1315 Digital System Design
Lab #6: MUX and Decoders as Combinational Gates
10/19/2010
Lab #6: MUX and Decoders as Combinational Gates
The scope of the investigation was to create an electrical logic circuit that is able to
implement three functions simultaneously. The first function must be implemented on an 8:1
Multiplexer (MUX) chip, and the two remaining functions must be implemented on a 3:8
Decoder chip. We are also allowed to choose a single additional chip of our choosing. Since they
must all function simultaneously, the inputs and outputs should be connected in some way to
optimize the number of circuits. The following chips were used to implement the functions.
74LS151 8:1 MUX
74LS138 3:8 Decoder
74_08 quad 2-input AND gates
The functions are given as follows.
𝑓2 (𝑥2 , 𝑥1 , 𝑥0 ) = (𝑥2 + 𝑥1 + 𝑥0 )(𝑥2 + 𝑥
̅̅̅1 + ̅̅̅)(𝑥
𝑥0 ̅̅̅2 + 𝑥1 + ̅̅̅)
𝑥0
𝑓1 (𝑥2 , 𝑥1 , 𝑥0 ) = 𝑥2 ⊕ 𝑥1 ⊕ 𝑥0
𝑓0 (𝑥3 , 𝑥2 , 𝑥1 , 𝑥0 ) = ∏ 𝑀(0,2,5,9,12,14)
A conversion table is given in Table 1 using inputs 𝑥3 , 𝑥2 , 𝑥1 , and 𝑥0 and with outputs of
𝑓2 , 𝑓1 and 𝑓0 . Functions 𝑓2 and 𝑓1 only consider 𝑥2 , 𝑥1 , and 𝑥0 , and so the outputs for
𝑥3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Table 1: Truth Table for 𝑓2 , 𝑓1 and 𝑓0
Input
Output
𝑥2
𝑥1
𝑥0
𝑓2
𝑓1
0
0
0
0
0
0
0
1
1
1
0
1
0
1
1
0
1
1
0
0
1
0
0
1
1
1
0
1
0
0
1
1
0
1
0
1
1
1
1
1
0
0
0
x
x
0
0
1
x
x
0
1
0
x
x
0
1
1
x
x
1
0
0
x
x
1
0
1
x
x
1
1
0
x
x
1
1
1
x
x
𝑓0
0
1
0
1
1
0
1
1
1
0
1
1
0
1
0
1
Converting Truth Table 1 into Karnaugh maps results in the following Map 1 - 4. Since
we want 𝑓0 to be able to be represented along with the other two functions, we need to compress
it in terms of three variables for the three input MUX gate and have the three switches for the
Decoder gate.
Map 1: 𝑓0 Karnaugh Map
00
01
11
𝑥3 , 𝑥2 , 𝑥1 , 𝑥0
00
0
1
1
01
1
0
1
11
0
1
1
10
1
0
1
10
0
1
0
1
Map 2: 𝑓0 Compressed Karnaugh Map
0
1
𝑥3 , 𝑥2 , 𝑥0
00
0
1
01
1
𝑥1
11
0
1
10
1
𝑥1
Map 3: 𝑓1 Karnaugh Map
00
01
11
𝑥2 , 𝑥1 , 𝑥0
0
0
1
0
1
1
0
1
10
1
0
Map 4: 𝑓2 Karnaugh Map
00
01
11
𝑥2 , 𝑥1 , 𝑥0
0
0
1
1
1
1
0
1
10
1
0
The circuit diagram in Figure 1 can easily be made from these Karnaugh maps since the
MUX gate outputs the full function of 𝑓0 . Functions 𝑓2 and 𝑓1 can be derived from the Decoder
gate, since the Decoder outputs all possible combinations of the three inputs in terms of the
inputs and their inverted form, and the needed Product of Sum form terms can be combined with
an AND chip.
Figure 1: 𝑓2 , 𝑓1 and 𝑓0 Combined Circuit
With the given circuit diagram, the function outputs can be displayed in Truth Table 2
Table 2: Truth Table of outputs for circuit diagram
Input
Output
𝑥3
𝑥2
𝑥1
𝑥0
𝑓2
𝑓1
𝑓0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
1
0
1
1
0
0
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
0
0
1
1
0
1
0
0
1
1
1
1
1
1
0
0
0
0
0
1
0
0
1
1
1
1
0
1
0
1
1
1
0
1
1
0
0
1
1
0
0
1
1
1
1
0
1
0
0
1
1
1
0
1
0
1
1
1
1
1
1
0
1
0
1
1
0
1
1
1
0
1
1
0
1
0
1
Since the functions of 𝑓2 and 𝑓1 do not depend on 𝑥3 , the first half of Table 2 is repeated
for 𝑓2 and 𝑓1 . Because the values in Table 1 that are marked as ‘don’t care’ coincide with the
values that are repeated, Table 1 and Table 2 are equivalent, therefore the circuit was designed
correctly.
The 74LS138 3:8 Decoder chip outputs the Maxterms of the inputs. The maxterms make
it easier for a NAND or NOR configuration to be created from the outputs of the chip.