Rapid, Predictive Modeling for High
Frequency Interconnect on Low Cost
Substrates
Dissertation Defense Presentation
Spring, 2005
Jaemin Shin
Advisor: Dr. Martin A. Brooke
School of Electrical and Computer Engineering
Georgia Institute of Technology, Atlanta, GA 30332
April 2005
Outline

Objective

Limitations of Electrical Board-level Interconnects

Background

Motivation

Proposed Modeling Procedure

Modeling of Straight Microstrip Lines

Modeling of Serpentine Interconnects

Conclusions
2
Objective

Our goal is to develop a rapid, predictive (scalable)
measurement-based modeling method for high
frequency interconnects on low cost substrates:

Modeling of interconnect structures

Prediction by scalability and interpolation

Evaluation of modeling performance with measured
behaviors and a simulation tool.
3
Outline

Objective

Limitations of Electrical Board-level Interconnects

Board-level Interconnect

Geometrical limitations at high frequency

Background

Motivation

Proposed Modeling Procedure

Modeling of Straight Microstrip Lines

Modeling of Serpentine Interconnects

Conclusions
4
Board-level Interconnect in Telecommunication
Backplane Interconnect
Chip-to-chip Interconnect
[1] http://www.ece.gatech.edu/research/labs/mag/mixed_signal/mixedsig3.htm
5
Limitations of Electrical Board-level Interconnects 1

Signal integrity problems


Transmission-line effects

High rising and falling time and delay time

High channel loss of long channels
Non-ideal effects at high frequency




Skin effect
Frequency-dependent dielectric loss
Manufacturing variations
Geometrical issues

Geometrical discontinuity


Dense connections


Reflection loss (Echo effect)

Self-coupling
Crosstalk
Electromagnetic interference (EMI)
6
Limitations of Electrical Board-level Interconnects 2

Switching noise

High power consumption

Thermal problem
Approaches to addressing the limitations

Advanced electrical technology





High speed interconnect driver : LVDS, CML, and PECL
Clock & data recovering circuit (CDR) Contribution of this thesis work
High performance board material
Co-design with accurate channel model
Optical interconnect technology

Optical technology

VSCEL (Vertical Surface Cavity Emitting Laser), micro-mirror, and
optical waveguide embedding techniques
7
Trend of Board-level Interconnect

60
According to 2003 ITRS
(International Technology
Roadmap of Semiconductor)

In near-term years, off-chip
frequency will be to keep its
speed lower than 10 GHz.

Most telecommunication
companies have preferred the use
of low cost FR4 materials.

Moreover, cost-performance and
low-cost products occupy a
considerable area of the market

Thus, interconnects on FR4 are
still attractive.

However, at high frequency,
FR4 material needs more design
work with an efficient, accurate
model to achieve acceptable
electrical performance.
Frequency (GHz)
50
40
30
20
10
0
1999
2001
2003
2005
2007
2009
2011
2013
2015
2017
Year
On-chip frequency
Off-chip frequency
[2] http://public.itrs.net/Files/2003ITRS/Home2003.htm
8
Example 1: Long Straight Lines of Different Dielectric Materials 1



Four different board materials
Configuration of striplines with 50-Ω characteristic impedance
12-mil wide, 18-inch long channel line
εr
εr
tanδ
@1 MHz
@1 GHz
@1GHz
Relative
Cost
FR4
4.30
4.05
0.020
1
GETEK
4.15
4.00
0.015
1.1
ROGERS
4350/4320
3.75
3.60
0.009
2.1
ARLON CLTE
3.15
3.05
0.004
6.8
Material
[3] http://www.tycoelectronics.com/products/simulation/files/papers/dc00brdh.pdf
9
Example 1: Long Straight Lines of Different Dielectric Materials 2

Eye diagrams at 5 Gbps and 10 Gbps
a) 5 Gbps
b) 10 Gbps
[3] http://www.tycoelectronics.com/products/simulation/files/papers/dc00brdh.pdf
10
Example 2: Long Straight Lines with a Via




Low-cost FR4 material
Microstrip with
50-Ω characteristic impedance
Via connection
Three different line lengths (1, 10 and 20cm)
and three different speeds (1 G, 2.5 G and10 Gbps)
Straight transmission line without via
130 mil
1.7 mil
20 mil
FR4 εr=4.3
Straight transmission line with via
11
Example 3: Interconnect Structures with Couplings and Bends


130-mil wide serpentine structures on FR4 board
Coupling effects and bending effects
130-mil wide M-shaped
serpentine structure
with 65-mil spacing
130-mil wide M-shaped
serpentine structure
with 130-mil spacing
Bending effect
& Line length
Coupling effect
10Gbps
12
130-mil wide 7-turn
serpentine structure
with 130-mil spacing
Outline

Objective

Limitations of Electrical Board-level Interconnects

Background


Non-ideal Effects
Previous Modeling Methods

Motivation

Proposed Modeling Procedure

Modeling of Straight Microstrip Lines

Modeling of Serpentine Interconnects

Conclusions
13
Non-ideal Effects on Transmission Line 1

Skin effect
Skin depth  
2
0


F0
=130mil
14
m
Non-ideal Effects on Transmission Line 2
Frequency-dependent dielectric loss


FR4
Complex dielectric
constant due to the
electric polarization
BT/Epoxy
   '-j "

Polymide
Loss tangent
tan  
951 Green
TapeTM
" 

 '  '
[4] D. I. Amey and S. J. Horowitz, "Materials performance at frequencies up to 20 GHz," presented at IEMT/IMC Symposium, 1997., 1st
[Joint International Electronic Manufacturing Symposium and the International Microelectronics Conference], 1997.
15
Non-ideal Effects on Transmission Line 3

Manufacturing variations

Composite ratio (glass- to- resin ratio)
 r   rsnVrsn   glsVgls
Metal

Conductor surface roughness

Too rough and random
FR4

Fabrication tolerance

The need for statistical approaches
16
SEM (Scanning Electron
Microscope) picture
Previous Modeling Methods


Earlier interconnect research: microwave and
digital engineering

Microwave engineering: transmission lines in narrow
bandwidths

Digital engineering: timing analysis at low frequency

High-frequency digital interconnect: frequency analysis
based on the electromagnetic equations, numerical
methods, and measurement techniques
Three classical methods

Analytical equation-based method

Numerical full-wave-based method

Measurement-based method
17
Analytical Equation-based Method

Direct derivation of a model from the fundamental
electromagnetic equations

Neither accurate nor practical unless the structures
of interest are simple

Not flexible

Difficult to develop, in general

Basic insight and background for the two following
methods
18
Numerical Full-wave-based Method

Maxwell equation-based method

Discretization of a structure into small segments to
obtain accurate responses of the entire system (tradeoff between accuracy and computational efficiency)

Accurate and highly flexible

Slow speed and extensive memory requirements for
complex geometrical systems

Difficult to incorporate the non-ideal effects such as
frequency-dependent variables and manufacturing
variations
19
Measurement-based Method

Measured data in the frequency domain can be used to
find circuit model parameters. Optimization techniques are
used for the equivalent-circuit parameters

Statistical modeling approaches can be applied to
overcome the manufacturing variations

The non-ideal effects are naturally incorporated

Compatible with the existing circuit simulators

Very accurate and fast

Needs to be more flexible
20
Motivation

The need for an accurate, rapid model for interconnects on FR4
to address electrical board-level interconnect limitations at high
frequency





Advantages of the measurement-based method compared with
others





FR4 material limitations
Non-ideal effects
Geometrical limitations
Inefficiency of numerical methods for complex structures
Easy: Compatibility with the circuit simulators
Efficient - Very fast simulation speed
- No need for heavy computation resources
Accurate: Incorporation of the non-ideal effects
Statistical: Incorporation of the fabrication tolerance
Co-simulation
and Co-design
with circuits
The need for improved flexibility: the use of scalability and
interpolation can achieve this goal.
21
Proposed Modeling Procedure
Determining the interconnect
structures to be considered
Co-simulation and co-design
with circuitry
Defining building blocks
Generating model library
Design and fabrication
Statistical approaches
Calibration and measurement
Verification with
measured data
Extraction of EC-parameters
using optimization
Initial modeling
Predicting other structures by using
the scalable model and interpolation
Extension
22
Generalization
Performance Evaluation

Modeling performance attributes



Accuracy

Frequency domain: Impedance parameters

Time domain: Eye diagrams
Efficiency

Computation resources

Simulation times
Utility

Limited to accessibility
23
Measurement Setup

Frequency response




Channel characterization
 Z-parameters converted from
measured S-parameters
SOLT (Short-open-load-thru) calibration
using 3.5 mm calibration kit
Vector network analyzer (VNA)
Time response


Interconnect verification
 Eye diagrams
Pattern generator and digital
oscilloscope
VNA
Port 1
Port 2
Digital Oscilloscope
Pattern generator
Device Under Test (DUT)
DUT
24
Momentum Simulation
2400 mils
Z11 Phase (degree)
Z21 Phase (degree)
Z21 Magnitude (dB)
Z11 Magnitude (dB)
Momentum simulation
Layout
Measured
Momentum
Momentum simulation results of the 2400 mil microstrip with SMA connector
25
Outline

Objective

Limitations of Electrical Board-level Interconnects

Background

Motivation

Modeling Procedure

Modeling of Straight Microstrip Lines

Modeling Description

Results and Performance Comparison

Modeling of Serpentine Interconnects

Conclusions
26
Building Block Diagrams and Equivalent Circuits

400-mil long line

800-mil long line
50 mil
SMA
Building
Block
SMA
Building
Block
Rectangular
Building Block
Rectangular Building Block
SMA Connector Building Block
27
Test Structures of the Straight Microstrip Lines
1600 mil long line
2400 mil long line
1200 mil long line
800 mil long line
28
400 mil long line
(Predictive model)
Optimization of Equivalent-circuit Parameters
Equivalent-circuit block
SMA connector
building block
S-parameter simulation setup
50 mil long microstrip
building block
Measured s-parameter
data block
Optimization setup
Initial values
29
Z11 Phase (degree)
Z21 Phase (degree)
Z11 Magnitude (dB)
Z21 Magnitude (dB)
Optimized Z-parameter Data of the 400-mil Long Line
Measured
30
Modeled
Z11 Phase (degree)
Z21 Phase (degree)
Z21 Magnitude (dB)
Z11 Magnitude (dB)
Predicted Z-parameter Data of the 800-mil Long Line
Measured
Modeled
31
Momentum
Z11 Phase (degree)
Z21 Phase (degree)
Z21 Magnitude (dB)
Z11 Magnitude (dB)
Predicted Z-parameter Data of the 2400-mil Long Line
Measured
Modeled
32
Momentum
Comparison of Eye Diagrams of the 2400-mil Long Line

Measured eye diagrams
1 Gbps
2.5 Gbps
5 Gbps
7.5 Gbps
500 mV
0V

Simulated eye diagrams using the predicted structure
500 mV
0V
33
10 Gbps
Simulation Time vs. Line Length

Simulation Resources

a UNIX computer

500 MHz Ultra SPARC IIi
CPU

2 G-byte memory
34
Outline

Objective

Limitations of Electrical board-level Interconnects

Background

Motivation

Modeling Procedure

Modeling of Straight Microstrip Lines

Modeling of Serpentine Interconnects


Modeling Description

Results and Performance Comparison

Interpolation
Conclusions
35
Building-block Diagrams and Equivalent Circuits

N-shaped structure

M-shaped structure
SMA Connector Building Block
Coupled Rectangular Building Block
Uncoupled Rectangular Building Block
36
U-shaped Building Block
Combination of Equivalent Circuits

Equivalent circuits of the N-shaped structure
37
Test Structures 1

3 different widths and 3 different spacings
Predicting
38
Test Structures 2

Four additional extended structures


130-mil width and 130-mil spacing (1S)
4-, 5-, 6- and 7- turn serpentine interconnect structures
4 turns
6 turns
5 turns
39
7 turns
Optimization of Equivalent-circuit Parameters
Predictive equivalent circuit block
Measured s-parameter
data block
S-parameter
simulation setup
Initial values
SMA connector
U-shape
Uncoupled Rectangle
Optimization setup
Uncoupled Rectangle
Coupled Rectangle
Mutual Coupling Element
40
Z11 Phase (degree)
Z21 Phase (degree)
Z21 Magnitude (dB)
Z11 Magnitude (dB)
Optimized Z-parameter Data of the N-shaped Serpentine Structure
Measured
41
Modeled
Z11 Phase (degree)
Z21 Phase (degree)
Z21 Magnitude (dB)
Z11 Magnitude (dB)
Predicted Z-parameter Data of the M-shaped Serpentine Structure
Measured
Modeled
42
Momentum
Comparison of Eye Diagrams of the M-shaped Serpentine Structure

Measured eye diagrams
1 Gbps
2.5 Gbps
5 Gbps
7.5 Gbps
500 mV
0V

Simulated eye diagrams using the predicted structure
500 mV
0V
43
10 Gbps
Z11 Phase (degree)
Z21 Phase (degree)
Z21 Magnitude (dB)
Z11 Magnitude (dB)
Predicted Z-parameter Data of the 7-turn Serpentine Structure
Measured
Modeled
44
Momentum
Comparison of Eye Diagrams of the 7-turn Serpentine Structure

Measured eye diagrams
1 Gbps
2.5 Gbps
5 Gbps
7.5 Gbps
500 mV
0V

Simulated eye diagrams using the predicted structure
500 mV
0V
45
10 Gbps
Simulation Time vs. Number of Turns

Simulation Resources

a UNIX computer

500 MHz Ultra SPARC IIi CPU

2 G-byte memory
N-shaped
M-shaped
46
Interpolation

N-shaped Structure Interpolation
65-mil spacing (0.5 S)
Spacing-interpolation
130-mil width and
130-mil spacing (1S)
104-mil width (-20%)
156-mil width (+20%)
Width-interpolation
260-mil spacing (2 S)
47
Z-parameter Data of N-shaped Structure Predicted by Width-interpolation
Z11 Phase (degree)
Z21 Phase (degree)
Z21 Magnitude (dB)
Z11 Magnitude (dB)
Predicted Z-parameter data of the 130-mil wide N-shaped serpentine structure

Measured
48
Modeled
Comparison of Eye Diagrams of the Predicted N-shaped Structure
by Width-interpolation

Measured eye diagrams
1 Gbps
2.5 Gbps
5 Gbps
7.5 Gbps
10 Gbps
500 mV
0V

Simulated eye diagrams using the predicted structure obtained by widthinterpolation
500 mV
0V
49
Z-parameter Data of M-shaped Structure Predicted by Width-interpolation
Z11 Phase (degree)
Z21 Phase (degree)
Z21 Magnitude (dB)
Z11 Magnitude (dB)
Z-parameter data of the 130-mil wide M-shaped serpentine structure predicted
using EC-parameters of the width-interpolated N-shaped structure

Measured
50
Modeled
Comparison of Eye Diagrams of the Predicted M-shaped Structure using
the EC-parameters of the Width-interpolated N-shaped Structure

Measured eye diagrams
1 Gbps
2.5 Gbps
5 Gbps
7.5 Gbps
10 Gbps
500 mV
0V

Simulated eye diagrams using the width-interpolated predicted structure
500 mV
0V
51
Z-parameter Data of N-shaped Structure Predicted by Spacing-interpolation
Predicted Z-parameter data of the N-shaped serpentine structure with 130-mil spacing (1S)
Z11 Phase (degree)
Z21 Phase (degree)
Z11 Magnitude (dB)
Z21 Magnitude (dB)

Measured
52
Modeled
Comparison of Eye Diagrams of the Predicted N-shaped Structure
Obtained by Spacing-interpolation

Measured eye diagrams
1 Gbps
2.5 Gbps
5 Gbps
7.5 Gbps
10 Gbps
500 mV
0V

Simulated eye diagrams using the spacing-interpolated predictive model
500 mV
0V
53
Predicted Z-parameter Data of M-shaped Structure by Spacing-interpolation
Z11 Phase (degree)
Z21 Phase (degree)
Z21 Magnitude (dB)
Z11 Magnitude (dB)
Z-parameter data of the M-shaped serpentine structure with 130-mil spacing (1S) predicted
using EC-parameters of the spacing-interpolated N-shaped structure

Measured
54
Modeled
Comparison of Eye Diagrams of the Predicted M-shaped Structure
using EC-parameters of the Spacing-interpolated N-shaped Structure

Measured eye diagrams
1 Gbps
2.5 Gbps
5 Gbps
7.5 Gbps
10 Gbps
500 mV
0V

Simulated eye diagrams from the predictive model by spacing-interpolation
500 mV
0V
55
Conclusions

A rapid, predictive measurement-based modeling method was
developed for high-frequency interconnects on FR4.

Our method was applied to the modeling of straight microstrip lines
and serpentine interconnect structures.

The predictive power of the developed scalable models was
demonstrated in several extended interconnect structures, and the
ability to use interpolation to predict the high frequency performance
of structures with differently sized building blocks was demonstrated.

The usefulness of this predictive method was validated by comparing
our predictions with measurements both in the frequency and time
domains and by comparing our predictions with the ADS momentum
simulations in terms of efficiency and accuracy.

Therefore, this proposed high-frequency interconnect modeling
method is not only efficient but accurate as well, compared with the
measured behaviors and the momentum simulation. Furthermore, the
interpolation enable fast accurate predictions for variations of
interconnects in width and spacing.
56
Publications Generated
1)
2)
3)
4)
5)
6)
7)
8)
9)
J. Shin, C.-S. Seo, A. Chellappa, M. Brooke, A. Chattejce and N. M. Jokerst, "Comparison of electrical
and optical interconnect," Electronic Components and Technology Conference, 2003.
O. Bourdreaux, S.-Y. Cho, J. Shin, A. Chellappa, D. Schimmel, M. Brooke and N. M. Jokerst, "Optical
chip-to-chip interconnects for memory systems," presented at Lasers and Electro-Optics Society, LEOS,
the 16th Annual Meeting of the IEEE, 2003.
C. Cha, J. Shin, Z. huang, N. M. Jokerst and M. Brooke, “High-Frequency Equivalent Circuit-Level
Model of MSM PD for Optical Front-end Receiver Applications,” presented at Asia Pacific Microwave
conference, APMC 2003.
N. M. Jokerst, T. K. Gaylord, E. Glytsis, M. A. Brooke, S. Cho, T. Nonaka, T. Suzuki, D. L. Geddis,
J. Shin, R. Villalaz, J. Hall, A. Chellapa and M. Vrazel,"Planar lightwave integrated circuits with
embedded actives for board and substrate level optical signal distribution," Advanced Packaging, IEEE
Transactions on [see also Components, Packaging and Manufacturing Technology, Part B: Advanced
Packaging, IEEE Transactions on], vol. 27, pp. 376-385, 2004.
J. Shin, C. Cha, S. Cho, J. Kim, N. M. Jokerst and M. Brooke,"FR4 printed circuit board design for
Giga-bits embedded optical interconnect applications," presented at Electronic Components and
Technology, ECTC '04. Proceedings, 2004.
J. Shin, S.-W. Seo, S.-Y. Cho, J. H. Kim, M. Brook and N. M. Jokerst,"Embedded photodetectors in
polymer waveguides for optical interconnect integrated with a Si-Ge transimpedance amplifier circuit
operating at 2.5 Gbit/s,"presented at Biophotonics/Optical Interconnects and VLSI Photonics/WBM
Microcavities, Digest of the LEOS Summer Topical Meetings, 2004.
J. H. Kim, J. Shin, C. Cha, N. Jokerst and M. Brooke, “Wideband multiple resonance small-signal laser
diode model for the co-design of laser drive circuits,” presented at the 47th Midwest Symposium, 2004.
J. Shin, J. H. Kim, C. Cha, N. M. Jokerst and M. Brooke,”Rapid, Predictive Measurement-based
Modeling for High Frequency Interconnect on FR4 Substrate,” accepted at Electronic Components and
Technology, 2005.
J. H. Kim, J. Shin, C. Cha, N. M. Jokerst, and M. A. Brooke, “An Improved Wideband Laser Diode
Lumped Element Equivalent Circuit Model for the Optoelectronic Circuit Design,” submitted at
Information and Communication Engineers (IEICE) Transactions on Information and Systems, 2005
57
Question
Thank You
58