COSC 3330/6308
Solutions to
First Problem Set
Jehan-François Pâris
September 2012
First problem (I)

A program consists of two parts, namely
– One part is purely sequential and takes
64 s to complete
– Another part takes 1,024 s when run on a
uniprocessor architecture
 Can be easily decomposed into two or
more parallel tasks
 Speedup would be proportional to the
number of tasks executing in parallel.
First problem (II)


What would be the speedups that the
program would achieve if it was to run on
computers with 2, 4, 8, 16, and 32
processors?
What would be the maximum speedup that
the program would achieve if it was to run on
a computer with an unlimited number of
processors?
Answer (I)

Will use Amdahl's law
Tn  To
Speedup 
Tn  Ti
Answer (II)
Sequential Number of
Part (s)
Proc.
64
1
64
2
64
4
64
8
64
16
64
32
Other
Part (s)
1,024
512
256
128
64
32
Total
(s)
Speedup
1,088
576
320
192
128
96
NA
1.889
3.400
5.667
8.500
11.333
Second problem

Simplify the two following logical
expressions:
–
ABC'D' + AB'D' + ACD + CD
–
(A  BC) (B + A)
using both algebra and Karnaugh maps.
First expression (I)

ABC'D' + AB'D' + ACD + CD =
ABC'D' + AB'D' + CD =
ABC'D' + AB'D' + AB'C'D' + CD =
AC'D' + AB'D' + CD
First expression (II)
C'D'
C'D
CD
CD'
A’B’
0
0
1
0
A’B
0
0
1
0
AB
1
0
1
0
AB’
1
0
1
1
AC'D' + AB'D' +CD
Second expression (I)

(A  BC) (B + A) =
(A(BC)' + A'BC) (A + B) =
(AB' + AC' + A'BC) (A + B) =
AB' + AC' + A'BC + ABC' =
AB' +AC' +A'BC
Second expression (II)
BC A  BC
A
B
C
A+ B
PRODUCT
F
F
F
F
F
T
F
F
F
F
F
F
F
F
F
F
T
T
F
T
F
T
F
T
T
T
F
T
T
T
T
F
F
T
F
T
F
F
F
F
T
T
T
T
T
T
T
T
T
T
T
T
T
F
T
F
A'BC
AB'C'
AB'C
ABC'
Second expression (III)
B'C'
B'C
BC
BC'
A’
0
0
1
0
A
1
1
0
1
AB' + AC' +A'BC
Second expression (IV)
A'B'
A'B
AB
AB'
C’
0
0
1
1
C
0
1
0
1
AB' + AC' +A'BC
Third problem

Simplify the expression
–
(ABC)' (A + DE)' (A  BC) (B + E)
and convert it to a form that can be
represented using a programmable logic
array.
Answer (I)


(ABC)' (A + DE)' (A  BC) (B + E)
Let us do it in two parts
– (ABC)' (A + DE)' =
(A' + B' + C')(A'(DE)') =
(A' + B' + C')(A'(D' +E') =
A'(D' +E') + A'B'(D' +E') +A’C’(D’ +E’) =
A'D' +A'E'
Answer (II)

The second part is
– (A  BC) (B + E) =
(A(BC)' + A'BC)(B + E) =
(AB' + AC' + A'BC)(B + E) =
ABC' + A'BC + AB'E + AC'E + A'BCE
Answer (III)


The product is
– (A'D' +A'E')
(ABC' + A'BC + AB'E + AC'E + A'BCE) =
A'BCD' + A'BCE' + A'BCD'E =
A'BCD' + A'BCE'
Sum of products can be represented by a PLA
I checked the answer on a spreadsheet
with 25 rows and 14 columns
Fourth problem

Implement the double implication operation:
– A  B = AB +A’B’
using only NAND gates.
NAND gates

A nand B = (AB)' = A' + B'

nand (A) nand nand(B) = (A'B')' = A + B

nand(A nand B) = (AB)'' = AB

nand(nand(A) nand nand(B)) =
(A' B')'' = A'B'
Answer
A
A+B
((A + B)(A' + B')' =
(A + B)' + (A' + B')' =
A'B' +AB
B
A
B
A'+B'
I started with a solution having
more NANDs and simplified it
Fifth problem

Build a regular D flip-flop using an R’S’ latch,
that is, an RS latch with inverted values for R
and S, and as few NOR gates as possible.
NOR gates

A nor B = (A + B)' = A' B'

nor (A) nor nor(B) = (A' + B')' = AB

nor(A nor B) = (A+B)'' = A + B

nor(nor(A) nor nor(B)) =
(A' + B')'' = A' + B'
From S'R' latch to D flip-flop


S'R' has three inputs
S'
Q'
– S' sets latch when S' = 0
R'
Q
and clock = 1
– R' resets latch when R' = 0
and clock = 1
Clock
D flip-flop
– Stores a 1 at clock transition when input is 1
– Stores a 0 at clock transition when input is 0
D flip-flop using an S-R latch
X
Clock
S
Q
R
Q'
Clock
D flip-flop using an S'-R' latch
X
Clock
S'
Q
R'
Q'
Clock
Introducing NORs
X
Clock
S'
Q
R'
Q'
Clock
(Clock+Clock')'=ClockClock'
Note


The solution is fairly simple because we
assumed that the R'S' latch had a clock entry
Solution for R'S' latch without clock input is
more complex
S’
Q
R’
Q’
Sixth problem (I)

Build a synchronous sequential circuit with
– Two inputs, respectively named P—for
plus—and M—for minus
– Two outputs respectively named O—for
overflow—and U—for underflow
Sixth problem (II)

The transitions are:
P/00
P/00
000
P/10
010
001
M/00
P/00
M/00
M/00
M/01
M/00
M/00
111
100
101
P/00
P/00
M/00
M/00
110
P/00
011
P/00
Answer


Eight states
– Three flip-flops X Y Z
Will consider separately
– How P inputs affect X, Y, Z
– How M inputs affect X, Y, Z
– When counters outputs O and U
How P inputs affect Z
Y'Z'
Y'Z
YZ
YZ'
P'X'
0
1
1
0
P'X
0
1
1
0
PX
1
0
0
1
PX’
1
0
0
1
Solution

Z = P'Z + PZ'
– Will use a T flip-flop triggered by P
How P inputs affect Y
Y'Z'
Y'Z
YZ
YZ'
P'X'
0
0
1
1
P'X
0
0
1
1
PX
0
1
0
1
PX’
0
1
0
1
Solution

Y = P'Y + PYZ' + PY'Z
– Will use a T flip-flop triggered by PZ
How P inputs affect X
Y'Z'
Y'Z
YZ
YZ'
P'X'
0
0
0
0
P'X
1
1
1
1
PX
1
1
0
1
PX’
0
0
1
0
Solution

X = P'X + PXY' + PXZ' + PX'YZ
– Will use a T flip-flop triggered by PYZ
How M inputs affect Z
Y'Z'
Y'Z
YZ
YZ'
M'X'
0
1
1
0
M'X
0
1
1
0
MX
1
0
0
1
MX’
1
0
0
1
Solution

Z = M'Z + MZ'
– Will use a T flip-flop triggered by M
How M inputs affect Y
Y'Z'
Y'Z
YZ
YZ'
M'X'
0
0
1
1
M'X
0
0
1
1
MX
1
0
1
0
MX’
1
0
1
0
Solution

Y = M'Y + MYZ + M Y'Z'
– Will use a T flip-flop triggered by MZ'
How M inputs affect X
Y'Z'
Y'Z
YZ
YZ'
M'X'
0
0
0
0
M'X
1
1
1
1
MX
0
1
1
1
MX’
1
0
0
0
Solution

X = M'X + MXY + MXZ +MX'Y'Z'
– Will use a T flip-flop triggered by MY'Z'
How P inputs affect O
Y'Z'
Y'Z
YZ
YZ'
P'X'
0
0
0
0
P'X
0
0
0
0
PX
0
0
1
0
PX’
1
0
0
0
Solution

O = PXYZ
How M inputs affect U
Y'Z'
Y'Z
YZ
YZ'
M'X'
0
0
0
0
M'X
0
0
0
0
MX
0
0
0
0
MX’
1
0
0
0
Solution

U = MX'Y'Z'
– Will use a T flip-flop triggered by MY'Z'
Summary


Flip-flops
– Z: T flip-flop triggered by P + M
– Y: T flip-flop triggered by PZ + MZ'
– X: T flip-flop triggered by PYZ + MY'Z'
Outputs
– O = PXYZ
– U = MX'Y'Z'