CEC 222 Digital Electronics Lab
Spring 2015
Lab 7: Introduction to a Hardware
Definition Language (VHDL)
Learning Objectives:

Introduction to VHDL

Demonstrate alternative VHDL code structures for combinational logic implementation.
Lab Overview:
An FPGA (or CPLD – see Figure 1) is
effectively a sea of gates, and more recently,
additional more sophisticated building blocks
(e.g., DSP blocks, …). The connectivity between
these gates (and input or output ports) can be
described via schematic designs (prior labs) or
using a Hardware Definition Language (HDL). The
two dominant HLD languages are Verilog and
Figure 1 A single block of an Altera Max V FPGA
VHDL. The latter was developed in the late 80’ by
the U.S. Department of Defense based on the ADA programming language.
We will revisit the majority voting problem of Lab 3 (see Table 1) and develop solutions to that problem and
the 7-segment decoder using VHDL. The optional (extra credit) exercise addresses building a 4:1 MUX in VHDL.
YOUR NAME(S)
Lab 7: Intro. to a Hardware Definition Language (VHDL)
Page 1 of 11
CEC 222 Digital Electronics Lab
Spring 2015
Pre-Lab (10%)
Using VHDL typically there exists more than one way to code a solution to any given problem. Partial VHDL
implementations to three different code alternatives are provided as potential solutions to the majority voting
problem from Lab 3.
Task 1.
Fill in the blanks to complete the VHDL code below required using “method1.vhd“.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Majority_Voting1 is
Port ( A, B, C : in
STD_LOGIC;
F : out STD_LOGIC);
end Majority_Voting1;
architecture My_Architecture of Majority_Voting1 is
begin
-Minterm Expansion: F = m3 + m5 + m6 + m7
F <= (not A AND
B AND
C) OR
(
A AND not B AND
C) OR
(_________________________) OR
(A AND
B AND
C);
end My_Architecture;
Task 2.
Fill in the blanks to complete the VHDL code below required using “method2.vhd“.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Majority_Voting2 is
Port ( A, B, C : in
STD_LOGIC;
F : out STD_LOGIC);
end Majority_Voting2;
architecture My_Architecture of Majority_Voting2 is
begin
-Minterm
F <= '1' when (A = '0'
'1' when (A = '1'
'1' when (A = '_'
'1' when (A = '1'
'0';
end My_Architecture;
Task 3.
YOUR NAME(S)
Expansion: F = m3
AND B = '1' AND C
AND B = '0' AND C
AND B = '_' AND C
AND B = '1' AND C
+
=
=
=
=
m5 +
'1')
'1')
'_')
'1')
m6 + m7
else
else
else
else
Fill in the blanks to complete the VHDL code below required using “method3.vhd“.
Lab 7: Intro. to a Hardware Definition Language (VHDL)
Page 2 of 11
CEC 222 Digital Electronics Lab
Spring 2015
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Majority_Voting3 is
Port ( A, B, C : in
STD_LOGIC;
F : out STD_LOGIC);
end Majority_Voting3;
architecture My_Architecture of Majority_Voting3 is
signal ABC : STD_LOGIC_VECTOR(2 downto 0);
begin
-Minterm Expansion: F = m3 + m5 + m6 + m7
ABC <= A & B & C; -- Concatenate the three bits
with ABC select
F <= '1' when "011",
'1' when "101",
'1' when "___",
'1' when "111",
'0' when others;
end My_Architecture;
YOUR NAME(S)
Lab 7: Intro. to a Hardware Definition Language (VHDL)
Page 3 of 11
CEC 222 Digital Electronics Lab
Spring 2015
Experiments (90%)
EXPERIMENT 1.
IMPLEMENTING THE MAJORITY VOTING CIRCUIT IN VHDL
In this initial experiment you will be implementing the majority
voting circuit which you designed in Lab 3 using the three different
VHDL code segments from the pre-lab.
Step 1.a: Create a project with all three methods

Open ISE and create a New Schematic Project named
“Lab_7_Experiment1”

Add a new source of type Schematic named “main” to the
project

Copy the three files “method1.vhd“,“method2.vhd“, and “method3.vhd“ to
your desktop.

Right click on the project and select “Add Copy of Source” then navigate to
“method1.vhd” to add the file to your project.
 Repeat the process to add method2.vhd and method3.vhd.

Edit the three method*.vhd files to include the corrections you determined in
the pre-lab.

Select the file “method1.vhd” and under “Design Utilities” click on “Create
Schematic Symbol”
 This will create a symbol entitled “Majority_Voting1”
 Add this symbol to your schematic

Repeat this process for the method2.vhd and method3.vhd files.

Connect the input ports of the three symbols to ports named “A”, “B”,
and “C”.

Connect the output ports of the three symbols to ports named “F1”,
“F2”, and “F3”.
Task 4.
YOUR NAME(S)
Insert a screenshot of your schematic (it should have three symbols) into Figure 2.
Lab 7: Intro. to a Hardware Definition Language (VHDL)
Page 4 of 11
CEC 222 Digital Electronics Lab
Spring 2015
Figure 2 Realizing the majority voting circuit via three VHDL code segments
Step 1.b: Test your majority voting circuit design via a simulation.
Developing a simulation affords the opportunity to test our design without using hardware. By stimulating
our design with relevant inputs (e.g., all possible input combinations) and observing the output signals we can
readily verify the behavior of our design.

With the “main.sch” highlighted select the Simulation view and double click on “Simulate Behavioral
Model.” The ISim window will appear (see below).
YOUR NAME(S)
Lab 7: Intro. to a Hardware Definition Language (VHDL)
Page 5 of 11
CEC 222 Digital Electronics Lab

Spring 2015
In the top enter of the window change the 1.00us simulation
duration to 8.00us

Click on the restart icon (

In order to generate all eight (i.e., 23) possible input patterns,
) to clear the traces
go to the ISim center pane and Right click on the signal “a”
and select “Force Clock” and set:
 Leading edge value = 0
 Trailing edge value = 1
 Period = 8us

Do the same with signal “b”, however, set the Period = 4us

Do the same with signal “c”, however, set the Period = 2us

Finally, click on the run (

You might want to click on the “zoom to full view” icon (
YOUR NAME(S)
) button to generate the waveforms.
)
Lab 7: Intro. to a Hardware Definition Language (VHDL)
Page 6 of 11
CEC 222 Digital Electronics Lab
Spring 2015
Question 1. Consider how this waveform compares with the truth table of Table 1. Specifically, which row
corresponds to time interval 4us to 5us? __________________
Task 5.
Insert a screenshot of your simulation waveform into Figure 3.
Figure 3 Simulation waveform
Step 1.c: Program your FPGA and test the three VHDL designs

Reset your view to implementation

Add an Implementation Constraints File (UCF) entitled
“Majority_Voting” to your project in order to connect:
 Inputs: “A” to SW2 = FPGA pin K3, “B” to SW1 = FPGA pin L3,
“C” to SW0 = FPGA pin P11 , and
 Output: “F1” to LED1 = FPGA pin M11, “F2” to LED2 = FPGA pin
P7, and “F3” to LED3 = FPGA pin P6.

Synthesize, Implement, and generate the programming file.

Load the “main.bit” file into your FPGA
Task 6.
Use switches SW2 (=A), SW1 (=B), and SW0 (=C) to select each of the 8 input combinations and
record the outputs in the “F1”, “F2”, and “F3” columns of Table 1 by observing LED1, LED2, and LED3.
Task 7.
YOUR NAME(S)
Take a picture of the switches and LEDs for the input combinations required in Figure 4.
Lab 7: Intro. to a Hardware Definition Language (VHDL)
Page 7 of 11
CEC 222 Digital Electronics Lab
Spring 2015
Figure 4 Picture of LEDs and switches for ABC = 100 (left) and 101 (right)
EXPERIMENT 2.
IMPLEMENTING THE 7-SEGMENT DECODER USING VHDL
In Lab 5 we implemented a 7-segment decoder using the tedious process of designing seven separate
schematics. Herein we will use VHDL to simplify the process.
Step 2.a: Develop VHDL code implementation of a 7-segment display decoder

Open ISE and create a New Schematic Project named “Lab_7_Experiment2”

Add a new source of type Schematic named “main” to the project

Add a new source of type “VHDL Module” named “seven_seg” to the project

Write the VHDL code to implement a 7-segment decoder (see Figure 5) using any of the three methods
from the pre-lab (or any other method you prefer)1.
 Use “w”, “x”, “y”, and “z” as your inputs and “a”, “b”, …, “g” as the outputs.
Question 2. Which method did you choose
and why?
________________________________
______________________________________
______________________________________
______________________________________
SW3
SW2
SW1
SW0
w
x
y
z
4-input
7-output
Logic Block
a
b
…
g
Figure 5 A 4-input / 7-output logic block
1
Refer to your solution for Lab 5 to obtain the logic of a 7-segment decoder and UCF file.
YOUR NAME(S)
Lab 7: Intro. to a Hardware Definition Language (VHDL)
Page 8 of 11
CEC 222 Digital Electronics Lab
Task 8.
Spring 2015
Insert a screenshot of your VHDL code into Figure 6.
Figure 6 VHDL code implementation of a 7-segment display decoder
Step 2.b: Implement the VHDL code and program the FPGA

Select the file “seven_seg.vhd” and under “Design Utilities” click on “Create Schematic Symbol” and add
this symbol to your schematic.

Connect the four inputs to ports named “w”, “x”, “y”, and “z”.

Connect the seven outputs to ports named “a”, “b”, …, “g”.

Add a UCF file named “seven_seg” by making a copy of the “my_7_sef.ucf” file from Lab_5
 You do NOT want the four lines in the middle of “my_7_sef.ucf” which connect to the LED’s (i.e.,
delete those four lines)

In ISE synthesize, Implement, and generate the programming file.

Load the “main.bit” file into your FPGA
Task 9.
Use the switches, SW3 to SW0, to select each of the two input combinations required by Figure
7. For each input combination insert a photo of the switches and 7- segment display into Figure 7.
YOUR NAME(S)
Lab 7: Intro. to a Hardware Definition Language (VHDL)
Page 9 of 11
CEC 222 Digital Electronics Lab
Spring 2015
Figure 7 Photos of 7-segment display and switch inputs for HEX = 1 (left) and A (right)
Report Requirements
Truth table to be completed
Inputs
A
B
C
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Table 1 Truth Table for the Majority Circuit
Outputs
F1 = LED1
F2 = LED2
F3 = LED3
F
(method1)
(method2)
(method3)
0
0
0
1
0
1
1
1
Optional Exercise(s) (+10% Extra Credit)
EXPERIMENT 3.
REALIZE A 4:1 MUX WITH VHDL
In this extra credit section you will be using VHDL code to realize a 4:1 MUX.
Step 3.a: Develop VHDL code implementation of a 4:1 MUX

Open ISE and create a New Schematic Project named “Lab_7_Experiment3”
YOUR NAME(S)
Lab 7: Intro. to a Hardware Definition Language (VHDL)
Page 10 of 11
CEC 222 Digital Electronics Lab

Spring 2015
Write the VHDL code to implement a 4:1 MUX.
Task 10.
Insert a screenshot of your VHDL code into Figure 6.
Figure 8 VHDL code implementation of a 4:1 MUX
Reference Material
APPENDIX A: XILINX ISE DESIGN SUITE INFORMATION
[1] Digilent Basys2 Board Reference Manual
YOUR NAME(S)
Lab 7: Intro. to a Hardware Definition Language (VHDL)
Page 11 of 11