Experiment 9
Digital Alarm System
Experiment 8: Random Notes
• Timing diagrams need to be annotated
– it’s not the reader’s job to figure out what is going on or what
is important
• Don’t forget circuit diagrams
– circuits you designed/experimented with
– answers to questions
• Take more space: use blank lines in code and in
experiment write-up
Instructional Objectives:
• Using VHDL behavioral modeling in the
design of a Finite State Machine (FSM)
• To combine previously designed VHDL
modules into a complete digital alarm system
using structural modeling
Finite State Machine
•A Finite State Machine (FSM) is a digital circuit whose
state changes based on both the current state (of the
FSM) and the current inputs
•The outputs of a FSM are functions of the current state
(Moore Model) --or-- functions current state and current
inputs (Mealy Model)
•Synchronous FSMs change their state with respect to a
clock input and maintain their state (store their state) in
flip-flops
FSM Models
Standard Architecture
VHDL Behavioral Model
VHDL Behavioral Models for FSM
VHDL Dependent PS/NS Architecture:
Y’s
External Control
(CLR, En, PRE)
• State Memory
• Clock Edge
Synchronization
• Ext. Controls
(clr, en, preset)
•Next State
Sequencing
•Output
Decoder
Z’s
X’s
Dependent PS / NS Coding Style: (2 Processes)
– Synchronous Process
• Clocking / Control (clears, enables, presets)
– Combinatorial Process
• Next State Sequencing
• Output Decoding Logic
Ref: Low-Carb VHDL Tutorial
CPE 169 Experiment 9
Experiment 9 Overview
P1: Finite State Machine Design
1. Using Your State Transition Diagram & PS/NS Table
2. Using the “Dependent PS/NS” VHDL Architecture
3. Simulate to Verify (Test Cases?)
P2: Digital Alarm System
–
–
–
Integrate earlier modules into a working system
Verify the complete system (instructor signoff)
Detailed schematic!!