UWB4SN: Workshop on UWB for Sensor Networks
Lausanne, 2005, Nov 4th
Energy Detection UWB Receiver
Design using a Multi-resolution
VHDL-AMS Description
Mario Casu, Mariagrazia Graziano
VLSI Lab - Dip. Elettronica
POLITECNICO DI TORINO
Lausanne 11/4/05, UWB4SN
Outline
Why Energy Detection Receiver?
Why should I use VHDL-AMS?
How does the receiver work?
How do I simulate it?
Some answers…
Ongoing work
Conclusions
Lausanne 11/4/05, UWB4SN
Why ED Receiver?
 Applications: WPAN with localization capabilities, low
power constraints, moderate (low) data-rate
 Match IEEE 802.15.4a objectives
 UWB impulse based enabling technology
 Coherent receivers aren’t low power nor low complexity
 indoor multipath ~100 replicas = ~100 Rake fingers?
 need Nyquist sampling… ~10 GHz low power?
 …or need analog template (impulse response) = simple?
 Energy Detection is (relatively) simple
 Square, Integrate & Dump, Sample (at pulse repetition rate!)
 Trade performance with simplicity
 GOAL: CMOS technology fully integrated ED receiver
Lausanne 11/4/05, UWB4SN
Energy Detection: example
2 PPM modulation, including white noise and multipath
0
0
1
0
1
( · ) 2 and integrate in proper windows
0
0
10.3
0
3.4
max
0
1
1
9.7
0
3.4
max
0
1
3.4
0
10.5
max
1
1
0
6.8
0
1
3.4
max
1
0
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3.4
0
9.1
max
1
1
Transceiver architecture
Pulse Gen
Mod &
Coding
Channel
Coding
MAC
PROC
BP
Filter
LNA
( )2
dt & H
Demod &
Decoding
N-bit ADC
CCA
Power
Management
Unit
CTRL
SYNCH
RANGING
RECEIVER BLOCKS
RF
Analog
Lausanne 11/4/05, UWB4SN
Mixed
Digital
Why VHDL-AMS?
 The receiver contains RF, analog, digital and
mixed blocks
 A powerful co-simulation environment (e.g.
ADMS™) enables simultaneous simulation of
 VHDL (digital)
 VHDL-AMS (analog/mixed)
 Spice (circuit level)
 Approach followed in this work:
1.
2.
3.
4.
Build a behavioral system using VHDL and VHDL-AMS
Check consistency w. higher level simulation (Matlab)
Refine the description using more accurate models
Substitute analog and mixed blocks with Spice
transistor-level models
Lausanne 11/4/05, UWB4SN
Example: LNA
entity LNA is
Mod &
Channel
Pulse
Gen
port (
Coding
Coding
terminal input, output: electrical);
end LNA;
BP
Filter
MAC
PROC
architecture behavioral of LNA is
( )2
LNA
dt & H
N-bit ADC
Demod &
Decoding
begin
Power
Management
Unit
CCA
SYNCH
RANGING
RECEIVER BLOCKS
end behavioral;
CTRL
RF
Analog
Lausanne 11/4/05, UWB4SN
Mixed
Digital
Example: LNA
entity LNA is
Mod &
Channel
Pulse
Gen
port (
Coding
Coding
terminal input, output: electrical);
end LNA;
BP
Filter
LNA
architecture behavioral of LNA is
Demod &
quantity
vin
to ADC
electrical_ref;
( )2
dtacross
& H input
N-bit
Decoding
quantity vout across iout through output
to electrical_ref;
begin
CCA
vout == vin
* gain;
Power
SYNCH
Management
Unit
RECEIVER BLOCKS
end behavioral;
CTRL
MAC
PROC
RF
RANGING
Analog
Lausanne 11/4/05, UWB4SN
Mixed
Digital
Example: LNA
entity LNA is
Mod &
Channel
Pulse
Gen
port (
Coding
Coding
terminal input, output: electrical);
end LNA;
BP
Filter
MAC
PROC
architecture behavioral of LNA is
Demod &
quantity
vin
to ADC
electrical_ref;
( )2
dtacross
& H input
N-bit
LNA
Decoding
quantity vout across iout through output
to electrical_ref;
begin
CCA
if (abs(vin'Ltf(num,den)*gain+vos) < vsat) use
vout == vin'Ltf(num,den)*gain+vos;
Power
SYNCH
RANGING
else
-saturation
Management
vout == vsat *sign(abs(vin'Ltf(num,den)*gain+vos);
Unit
RECEIVER BLOCKS
end use;
end behavioral;
CTRL
RF
Analog
Lausanne 11/4/05, UWB4SN
Mixed
Digital
Matlab vs VHDL-AMS
No loss in accuracy
Simple 2-PPM
with Channel
Model IEEE
802.15.3a
Matlab
CPU Time:
MATLAB
VHDL-AMS-1
VHDL-AMS-2
1
16.2
1.53
Lausanne 11/4/05, UWB4SN
VHDL-AMS-1
continuous-time
VHDL-AMS-2
discrete-time
How does the receiver work?
1.
Listen to channel, measure noise energy (in Tbit) and
set noise threshold Nth
2. If channel energy (in Tbit) < Nth then goto 1, else
1. Adjust gain
2. Coarse synchronization
3. Concurrent demodulation and fine synch
4. If Two-Way-Ranging (TWR) command, prepare for
packet reply
5. Send coarse & fine synch info in replied packet
payload
Lausanne 11/4/05, UWB4SN
Clear Channel Assessment
input
LNA
( )2
dt & H
N-bit ADC
Demod &
Decoding
CCA
CTRL
SYNCH
Lausanne 11/4/05, UWB4SN
RANGING
Noise Estimation
Integrate CK from Synch
strobe from CTRL
Noise Integrated and Dumped
NOISY (INPUT)2 ADC output
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Preamble Detection
strobe from CTRL
ADC output
Integrate CK from Synch
Non-modulated (INPUT)2 (INPUT)2 integrated and dumped
Lausanne 11/4/05, UWB4SN
Gain Adjustment
1111
0111
LUT
VGA
LNA
( )2
dt & H
4-bit ADC
gain 0
Demod &
gain 1
Decoding
CCA
gain 7
DAC
SYNCH
RANGING
gain 15
CTRL
Lausanne 11/4/05, UWB4SN
Synchronization






~ IEEE 802.15.4 packet
Simple 2 PPM : 1 pulse/symbol
Non modulated preamble is used for coarse synchronization
Must finish before Start of Frame Delimiter (SFD)
When locked, Fine Synchronization starts
Extends over non modulated pulses
4 bytes
1
1
variable length
preamble
SFD
FL
payload
data
coarse
Locked!
fine
Lausanne 11/4/05, UWB4SN
Synchronization of 2-PPM signal
Non-modulated preamble: ( · ) 2 and integrate with a sliding window
0
3.4
t0
0
9.7
t0+dt
0
0
10.5
t0+2dt
max
0
0
6.8
6.0
4.5
t0+3dt
t0+4dt
t0+5dt
SYNCH TIME: t0+2dt
Fine synch similar with finer increment step around coarse lock point
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Coarse Synch simulation
ADC output
Incremental delay
System CK Integrate Strobe
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Demodulation
1 1 1 0 0 1 0 1 0 0 0 0 1 0 1 0
Start of Frame Delimiter
Frame Length = 10 Bytes
1 1 1 0 0 1 0 1 0 0 0 0 1 0 1 0
Lausanne 11/4/05, UWB4SN
Putting it all together
(INPUT)2
(Noise)2
Gain Set
Synch Search
SFD
Preamble Detect
Noise Estimate
Lausanne 11/4/05, UWB4SN
Lessons learned
 Ideal simulations show system functionality
 Problems arise when simulating effects like saturation
and limited A/D resolution
 Need for a reliable AGC. Example:
 Given pulse energy and A/D N-bit, gain too low leads
to bad synch (impossible to resolve integrated signal)
 Gain too high leads to saturation: Same problem!
 Ranging requisites stricter in terms of A/D resolution
 OK 4 bits for coarse synch & demod
 1 more bit for fine synch and thus ranging
Lausanne 11/4/05, UWB4SN
Ongoing Work
Transmitter design
~1ns
Almost digital operation
Found sequence of pulses that best matches
FCC/ETSI mask
Two Way Ranging Simulation
Old 802.15.3a CM used
Preliminary results show ~ns accuracy
Lausanne 11/4/05, UWB4SN
Conclusions
 Status of the work
1.Build a behavioral system using VHDL and VHDL-AMS
2.Check consistency w. higher level simulation (Matlab)
3.Refine the description using more accurate models
4.Substitute analog and mixed blocks with Spice
transistor-level models
Lausanne 11/4/05, UWB4SN
Conclusions
 Status of the work
1.Build a behavioral system using VHDL and VHDL-AMS
2.Check consistency w. higher level simulation (Matlab)
3.Refine the description using more accurate models
4.Substitute analog and mixed blocks with Spice
transistor-level models
Lausanne 11/4/05, UWB4SN
Conclusions
 Status of the work
1.Build a behavioral system using VHDL and VHDL-AMS
2.Check consistency w. higher level simulation (Matlab)
3.Refine the description using more accurate models
4.Substitute analog and mixed blocks with Spice
transistor-level models
Lausanne 11/4/05, UWB4SN
Conclusions
 Status of the work
1.Build a behavioral system using VHDL and VHDL-AMS
2.Check consistency w. higher level simulation (Matlab)
3.Refine the description using more accurate models
4.Substitute analog and mixed blocks with Spice
transistor-level models
Lausanne 11/4/05, UWB4SN
Conclusions
 Status of the work
1.Build a behavioral system using VHDL and VHDL-AMS
2.Check consistency w. higher level simulation (Matlab)
3.Refine the description using more accurate models
4.Substitute analog and mixed blocks with Spice
transistor-level models
 So far, VHDL-AMS proved to be effective in
managing the design complexity at system
simulation stage
Lausanne 11/4/05, UWB4SN
Conclusions
 Status of the work
1.Build a behavioral system using VHDL and VHDL-AMS
2.Check consistency w. higher level simulation (Matlab)
3.Refine the description using more accurate models
4.Substitute analog and mixed blocks with Spice
transistor-level models
 So far, VHDL-AMS proved to be effective in
managing the design complexity at system
simulation stage
 Next: Tracking IEEE 802.15.4a PHY
Lausanne 11/4/05, UWB4SN
That’s all
Folks…
THANK YOU!
Lausanne 11/4/05, UWB4SN