Chapter 3
• How transistors operate and form simple
switches
• CMOS logic gates
• PLA, PAL, FPGA
• Basic electrical characteristics of logic
circuits
Transistor Switches
• Logic Circuits are built with Transistors
– “A full treatment of transistor behavior is
beyond the scope of this text”
• MOSFETs
– NMOS - nchannel
– PMOS – pchannel
NMOS vs PMOS
x = "low"
x = "high"
(a) A simple switch controlled by the input x
x = "high"
(a) A switch with the opposite behavior
Gate
Gate
Source
Drain
Substrate (Body)
(b) NMOS transistor
Drain
Source
Substrate (Body)
VDD
(b) PMOS transistor
VG
VG
VS
x = "low"
VD
(c) Simplified symbol for an NMOS transistor
VS
VD
(c) Simplified symbol for a PMOS transistor
NMOS & PMOS in Logic Circuits
VD
VD = 0 V
VD
VG
VS = 0 V
Closed switch
whenVG = VDD
Open switch
whenVG = 0 V
(a) NMOS transistor
VS = VDD
VDD
VDD
VD
VD
VD = VDD
VG
Open switch
whenVG = VDD
(b) PMOS transistor
Closed switch
whenVG = 0 V
NMOS Inverter
VDD
R
5V
R
+
Vf
-
Vf
Vx
Vx
(a) Circuit diagram
x
(b) Simplified circuit diagram
f
x
(c) Graphical symbols
f
NMOS NAND vs AND
VDD
VDD
VDD
Vf
Vx
Vx
Vf
1
A
2
(a) Circuit
x1 x2
f
0
0
1
1
1
1
1
0
0
1
0
1
Vx1
Vx2
x2
f
0
0
1
1
0
0
0
1
0
1
0
1
(b) Truth table
(b) Truth table
(a) Circuit
x1
x1 x2
f
x1
x2
(c) Graphical symbols
f
x1
x2
f
x1
x2
(c) Graphical symbols
f
NOR and OR
V DD
Vf
V
x
Vx
1
2
x2
f
0
0
1
1
1
0
0
0
0
1
0
1
What would an
OR gate look
like?
(b) Truth table
(a) Circuit
x1
x1 x2
f
x1
x2
(c) Graphical symbols
f
SN7408 - QUADRUPLE 2-INPUT POSITIVE-AND GATES
What’s Wrong With this Picture?
VDD
R
Vf
Vx
When Vx is high there is a constant current
through R
Structure of an
NMOS Circuit
V DD
VDD
Vf
Vx
Vx
1
2
Vf
Vx
Vx
1
Pull-down network
(PDN)
n
Structure of a
CMOS circuit
V DD
Pull-up network
(PUN)
Vf
Vx
Vx
1
Pull-down network
(PDN)
n
VDD
T1
V DD
Vx
T1
Vf
T2
T2
Vf
Vx
Vx
T3
1
T4
2
(a) Circuit
x1 x2
T1 T2 T3 T4
f
0
1
0
1
on on off off
on off off on
off on on off
1
1
1
0
0
0
1
1
off off on on
(b) Truth table and transistor states
V DD
V DD
Vf
Vx
1
Vx
2
V DD
V DD
Vf
Vx
1
Vx
2
Vf
Vf = X1X2 = X1 + X2
Vf = X1X2
PUN = Vf
PDN = Vf
f = X1 + X2X3
V DD
Vf
Vx
1
Vx
2
Vx
3
Types of Integrated Circuits
• Standard Logic
• Programmable Logic
• Custom Logic
7400 Series Standard Chips - random logic
DD
V
7404
7408
x1
x2
x3
7432
f
= x 1 x2 + x2 x3
Standard Logic
• Seldom used – with exception of buffers
• SSI
– Earliest devices only a few logic gates/transistors
• MSI
– 10 to100 gates
• LSI
– Greater than MSI
• VLSI
PLDs – Programmable Logic Devices
•
•
•
•
•
•
•
•
PLA – Programmable Logic Array
SPLDs
PAL – Programmble Array Logic
CPLD – Complex PLD
FPGA – Field Programmable Gate Arrays
Custom Chips
ASIC – Application Specific Integrated Circuit
Gate Arrays
Memory
}
PLA – Programmable Logic
Array
• Based on the idea that logic functions can
be realized in SoP form
• “Modest” size circuits
– Inputs & Outputs of not more than 32
x1
x2
x3
Programmable
connections
OR plane
P1
P2
P3
P4
AND plane
f1
f2
x1
x2
x3
Programmable
connections
OR plane
P1
P2
P3
P4
f1 = x1x2 + x1x3 + x1x2x3
f2 = x1x2 + x1x2x3 + x1x2
AND plane
f1
f2
x1
x2
x3
OR plane
P1
P2
P3
P4
AND plane
f1
f2
PAL – Programmble Array Logic
• PLA’s Programmable Fuses
– Fabrication difficult
– Fuses slow down circuit
• PALs
– Only AND plane is programmable
– OR plane is fixed
• “Modest” size circuits
– Inputs & Outputs of not more than 32
x1
x2
x3
P1
f1
P2
P3
f2
P4
AND plane
PAL Macrocell
Select
Enable
f1
Flip-flop
D
Clock
To AND plane
Q
CPLD – Complex PLD
• Multiple Circuit blocks on a single chip
• Each circuit block similar to PAL or PLA
• Typical CPLDs
– 16 Macro cells in each PAL like block
– 5 to 20 inputs to each OR gate
– 2 to more than 100 PAL like blocks
I/O block
PAL-like
block
I/O block
PAL-like
block
PAL-like
block
PAL-like
block
I/O block
I/O block
Interconnection wires
Structure of a complex programmable logic device (CPLD).
PAL-like block (details not shown)
PAL-like block
D Q
D Q
D Q
A section of a CPLD
Note how output pin
can be used as an input
pin but associated
macrocell cannot be
used – some CPLDs
include additional
wiring to get around this
limitation
Equivalent Gates
• Two input NAND gate used as measure of
circuit size
• SPLD, CPLD macrocell = 20 Equivalent Gates
• PAL with 8 Macrocells can hold circuit of
about 160 EG
• CPLD with 500 macrocells can hold circuit
of about 10,000 EG
• Today’s logic circuits demand circuits
greater than 10,000 EG
Memory as Logic
How Memory Works
•Supply address
•Get Data
Address
Data
Memory as Logic
Consider an 8 location memory chip
with one binary bit at each location
•How many bits to address a location?
•How many bits at each location?
Address
Data
Memory as Logic
A2 A1 A0
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Data
0
0
0
1
0
1
0
0
Address
Data
f= A2A1A0 + A2A1A0
What would you name this?
FPGA – Field Programmable
Gate Arrays
•
•
•
•
•
•
Quite different from SPLDs and CPLDs
FPGAs don’t have AND or OR planes
Logic blocks – most common are LUTs
I/O blocks
Interconnection wires
Greater than 1M EG
x1
0/1
0/1
f
0/1
0/1
x2
(a) Circuit for a two-input LUT
x1 x2
f1
0
0
1
1
1
0
0
1
0
1
0
1
(b) f 1 = x 1 x 2 + x 1 x 2
x1
1
0
0
1
x2
(c) Storage cell contents in the LUT
f1
x1
x2
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
x3
A three-input LUT.
f
Select
Out
Flip-flop
In1
In2
D
LUT
Q
In3
Clock
Inclusion of a flip-flop in an FPGA logic block.
x3
f
x1
x1
x2
x2
0
0
0
1
f1
x2 0
1
0
x3
0
f2
f1 0
1
1
f2
1
f
A section of a programmed FPGA.
Custom Chips, Standard Cells, &
Gate Arrays
• Programmable switches
– Size issue
– Speed issue
Custom Chips
• Complete flexibility in transistor placement
and connection
• Large design effort
• Large cost
• Large quantities
ASICs
Application Specific Integrated Circuits
• Standard Cell Libraries
• Configurable connections
Gate Arrays
• Gates prefabricated
• Connections added later
In-System Programming
vs
?
Out of System Programming
•Compare Teensy++ to ATtiny261
Programming
• PALs & PLAs usually programmed out of
systems
• CPLDs usually programmed via JTAG insystem
• FPGAs programmed via JTAG in-system
• PALs, PLAs, & CPLDs nonvolatile
• FPGAs volatile
Practical Aspects
• Transistor Operation
• Static Operation - Voltage Levels
• Dynamic Operation – Transition Times
• Power Dissipation
ID
Triode
0
V GS – V T
Saturation
VDS
The current-voltage relationship in the NMOS transistor.
VD
VD
VG
VS = 0 V
Open switch
whenVG = 0 V
VD
VD = 0 V
VG
VS = 0 V
Closed switch
whenVG = VDD
Logic Values as Voltage Levels
Logic Value 1
VOH
High Noise Margin VOH – VIH
VIH
VIL
VOL
Low Noise Margin VIL - VOL
Logic Value 0
Dynamic Operation
• Ideal gates
– Switch immediately in response to a change in
inputs
– Transition logic states in zero time
• We don’t live in an Ideal World
VDD
Vx
50%
50%
Gnd
Propagation delay
Propagation delay
VDD
90%
VA
90%
50%
Gnd
50%
10%
10%
tr
tf
Rise Time
Fall Time
Power Dissipation
• Static power consumption
• Dynamic power consumption
Static Power Consumption
VDD
VDD
T1
R
Vf
Vx
Vx
Vf
T2
Dynamic Power Consumption
VDD
Vx
ID
Vf
Vx
ID
Vf
Fan-in Fan-out
• Fan-in
– Number of inputs to the gate
– No choice really
• Fan-out
– Number of inputs being driven
– Increase in capacitance slows down rise time
– Increase in load changes DC levels
Buffers
• Non-inverting
• Inverting
• Tri-state
e
e
f
x
f
x
(a)
(b)
e
e
f
x
f
x
(c)
(d)
Tri-state buffers
Reading
• Chapter 3
Laboratory Preparation
• None
Homework Problems
• For SN74HCT00N and MM74HCT00N
– Calculate Noise Margins
– Find rise and fall times
– Find propagation delay
• some datasheets show this as tt
– Compare the two datasheets