ECE 331 – Digital System Design
Transistor Technologies,
and
Realizing Logic Gates using CMOS Circuits
(Lecture #23)
Transistor Technologies
Two transistor technologies:
1. Transistor-Transistor Logic (TTL)
2. Metal Oxide Semiconductor (MOS)
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TTL Technology




TTL = Transistor-transistor Logic
Dominant technology prior to the emergence of
CMOS technology.
Not as suitable for large-scale integration as
CMOS technology.
Largely obsolete for new designs.

Good for labs and educational use because it
is more robust than CMOS.
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TTL Technology



Bipolar Junction Transistor (BJT)

Base – controls current flow in transistor

Collector – current flow enters transistor

Emitter – current flow exits transistor
npn BJT

Collector, Emitter: n-type semiconductor

Base: p-type semiconductor
pnp BJT

Collector, Emitter: p-type semiconductor

Base: n-type semiconductor
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MOS Technology

CMOS


NMOS


N-channel MOSFET
PMOS


Complementary Metal Oxide
Semiconductor
P-channel MOSFET
MOSFET

Metal Oxide Semiconductor Field Effect
Transistor
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NMOS Transistor
x = "low"
x = "high"
(a) A simple switch controlled by the input x
Gate
Source
Drain
Substrate (Body)
(b) NMOS transistor
VG
VS
VD
(c) Simplified symbol for an NMOS transistor
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NMOS Transistor

Four-terminal device




Simplified three-terminal representation
Conducting channel is N-type material
Drain pulled high (connected to supply voltage)
in digital circuits
Source pulled low (connected to ground) in
digital circuits
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NMOS Transistor

Gate-to-Source Voltage (VGS)


Controls the drain current (iD) via an electric
field
Oxide (silicon dioxide) insulates the gate from
the drain and the source

iG ~= 0 Amps

iD ~= iS

Low power
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NMOS Transistor

Operates as a binary switch in digital circuits

VG = 0V
(VS = GND = 0V)

VGS ~= 0V

“looks like” an open switch (in the cutoff region; “off”)


ID = IS = 0A
VG = VDD
(VS = GND = 0V)

VGS ~= VDD

“looks like” a closed switch (in the saturated region;
“on”)
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PMOS Transistor
x = "high"
x = "low"
(a) A switch with the opposite behavior of the NMOS transistor
Gate
Drain
Source
VDD
Substrate (Body)
(b) PMOS transistor
VG
VS
VD
(c) Simplified symbol for a PMOS transistor
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PMOS Transistor

Four-terminal device




Three-terminal simplified representation
Conducting channel is P-type material
Drain pulled low (connected to ground) in digital
circuits
Source pulled high (connected to supply
voltage) in digital circuits
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PMOS Transistor

Gate-to-Source Voltage (VGS)


Controls the drain current (iD) via an electric
field
Oxide (silicon dioxide) insulates the gate from
the drain and the source

iG ~= 0 Amps

iD ~= iS

Low power
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PMOS Transistor

Operates as an binary switch in digital circuits

VG = 0V

(VS = VDD = Supply Voltage)

VGS ~= -VDD

“looks like” an closed switch (in the saturated region;
“on”)
VG = VDD
(VSG ~= VDD)
(VS = VDD = Supply Voltage)

VGS ~= 0V

“looks like” a open switch (in the cutoff region; “off”)

(VSG = 0V)
ID = IS = 0A
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NMOS and PMOS Transistors
VD
VD = 0 V
VD
VG
VS = 0 V
Closed switch
when VG = VDD
Open switch
when VG = 0 V
(a) NMOS transistor
VS = VDD
VDD
VDD
VD
VD
VD = VDD
VG
Open switch
when VG = VDD
Closed switch
when VG = 0 V
(b) PMOS transistor
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CMOS Logic Circuit
V DD
Pull-up network
(PUN)
PMOS transistors
Vf
Vx
Vx
1
Pull-down network
(PDN)
NMOS transistors
n
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Voltage Levels in CMOS Circuits
Voltages are used to represent Logic values in
CMOS (and TTL) circuits:
Logic 1 = VDD
Logic 0 = GND
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Voltage Ranges in CMOS Circuits
Voltage
V DD
Logic value 1
V 1,min
Undefined
V 0,max
Logic value 0
V SS (Gnd)
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CMOS Logic


Beneficial to use NMOS and PMOS in same design

No steady state drain (or gate) current

Low power dissipation
Configuration of NMOS and PMOS transistors


For Output of CMOS circuit = Logic 0

PDN (NMOS transistors)
ON

PUN (PMOS transistors)
OFF
For Output of CMOS circuit = Logic 1

PDN (NMOS transistors)
OFF

PUN (PMOS transistors)
ON
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CMOS Circuit: Inverter (NOT)
V DD
T1
Vx
Vf
x
T1 T2
f
0
1
on off
off on
1
0
T2
(b) Truth table and transistor states
(a) Circuit
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CMOS Circuit: NAND Gate
VDD
T1
T2
Vf
Vx
T3
1
Vx
T4
2
(a) Circuit
x1 x2
0
0
1
1
0
1
0
1
T1 T2 T3 T4
f
on on offoff
on offoff on
off on on off
1
1
1
0
offoff on on
(b) Truth table and transistor state
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CMOS Circuit: NOR Gate
VDD
Vx
T1
Vx
T2
1
2
Vf
T4
T3
(a) Circuit
x1 x2
0
0
1
1
0
1
0
1
T1 T2 T3 T4
f
on on off off
on offoff on
off on on off
1
0
0
0
offoff on on
(b) Truth table and transistor state
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CMOS Circuit: AND Gate
VDD
VDD
NAND Gate
Inverter
Vf
Vx
1
Vx
2
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CMOS Circuit: OR Gate
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CMOS Circuits
Analysis
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CMOS Circuits: Analysis
The functional behavior of a CMOS circuit can be
determined by analyzing the behavior of the
individual PMOS and NMOS transistors, and,
thus, the behavior of the PUN and PDN.
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CMOS Circuits: Analysis (Steps)
• Determine the state of each transistor for each
input combination.
• Determine the output of the CMOS circuit for
each input combination.
• Derive the corresponding Truth Table
• Determine the Boolean Expression that defines
the behavior of the CMOS circuit.
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CMOS Circuits: Analysis
Example #1:
Analyze the following CMOS circuit to determine
the logic function that it implements.
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CMOS Circuit: Analysis (Ex. #1)
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CMOS Circuits: Analysis
Example #2:
Analyze the following CMOS circuit to determine
the logic function that it implements.
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CMOS Circuit: Analysis (Ex. #2)
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