EECS 373 Midterm
Fall 2009 Solutions revised 11/7
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Scores:
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Points
1
2
3
4a
4b
/?
/?
/?
/?
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Design
Part 1
Part 2
Total
/?
/?
/100
NOTES:
1.
2.
3.
4.
5.
6.
Open 373 reference manual and the complex branch handout only.
There are
pages including this one.
Calculators are allowed, but no PDAs, Portables, Cell phones, etc.
Don’t spend too much time on any one problem.
You have about 80 minutes for the exam.
Be sure to show work and explain what you’ve done when asked to do so. Getting
partial credit without showing work will be rare.
Spend your time wisely. In particular, be sure to try all 2 parts of the design problem.
Page 1 of 15
Fill-in-the-blank/multiple choice. [? points, -? for each wrong or blank answer]
a) A 40kHz clock with a 20% duty cycle is high for ________5________ us.
b) A 1 Mbit square memory with 15 address lines would output 2 / 4 / 8 / 16 / 32 / 64
bits of data in a given read. The row decoder would have ____10_____ inputs while
the MUX selector would have _____5____ inputs.
c) It is necessary to set the EE bit of the MSR to 1 before executing an RFI to enable the
interrupts. True / False
d) If R0 = 0x12345678 then addi. R2, R0, 0xffff will result in what value in R2?
_____xffffffff_____ negative 1
e) If the top 2 bytes of SIPEND were 0xA101 and the top 2 bytes of SIMASK were 0x5323,
then the value in SIVEC would be _____00011100____1C . LVL3 and IRQ7 not masked,
so LVL3 highest priority
f) Say the top 2 bytes of SIPEND were 0xC314, and the top 2 bytes of SIEL were 0x8023. If
we wrote 0xFF00 to the top 2 bytes of SIPEND, what would be the value in SIPEND after
that write? _________0x4314__________. (answer in hex) resets only IRQ0
g) An ABI compliant function uses R3, R4, R5, R31 and does not have any conditional
statements. How many WORDS are required for the local stack frame? 2 / 3 / 4 / 5 / 6
Back chain, LR reserve, pad R31
h) If you trigger the logic analyzer on the address 0x29xxxxx where x is don’t care, how
many times will you see TA* on the logic analyzer when you execute the instruction sth
r4, 1(r3) where r3 = 0x2900001? ______1_______
i) When addressing internal device memory mapped registers such as the UART registers, it
is necessary to get the base address from the ______IMMR______register first.
j) Consider the instruction ori r2, r3, n, where n is an immediate. __216-1__ or
0xffff
is the maximum value n can take.
Page 2 of 15
Design a device which takes an input clock of 1Khz and outputs a 200Hz clock
with a 40% duty cycle. You may use n bit binary counters, D or JK flipflops with synchronous
reset. You may express combinational logic as a Boolean expression or use standard logic
symbols. Label and write clearly.
Generalized Solution
Q0-2
3 bit Counter
Q0
< 2 counts
Out =Q0&~Q1&~Q2 |
~Q0&Q1&~Q1
D Flip Flop
D
1kz
> CLK
Q1
Q0-2
Q2
1kz
>CLK
SYN RESET
1khz/5 = 200hz 
=needs to count 5
Out = Q0*Q1 //4 counts
Note: one more count is used
for the sync reset
5ms period
40% duty cycle  2/5 period high 2ms
Or high for 2 counts or low for 3 counts
000 count 0
001 count 1
010 count 2
011 count 3
100 count 4
Page 3 of 15
JK solution
Page 4 of 15
1. Short answer [? points]
a. Consider the PowerPC assembly found below. Assume that r3=0x0x11223344,
r1=0x1000, r4 = -8 and all other registers and memory locations are initialized to zero.
stwu r3, 3(r1)
lbz r5,0(r1)
andi r5, r5, 0xF
sthux r3, r1, r5
sthux r3,r1,r4
lwz r3, 0(r1)
What are the values of these registers? You must write your answers as 8-digit hex
numbers if you wish to receive credit! [8, 2 each]
i. R1=__________0xfffc___________
ii. R3=__________0x3344___________
iii. R4=__________-8___________
iv. R5=___________0x1__________
init
stwu r3, 3(r1)
lbz r5, 2(r1)
R1
0x1000
0x1003
0x1003
R3
0x11223344
0x11223344
0x11223344
R4
-8
-8
-8
R5
0
0
0x11
0xfffc
0
0
0
0x1000
0
0x00000011
0x00000011
0x1004
0
0x22334400
0x22334400
andi r5,r5,0xF
0x1003
0x11223344
-8
0x1
0
0x00000011
0x22334400
sthux r3,r1,r5
0x1004
0x11223344
-8
0x1
0
0x00000011
0x33334400
sthux r3,r1,r4
0xfffc
0x11223344
-8
0x1
0x33440000
0x00000011
0x33334400
lwz r3,0(r1)
0xfffc
0x3344
-8
0x1
0x33440000
0x00000011
0x33334400
Page 5 of 15
Complete the bus transaction information for the following instructions. If the value is unknown,
use ---. Assume R3 = 0x2900000 and R4 = 0x01234567. Memory location 0x2900000 =
aabbccdd. There may be more cycles shown then required. Assume zero wait state. [? points]
CLK
TS*
RDWR*
ADDR[6:31]
TSIZ[0:1]
DATA[0:31]
TA*
T0
T1
T2
T3
Complete the following table for stw r4, 3(r3)
T0
T1
T2
0
1
0
TS*
1
0
1
TA*
0x2900003
0x2900003
0x2900004
ADDR
TSIZ
RDWR*
DATA
01
0
0101--01
01
0
0101--01
10
0
2345-----
Complete the following table for lwz r4, 2(r3)
T0
T1
T2
0
1
0
TS*
1
0
1
TA*
0x2900002 0x2900002 0x2900004
ADDR
10
10
1
1
aabbccdd
aabbccdd
----ccdd
----ccdd
----cc01
----cc01
290000 aabbcc01 or aabbccdd
290004 23456700 or 00000000
TSIZ
RDWR*
DATA
10
1
00000000
0000---2345----
T4
T5
T3
1
0
0x2900004
T4
0
1
0x2900006
T5
1
0
0x2900006
10
0
2345-----
01
0
67--67--
01
0
67--67--
T4
T5
T3
1
0
0x2900004
10
1
00000000
0000---2345----
Page 6 of 15
Consider an ABI compliant function that uses the following registers: R0-R5, R30-R31, condition
register fields CRF0 – 3 and has a local array: int myarray[2]. Write the epilog for this function,
which is the part that creates the stack frame and stores the relevant registers. You must include a
table that shows the contents (register or generally stated) of the stack frame you are writing the
epilog for. All constants should be expressed in DECIMAL!
prolog
mflr r0
stw r1, 4(r1)
stwu r1, -32(r1)
stw r31, 28(r1)
stw r30, 24(r1)
stw r2, 20(r1)
mfcr r31
stw r31, 20(r1)
epilog
lwz r0, 36(r1)
mtlr r0
lwz r31, 28(r1)
lwz r30, 24(r1) //or lmw r30, 24(r1)
lwz r2, 20(r1)
lwz r5, 20(r1)
mtcr r5
addi r1, r1, 32
blr
8, 0x8, etc
36, 0x24, this func LR
32, 0x20, Back Chain
R1
28, 0x1C, R31
24, 0x18, R30
20, 0x14, R2
16, 0x10, CR
12, 0xC, Myarray[1]
8, 0x8, Myarray[0]
4, 0x4, Reserve LR
0, 0x0, Back Chain R1
4 bytes x 8 = 32
Page 7 of 15
Design Problem
Background
You are given the task of developing the hardware and software interface to a linear actuator. The
actuator can move a mounting platform roughly 1 meter in increments of 0.001 meters in either direction.
All interfacing to the actuator is via the actuators embedded controller.
Actuator Hardware Interface
The actuators embedded controller does all the detail work of sensing and moving the platform. To
control the linear actuator, you must be able to read 1, 8 bit control register and write 1, 16 bit control
register. The proposed data path between the controller registers and the power pc is illustrated below.
BUS CLK
TS*
AH 6-11
AL 24-31
RDWR*
External Bus
Controller
Actuator
Controller
TSIZE 0-1
PD_OUT_EN
Read Control (REN)
TA
Data Read Path (D24-31)
Power PC
External
Bus
Interface
8 Bit
Read
Only
Status
Register
Linear
Actuator
Write Control (WEN)
Data Write Path (D16-31)
BUS CLK
16 Bit
Write
Only
Distance
and
Direction
Register
W CLK
Page 8 of 15
Data Path and Control Assumption:
1. The registers are D style flip-flops like the ones we used in the lab 3.
2. The WEN (write enable, active high) enables the BUS CLK (write clock) to write the
Distance/Direction register.
3. The REN (read enable, active high) enables an internal tri-state buffer in the read register data
path.
4. A zero wait state response will accommodate all propagation and setup/hold time requirements.
5. The Status register should be a read only, byte addressable register. Assume the read data path is
connected to D24-31 of the PPC data path.
6. The Distance/Direction register is a write only, ½ word addressable register. Assume the write
data path is connected to D16-31 of the PPC data path.
7. The word aligned address for both registers is 0x2800000.
Part 1: External Bus Controller Design [? Points]
Provide the bus controller logic to read and write the actuator control registers on the following pages.
1. You may provide the logic in schematic, Verilog or a combination of both.
2. You may use standard gates and D style flip-flops for schematic form.
3. It will not be necessary to perfect Verilog syntax; however, your Verilog must:
a. be logically correct
b. provide correct module porting
c. provide data variable types (wire, reg).
4. Provide your logic on the following pages using these port names .
BUS_CLK
TS*
TA*
AH[6-11]
AL[24-31]
RDWR*
TSIZE[0-1]
External Bus
Controller
REN
WEN
PD_OUT_EN
Page 9 of 15
Provide Your External Bus Controller Logic Here
BUS_CLK
TS*
TA*
AH[6-11]
AL[24-31]
RDWR*
TSIZE[0-1]
External Bus
Controller
REN
WEN
PD_OUT_EN
module bus_controller(
input BUS_CLK,TS_BAR,RDWR_BAR,
input [6:11]AH,
input [24:31]AL,
input [0:1]TSIZE,
output reg TA_BAR, PD_OUT_EN, WEN, REN);
reg Q0TA, Q0REN, Q0WEN, TA_BAR_Decode, REN_Decode, WEN_Decode;
always@*
begin
if (AH == 6'h28 && ~TS_BAR) TA_BAR_Decode = 1; //TA generation for both read and write cycles
else TA_BAR_Decode = 0;
if (AH == 6'h28 && AL == 3 && ~TS_BAR && RDWR_BAR && TSIZE == 01) REN_Decode = 1; //read specific control
else REN_Decode = 0;
if (AH == 6'h28 && AL == 2 && ~TS_BAR && ~RDWR_BAR && TSIZE == 10)WEN_Decode = 1; //write specific control
else WEN_Decode = 0;
PD_OUT_EN = REN;
end
always@ (posedge BUS_CLK)
begin
Q0TA <= TA_BAR_Decode;
Q0REN <= REN_Decode;
Q0WEN <= WEN_Decode;
end
always@ (negedge BUS_CLK)
begin
TA_BAR <= ~Q0TA;
REN <= Q0REN;
WEN <= Q0WEN;
end
endmodule
Page 10 of 15
Extra Page for External Bus Controller Logic
BUS_CLK
TS*
TA*
AH[6-11]
AL[24-31]
RDWR*
TSIZE[0-1]
External Bus
Controller
REN
WEN
PD_OUT_EN
Page 11 of 15
Part 2: The Device Driver [ ?points]
You will also provide the device driver for the actuator with the following C function prototype.
int actuator(unsigned char distance, unsigned char direction);
The function will be written in assembly and callable as a C function (ABI compliant). The distance the
actuator is to move in inches is passed in as the unsigned char distance. If the distance value exceeds 40
inches, actuator should return the error code -1 as an integer. If there are no errors, actuator should
return the code 0. The direction the actuator is to move is passed in as an unsigned char and coded as a 0
for forward and a 1 for backward.
The distance/direction register distance in 0.0001 meters (mm). Rather than do the calculation in
assembly, you will call a C function that converts the distance in inches to 0.001 meters. You do not have
to write this function. The function has the following prototype:
unsigned short convert(unsigned char distance)
The MSB bit of the distance/direction register determines the direction and follows the coding 0 forward
and 1 backward.
When the direction/distance register is written the actuator will move. Your driver must wait for the
actuator to complete the movement before returning. The actuator will provide a 1 in the LSB of the
status register when then movement is complete. The value is reset to 0 after a distance/direction
register write.
Provide the assembly for the device driver on the following page.
1. Be clear and neat.
2. Providing a high level description, comments and table showing stack frame usage will increase
your chances for partial credit.
3. Assume adequate stack space is provided.
4. Use only the stack frame space required for your function.
5. Feel free to use simplified assembly mnemonics and assembler directives.
Page 12 of 15
Provide the Assembly Code for Your Device Driver Here.
actuator:
mflr r0
stw r0, 4(r1)
stwu r1, -8(r1)
cmpi r3, 40
ble cont
li r3, -1
b exit
cont:
bl convert
cmpi r4, 0
beq cont2
li r4, 0x8000
or r3,r3,r4
cont2: lis r5, 0x28
sth r3, 2(r5)
//save link register on back stack
//even word multiple stack
Stack frame
LR reserve
SP (R1)
//distance greater then 40?
//yes, return(-1)
// convert inches to mm
//direction set for forward?
//no, backup
//add backup bit
//write distance and direction
cont1:
lbz r6, 3(r5)
cmpi r6, 1
bne cont1
//read status register
//actuator done moving or RDY?
lis r3, 0
// return(0)
addi r1, r1, 8
lwz r0, 4(r1)
mtlr r0
blr
//release stack frame
//restore lr
exit:
//return from call with error code
Page 13 of 15
Page 14 of 15
Extra Page For Device Driver Assembly Code
Page 15 of 15