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The Devices Jan M. Rabaey Digital Integrated Circuits Devices © Prentice Hall 1995 Goal of this chapter • Present intuitive understanding of device operation • Introduction of basic device equations • Introduction of models for manual analysis • Introduction of models for SPICE simulation • Analysis of secondary and deep-sub-micron effects • Future trends Digital Integrated Circuits Devices © Prentice Hall 1995 The Diode B A Al SiO2 p n Cross-section of pn-junction in an IC process A Al A p n B B One-dimensional representation Digital Integrated Circuits diode symbol Devices © Prentice Hall 1995 Depletion Region hole diffusion electron diffusion p (a) Current flow. n hole drift electron drift Charge Density + x Distance - Electrical Field (b) Charge density. x (c) Electric field. V Potential -W 1 Digital Integrated Circuits W2 Devices x (d) Electrostatic potential. © Prentice Hall 1995 Diode Current Digital Integrated Circuits Devices © Prentice Hall 1995 pn (W2) Forward Bias pn0 Lp np0 p-region -W1 0 W2 n-region x diffusion Digital Integrated Circuits Devices © Prentice Hall 1995 Reverse Bias pn0 np0 p-region -W1 0 W2 x n-region diffusion Digital Integrated Circuits Devices © Prentice Hall 1995 Diode Types pn(x) Short-base Diode (standard in semiconductor devices) x pn0 Wn pn(x) pn0 Digital Integrated Circuits Long-base Diode x Wn Devices © Prentice Hall 1995 Models for Manual Analysis + ID = IS(eV D/T – 1) VD ID + + VD – – (a) Ideal diode model Digital Integrated Circuits – VDon (b) First-order diode model Devices © Prentice Hall 1995 Junction Capacitance Digital Integrated Circuits Devices © Prentice Hall 1995 Diffusion Capacitance Digital Integrated Circuits Devices © Prentice Hall 1995 Diode Switching Time Rsrc VD V1 ID Vsrc V2 t=0 t=T VD Excess charge Space charge ON OFF ON Time Digital Integrated Circuits Devices © Prentice Hall 1995 Secondary Effects ID (A) 0.1 0 –0.1 –25.0 –15.0 –5.0 0 5.0 VD (V) Avalanche Breakdown Digital Integrated Circuits Devices © Prentice Hall 1995 Diode Model RS + VD ID CD - Digital Integrated Circuits Devices © Prentice Hall 1995 SPICE Parameters Digital Integrated Circuits Devices © Prentice Hall 1995 The MOS Transistor Gate Oxyde Gate Source Polysilicon n+ Drain n+ p-substrate Field-Oxyde (SiO2) p+ stopper Bulk Contact CROSS-SECTION of NMOS Transistor Digital Integrated Circuits Devices © Prentice Hall 1995 Cross-Section of CMOS Technology Digital Integrated Circuits Devices © Prentice Hall 1995 MOS transistors Types and Symbols D D G G S S NMOS Enhancement NMOS Depletion D D G G S S PMOS Enhancement Digital Integrated Circuits B Devices NMOS with Bulk Contact © Prentice Hall 1995 Threshold Voltage: Concept + S VGS - D G n+ n+ n-channel Depletion Region p-substrate B Digital Integrated Circuits Devices © Prentice Hall 1995 The Threshold Voltage Digital Integrated Circuits Devices © Prentice Hall 1995 Current-Voltage Relations VGS VDS S G n+ – V(x) ID D n+ + L x p-substrate B MOS transistor and its bias conditions Digital Integrated Circuits Devices © Prentice Hall 1995 Current-Voltage Relations Digital Integrated Circuits Devices © Prentice Hall 1995 Transistor in Saturation VGS VDS > VGS - VT G D S n+ Digital Integrated Circuits - VGS - VT Devices + n+ © Prentice Hall 1995 I-V Relation VDS = VGS-VT Saturation ID (mA) VGS = 4V 1 VGS = 3V VGS = 2V VGS = 1V 0.0 1.0 2.0 3.0 4.0 5.0 VDS (V) 0.020 ÷ID Triode Square Dependence 2 VGS = 5V 0.010 Subthreshold Current 0.0 2.0 VT1.0 VGS (V) 3.0 (b) ID as a function of VGS (for VDS = 5V). (a) ID as a function of VD S NMOS Enhancement Transistor: W = 100 m, L = 20 m Digital Integrated Circuits Devices © Prentice Hall 1995 A model for manual analysis Digital Integrated Circuits Devices © Prentice Hall 1995 Dynamic Behavior of MOS Transistor G CGS CGD D S CGB CSB CDB B Digital Integrated Circuits Devices © Prentice Hall 1995 The Gate Capacitance Digital Integrated Circuits Devices © Prentice Hall 1995 Average Gate Capacitance Different distributions of gate capacitance for varying operating conditions Most important regions in digital design: saturation and cut-off Digital Integrated Circuits Devices © Prentice Hall 1995 Diffusion Capacitance Digital Integrated Circuits Devices © Prentice Hall 1995 Junction Capacitance Digital Integrated Circuits Devices © Prentice Hall 1995 Linearizing the Junction Capacitance Replace non-linear capacitance by large-signal equivalent linear capacitance which displaces equal charge over voltage swing of interest Digital Integrated Circuits Devices © Prentice Hall 1995 The Sub-Micron MOS Transistor • Threshold Variations • Parasitic Resistances • Velocity Sauturation and Mobility Degradation • Subthreshold Conduction • Latchup Digital Integrated Circuits Devices © Prentice Hall 1995 Threshold Variations VT Long-channel threshold Low VDS threshold L Threshold as a function of the length (for low VDS) Digital Integrated Circuits Drain-induced barrier lowering (for low L) Devices © Prentice Hall 1995 Parasitic Resistances Polysilicon gate LD G Drain contact W VGS,eff D S RS RD Drain Digital Integrated Circuits Devices © Prentice Hall 1995 Velocity Saturation (1) 2 n (cm /Vs) n (cm/sec) sat = 10 7 constant velocity Constant mobility (slope = ) Esat E V/m) 700 250 0 EtV/m) (b) Mobility degradation (a) Velocity saturation Digital Integrated Circuits n0 Devices © Prentice Hall 1995 Velocity Saturation (2) 1.5 0.5 VGS = 3 0.5 VGS = 2 VGS = 1 0.0 1.0 2.0 3.0 4.0 5.0 VDS (V) (a) I D as a function of VDS ID (mA) VGS = 4 I D (mA) 1.0 Linea r Dependence VGS = 5 0 0.0 1.0 2.0 VGS (V) 3.0 (b) ID as a function of VGS (for VDS = 5 V). Linear Dependence on VGS Digital Integrated Circuits Devices © Prentice Hall 1995 Sub-Threshold Conduction 102 ln(ID) (A) 104 Linear region 106 108 1010 10120.0 Digital Integrated Circuits Subthreshold exponential region VT 1.0 2.0 3.0 VGS (V) Devices © Prentice Hall 1995 Latchup VD D VDD p + + n n + p + p n-well + n + p-source Rnwell Rpsubs n-source p-substrate (a) Origin of latchup Digital Integrated Circuits Rnwell Devices Rpsubs (b) Equivalent circuit © Prentice Hall 1995 SPICE MODELS Level 1: Long Channel Equations - Very Simple Level 2: Physical Model - Includes Velocity Saturation and Threshold Variations Level 3: Semi-Emperical - Based on curve fitting to measured devices Level 4 (BSIM): Emperical - Simple and Popular Digital Integrated Circuits Devices © Prentice Hall 1995 MAIN MOS SPICE PARAMETERS Digital Integrated Circuits Devices © Prentice Hall 1995 SPICE Parameters for Parasitics Digital Integrated Circuits Devices © Prentice Hall 1995 SPICE Transistors Parameters Digital Integrated Circuits Devices © Prentice Hall 1995 Fitting level-1 model for manual analysis Region of matching ID Short-channel I-V curve VGS = 5 V Long-channel approximation VDS = 5 V VDS Select k’ and such that best matching is obtained @ Vgs= Vds = VDD Digital Integrated Circuits Devices © Prentice Hall 1995 Technology Evolution Digital Integrated Circuits Devices © Prentice Hall 1995 Bipolar Transistor E B p+ n+ p+ isolation C n+ p p+ n-epitaxy n+ buried layer p-substrate (a) Cross-sectional view. B E n+ p n C (b) Idealized transistor structure. Digital Integrated Circuits Devices © Prentice Hall 1995 Schematic Symbols and Sign Conventions VBC – C VBC IC + C IC + + B IB – + B VCE + VBE IB – – E + VBE IE – – E (a) npn Digital Integrated Circuits VCE IE (b) pnp Devices © Prentice Hall 1995 Operations Modes Digital Integrated Circuits Devices © Prentice Hall 1995 Forward Active Operation Carrier Concentration E nb(0) Depletion Regions B C pc0 nb0 pe0 x 0 W WB Digital Integrated Circuits Devices © Prentice Hall 1995 Current Components B E C 1 IE 2 IC 3 x electrons IB holes Digital Integrated Circuits Devices © Prentice Hall 1995 Reverse Active Carrier Concentration E B C nb(W) pc0 pe0 nb0 nb(0) x 0 W WB Digital Integrated Circuits Devices © Prentice Hall 1995 Saturation Mode Carrier Concentration nb (0) E B C nb(W) QA pc0 QS pe0 nb0 0 x W WB Digital Integrated Circuits Devices © Prentice Hall 1995 Cutoff Carrier Concentration E B nb (0) pe0 nb0 C nb (W) pc0 x 0 W WB Digital Integrated Circuits Devices © Prentice Hall 1995 Bipolar Transistor Operation 0 15 I B=25 A Forward Operation I B=50 A Active I B=75 A 10 IB =75 A IC(mA) I C (mA) I B=100 A IB =100 A -0.25 IB =50 A 5 IB =25 A Reverse Operation Saturation -0.5 -3.0 0 0.0 -1.0 VC E (V) Digital Integrated Circuits 2.0 VCE (V) Devices © Prentice Hall 1995 A Model for Manual Analysis IB B IB C + VBE FIB B C VBE(on) F IB + – – IB = IS (eV BE/T – 1) E E (a) Forward-active (b) Forward-active (simplified) IB C B VBE(sat) + – + – E VCE(sat) IC < FIB (c) Forward-saturation Digital Integrated Circuits Devices © Prentice Hall 1995 Capacitive Model for Bipolar Transistor C QR Cbc Ccs collector-substrate junction capacitance B QF base charge S Cbe E base-emitter junction capacitances base-collector Digital Integrated Circuits Devices © Prentice Hall 1995 Junction Capacitances Digital Integrated Circuits Devices © Prentice Hall 1995 Base Charge - Diffusion Capacitance Digital Integrated Circuits Devices © Prentice Hall 1995 Bipolar Transistors - Secondary Effects • Early Voltage • Parasitic Resistances • Beta Variations Digital Integrated Circuits Devices © Prentice Hall 1995 Early Voltage IC Forward Active VBE3 Saturation VBE2 VBE1 VCE VA Digital Integrated Circuits Devices © Prentice Hall 1995 Parasitic Resistance E B n+ rE p+ C p+ p n+ isolation n-epitaxy rB rC1 p+ rC3 n+ buried layer rC2 p-substrate Digital Integrated Circuits Devices © Prentice Hall 1995 Beta Variations ln (I) IKF IC High Level Injection F Recombination IB VBE (linear) Digital Integrated Circuits Devices © Prentice Hall 1995 SPICE models for Bipolar Digital Integrated Circuits Devices © Prentice Hall 1995 Main Bipolar Transistor SPICE Models Digital Integrated Circuits Devices © Prentice Hall 1995 Spice Parameters for Parasitics Digital Integrated Circuits Devices © Prentice Hall 1995 SPICE Transistor Parameters Digital Integrated Circuits Devices © Prentice Hall 1995 Process Variations Devices parameters vary between runs and even on the same die! Variations in the process parameters, such as impurity concentration densities, oxide thicknesses, and diffusion depths. These are caused by nonuniform conditions during the deposition and/or the diffusion of the impurities. This introduces variations in the sheet resistances and transistor parameters such as the threshold voltage. Variations in the dimensions of the devices, mainly resulting from the limited resolution of the photolithographic process. This causes (W/L) variations in MOS transistors and mismatches in the emitter areas of bipolar devices. Digital Integrated Circuits Devices © Prentice Hall 1995 Impact of Device Variations 2.10 2.10 Delay (nsec) Delay (nsec) 1.90 1.90 1.70 1.70 1.50 1.10 1.20 1.30 1.40 1.50 1.60 Leff (in mm) 1.50 –0.90 –0.80 –0.70 –0.60 –0.50 VTp (V) Delay of Adder circuit as a function of variations in L and VT Digital Integrated Circuits Devices © Prentice Hall 1995
