EE 319K
Introduction to Embedded Systems
Lecture 8: Periodic Timer Interrupts,
Digital-to-Analog Conversion, Sound,
Lab 6
Interrupts: read Sections 9.1 to 9.6
Sound: read Sections 10.1 to 10.3
http://users.ece.utexas.edu/~valvano/Volume1/E-Book/C12_Interactives.htm
http://users.ece.utexas.edu/~valvano/Volume1/E-Book/C13_Interactives.htm
Bard, Gerstlauer, Janapa Reddi, Telang, Tiwari, Valvano, Yerraballi
8-1
Agenda
Interrupt
Recap
PLL
Data structures
FSMs, linked structure
Interrupts
Perform I/O
return from interrupt
 Agenda
Periodic Interrupts
Digital to Analog Conversion
Nyquist Theorem
Sound generation
Bard, Gerstlauer, Janapa Reddi, Telang, Tiwari, Valvano, Yerraballi
SysTick ISR
Output one
value to DAC
8-2
INTERRUPT VECTORS
77 total
Vector address
0x00000038
0x0000003C
0x00000040
0x00000044
0x00000048
0x0000004C
0x00000050
0x00000054
0x00000058
0x0000005C
0x00000060
0x00000064
0x00000068
0x0000006C
0x00000070
0x00000074
0x00000078
0x0000007C
0x00000080
0x00000084
0x00000088
0x0000008C
0x00000090
0x00000094
0x00000098
0x0000009C
0x000000A0
0x000000A4
0x000000A8
0x000000AC
0x000000B0
0x000000B4
0x000000B8
0x000000BC
0x000000C0
0x000000C4
0x000000C8
0x000000CC
0x000000D0
0x000000D4
0x000000D8
0x000000DC
0x000000E0
0x000000E4
0x000000E8
0x000000EC
0x000000F0
0x000000F4
0x000000F8
0x000000FC
Number
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
IRQ
-2
-1
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
ISR name in Startup.s
PendSV_Handler
SysTick_Handler
GPIOPortA_Handler
GPIOPortB_Handler
GPIOPortC_Handler
GPIOPortD_Handler
GPIOPortE_Handler
UART0_Handler
UART1_Handler
SSI0_Handler
I2C0_Handler
PWMFault_Handler
PWM0_Handler
PWM1_Handler
PWM2_Handler
Quadrature0_Handler
ADC0_Handler
ADC1_Handler
ADC2_Handler
ADC3_Handler
WDT_Handler
Timer0A_Handler
Timer0B_Handler
Timer1A_Handler
Timer1B_Handler
Timer2A_Handler
Timer2B_Handler
Comp0_Handler
Comp1_Handler
Comp2_Handler
SysCtl_Handler
FlashCtl_Handler
GPIOPortF_Handler
GPIOPortG_Handler
GPIOPortH_Handler
UART2_Handler
SSI1_Handler
Timer3A_Handler
Timer3B_Handler
I2C1_Handler
Quadrature1_Handler
CAN0_Handler
CAN1_Handler
CAN2_Handler
Ethernet_Handler
Hibernate_Handler
USB0_Handler
PWM3_Handler
uDMA_Handler
uDMA_Error
Lab 6
Lab 8
Lab 9
Lab 10
NVIC
NVIC_SYS_PRI3_R
NVIC_SYS_PRI3_R
NVIC_PRI0_R
NVIC_PRI0_R
NVIC_PRI0_R
NVIC_PRI0_R
NVIC_PRI1_R
NVIC_PRI1_R
NVIC_PRI1_R
NVIC_PRI1_R
NVIC_PRI2_R
NVIC_PRI2_R
NVIC_PRI2_R
NVIC_PRI2_R
NVIC_PRI3_R
NVIC_PRI3_R
NVIC_PRI3_R
NVIC_PRI3_R
NVIC_PRI4_R
NVIC_PRI4_R
NVIC_PRI4_R
NVIC_PRI4_R
NVIC_PRI5_R
NVIC_PRI5_R
NVIC_PRI5_R
NVIC_PRI5_R
NVIC_PRI6_R
NVIC_PRI6_R
NVIC_PRI6_R
NVIC_PRI6_R
NVIC_PRI7_R
NVIC_PRI7_R
NVIC_PRI7_R
NVIC_PRI7_R
NVIC_PRI8_R
NVIC_PRI8_R
NVIC_PRI8_R
NVIC_PRI8_R
NVIC_PRI9_R
NVIC_PRI9_R
NVIC_PRI9_R
NVIC_PRI9_R
NVIC_PRI10_R
NVIC_PRI10_R
NVIC_PRI10_R
NVIC_PRI10_R
NVIC_PRI11_R
NVIC_PRI11_R
NVIC_PRI11_R
NVIC_PRI11_R
Bard, Gerstlauer, Janapa Reddi, Telang, Tiwari, Valvano, Yerraballi
Priority bits
23 – 21
31 – 29
7–5
15 – 13
23 – 21
31 – 29
7–5
15 – 13
23 – 21
31 – 29
7–5
15 – 13
23 – 21
31 – 29
7–5
15 – 13
23 – 21
31 – 29
7–5
15 – 13
23 – 21
31 – 29
7–5
15 – 13
23 – 21
31 – 29
7–5
15 – 13
23 – 21
31 – 29
7–5
15 – 13
23 – 21
31 – 29
7–5
15 – 13
23 – 21
31 – 29
7–5
15 – 13
23 – 21
31 – 29
7–5
15 – 13
23 – 21
31 – 29
7–5
15 – 13
23 – 21
31 – 29
8-3
Nested Vectored Interrupt Controller
(NVIC)
Hardware unit that coordinates among
interrupts from multiple sources
Define priority level of each interrupt source
(NVIC_PRIx_R registers)
Separate enable flag for each interrupt source
(NVIC_EN0_R and NVIC_EN1_R)
Interrupt does not set I bit
Higher priority interrupts can interrupt lower
priority ones
Bard, Gerstlauer, Janapa Reddi, Telang, Tiwari, Valvano, Yerraballi
8-4
NVIC Registers
 High order three bits of each byte define priority
31 – 29
23 – 21
0xE000E400
GPIO Port D
GPIO Port C
GPIO Port B
GPIO Port A
NVIC_PRI0_R
0xE000E404
SSI0, Rx Tx
UART1, Rx Tx
UART0, Rx Tx
GPIO Port E
NVIC_PRI1_R
0xE000E408
PWM Gen 1
PWM Gen 0
PWM Fault
I2C0
NVIC_PRI2_R
0xE000E40C
ADC Seq 1
ADC Seq 0
Quad Encoder
PWM Gen 2
NVIC_PRI3_R
0xE000E410
Timer 0A
Watchdog
ADC Seq 3
ADC Seq 2
NVIC_PRI4_R
0xE000E414
Timer 2A
Timer 1B
Timer 1A
Timer 0B
NVIC_PRI5_R
0xE000E418
Comp 2
Comp 1
Comp 0
Timer 2B
NVIC_PRI6_R
0xE000E41C
GPIO Port G
GPIO Port F
Flash Control
System Control
NVIC_PRI7_R
0xE000E420
Timer 3A
SSI1, Rx Tx
UART2, Rx Tx
GPIO Port H
NVIC_PRI8_R
0xE000E424
CAN0
Quad Encoder 1
I2C1
Timer 3B
NVIC_PRI9_R
0xE000E428
Hibernate
Ethernet
CAN2
CAN1
NVIC_PRI10_R
0xE000E42C
uDMA Error
uDMA Soft Tfr
PWM Gen 3
USB0
NVIC_PRI11_R
0xE000ED20
SysTick
PendSV
--
Debug
NVIC_SYS_PRI3_R
Address
15 – 13
7–5
Bard, Gerstlauer, Janapa Reddi, Telang, Tiwari, Valvano, Yerraballi
Name
8-5
NVIC Interrupt Enable Registers
Two enable registers –
NVIC_EN0_R and NVIC_EN1_R
Each 32-bit register has a single enable bit for
a particular device
NVIC_EN0_R control the IRQ numbers 0 to 31
(interrupt numbers 16 – 47)
NVIC_EN1_R control the IRQ numbers 32 to 47
(interrupt numbers 48 – 63)
Bard, Gerstlauer, Janapa Reddi, Telang, Tiwari, Valvano, Yerraballi
8-6
Interrupt Rituals
Things you must do in every ritual
Initialize data structures (counters, pointers)
Arm (specify a flag may interrupt)
Configure NVIC
o Enable interrupt (NVIC_EN0_R)
o Set priority (e.g., NVIC_PRI1_R)
Enable Interrupts
o Assembly code
o C code
CPSIE I
EnableInterrupts();
Bard, Gerstlauer, Janapa Reddi, Telang, Tiwari, Valvano, Yerraballi
8-7
Interrupt Service Routine (ISR)
Things you must do in every interrupt
service routine
Acknowledge
o clear flag that requested the interrupt
o SysTick is exception; automatic acknowledge
Maintain contents of R4-R11 (AAPCS)
Communicate via shared global variables
Bard, Gerstlauer, Janapa Reddi, Telang, Tiwari, Valvano, Yerraballi
8-8
Interrupt Events
 Respond to infrequent but important events
 Alarm conditions like low battery power
 Error conditions
 I/O synchronization
 Trigger interrupt when signal on a port changes
 Periodic interrupts
 Generated by the timer at a regular rate
 Systick timer can generate interrupt when it hits zero
 Reload value + frequency determine interrupt rate
Bard, Gerstlauer, Janapa Reddi, Telang, Tiwari, Valvano, Yerraballi
8-9
Synchronization
Main
program
ISR
Main
program
ISR
Other calculations
0
Flag = 1
Flag = 1
Flag
Flag
1
Flag = 0
Do important stuff
Semaphore
Other calculations
0
1
Flag = 0
Do important stuff
Use global variable to communicate
One thread sets the flag
The other thread waits for, and clears
Mailbox – to be presented for Lab 8
FIFO queue – to be presented for Lab 9
Bard, Gerstlauer, Janapa Reddi, Telang, Tiwari, Valvano, Yerraballi
8-10
Periodic Interrupts
Data acquisition samples ADC
Lab 8 will sample at a fixed rate
Signal generation output to DAC
Audio player (we use the Systick interrupt to
write samples out periodically in Lab 6)
Communications
Digital controller
FSM
Linear control system (EE362K)
Demo PeriodicSystickInts starter C code
Bard, Gerstlauer, Janapa Reddi, Telang, Tiwari, Valvano, Yerraballi
8-11
Digital Representation of Analog Signals
Digitization: Amplitude and time quantization
32
28
24
20
16
Discrete digital signal
12
8
Continuous analog signal
4
0
0
1
2
3
4
5
6
7
8
9 10
Time (s)
Bard, Gerstlauer, Janapa Reddi, Telang, Tiwari, Valvano, Yerraballi
8-12
Conversion from Digital to Analog
0 to 3.3V
Resolution
3.3V/15 = 0.22V
Precision
4 bits
16 alternative
Measured Analog Output (V)
Range
4-bit DAC
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
0
5
10
15
Digital Input
Speed
Monotonic
http://users.ece.utexas.edu/~valvano/Volume1/E-Book/C13_Interactives.htm
Bard, Gerstlauer, Janapa Reddi, Telang, Tiwari, Valvano, Yerraballi
8-13
Digital
↔ Analog Conversion
Sampled at a fixed time, Dt
fs = 1/Dt
Signal has frequencies 0 to ½ fs
Bard, Gerstlauer, Janapa Reddi, Telang, Tiwari, Valvano, Yerraballi
8-14
Digital ↔ Analog Conversion
Analog: voltage vs. time
Digital: voltage vs. time
fs = 1/Dt
Signal has frequencies 0 to ½ fs
Bard, Gerstlauer, Janapa Reddi, Telang, Tiwari, Valvano, Yerraballi
8-15
Digital-to-Analog Converter (DAC)
 Binary Weighted DAC
 One resistor for each bit of output
 Resistor values in powers of 2
LM3S
TM4C
bit1
bit0
10k
Q1
V1
Q0
LM3S
TM4C
bit1
bit0
Q1
20k
I = 3.7mA
I
R
V2
Q0
20k 20k
V
10k
Battery
V=3.7V
R = 1k
Resistor
Bard, Gerstlauer, Janapa Reddi, Telang, Tiwari, Valvano, Yerraballi
8-16
10k
R2
R1
R0
10
20
40
3 bit DAC
kΩ
kΩ
kΩ
PB2
20k Vout
PB1
40k
PB0
n=1
n=2
n=3
n=4
n=5
n=6
n
0
PB2
0
PB1
0
PB0
0
1
0
0
3.3
R2||R1
2
0
3.3
0
3
0
3.3
4
5
3.3
3.3
6
7
3.3
3.3
3.3V 40k
equation
Vout (V)
0.000
6.67
3.3*(R1||R2)/(R0+R1||R2)
0.471
R2||R0
8.00
3.3*(R2||R0)/(R1+R2||R0)
0.943
3.3
R1||R0
13.33
3.3*R2/(R2+R1||R0)
1.414
0
0
0
3.3
R1||R0
R2||R0
13.33
8.00
3.3*(R1||R0)/(R2+R1||R0)
3.3*R1/(R1+R2||R0)
1.886
2.357
3.3
3.3
0
3.3
R2||R1
6.67
3.3*R0/(R0+R2||R1)
2.829
3.300
Vout
6.7k
3.3V 20k V 8k
out
3.3V 13.3k
3.3V 10k
Vout
Vout
10k
Vout
DAC output
3.500
3.000
2.500
13.3k
3.3V 8k V 20k
out
3.3V 6.7k
kohm
40k
2.000
DAC output
1.500
1.000
0.500
0.000
0
2
Bard, Gerstlauer, Janapa Reddi, Telang, Tiwari, Valvano, Yerraballi
4
6
8-17
8
Other Types of DACs
 R-2R Ladder DAC
Binary weighted cascading ladder
Improved precision owing to ability to select
resistors of equal value
Bard, Gerstlauer, Janapa Reddi, Telang, Tiwari, Valvano, Yerraballi
8-18
DAC Performance
Resolution, range, precision
Maximum sampling frequency
Monotonicity
Input increase causes output increase (always)
Vout
nonlinear
Vout
nonmonotonic
Ideal
Digital Input
Ideal
Digital Input
Bard, Gerstlauer, Janapa Reddi, Telang, Tiwari, Valvano, Yerraballi
8-19
Resistor Network for 4-bit DAC
TM4C123
R3
Static
testing
Bit3
R2
Bit2
bit1
R1
Voltmeter
R0
Bit0
Bard, Gerstlauer, Janapa Reddi, Telang, Tiwari, Valvano, Yerraballi
8-20
Dynamic testing
TM4C123
1.5k
Bit3
Bit2
Bit1
Bit0
3k
Vout
I out
6k
12k
Speaker
Bard, Gerstlauer, Janapa Reddi, Telang, Tiwari, Valvano, Yerraballi
8-21
Sound
Loudness and pitch
 Controlled by amplitude and frequency
Humans can hear from about 25 to 20,000 Hz.
Middle A is 440 Hz
Other notes on a keyboard are determined
o 440 * 2N/12, where N is no. of notes from middle A.
Middle C is 261.6 Hz.
Music contains multiple harmonics
Bard, Gerstlauer, Janapa Reddi, Telang, Tiwari, Valvano, Yerraballi
8-22
Tempo
330 Hz
0.5s
330 Hz
0.5s
523 Hz
1.0s
Tempo defines note duration
Quarter note = 1 beat
120 beats/min => ½ s duration
Bard, Gerstlauer, Janapa Reddi, Telang, Tiwari, Valvano, Yerraballi
8-23
Chord
Two notes at the same time
Sound Amplitude
Superimposed waveforms
262 Hz (low C) and a 392 Hz (G)
2
1
0
-1
-2
0
0.005
0.01
Time (sec)
0.015
Bard, Gerstlauer, Janapa Reddi, Telang, Tiwari, Valvano, Yerraballi
0.02
8-24
Instrument Characteristics
period
Waveform shape of a trumpet sound
330 Hz
0.5s
330 Hz
0.5s
523 Hz
1.0s
Plucked string signal with envelope
Bard, Gerstlauer, Janapa Reddi, Telang, Tiwari, Valvano, Yerraballi
8-25
Synthesizing Digital Music
Nyquist’s Sampling Theorem
We can reproduce any bandlimited signal from
its samples if we sample correctly and at a
frequency, fs, that is at least twice the highest
frequency component of the signal, fmax.
Where do we get the samples?
We could sample a series of musical tones
We can compute the samples
Bard, Gerstlauer, Janapa Reddi, Telang, Tiwari, Valvano, Yerraballi
8-26
Synthesizing Digital Music (cont.)
What is a musical tone?
A sinusoid of a particular frequency
Notes vary by twelfth root of 2 ~ 1.059
What would the samples be?
Fixed point numbers
How do we generate a sinusoid?
Output appropriate digital values via a resistor
network that effectively produces an pseudoanalog signal
What about frequency?
Employ a programmable timer to tell us when
to output the next value
Bard, Gerstlauer, Janapa Reddi, Telang, Tiwari, Valvano, Yerraballi
8-27
Synthesizing Digital Music (cont.)
440 Hz sine wave generated by 6-bit DAC
Frequency
spectrum
Bard, Gerstlauer, Janapa Reddi, Telang, Tiwari, Valvano, Yerraballi
8-28
Music Generation – Lab 6
Objectives
Employ TM4C to generate appropriately
scaled digital outputs at a specified
frequency
o Three frequencies are required
o Frequencies are to be determined by switch
settings
Four digital outputs are inputs to a resistor
network that serves as a digital-to-analog
converter (DAC)
o Four output bits => 16 levels
Bard, Gerstlauer, Janapa Reddi, Telang, Tiwari, Valvano, Yerraballi
8-29
Music Generation (cont.)
DAC hardware
Employ least significant four bits of a GPIO port
Arrange resistor network in 1, 2, 4, 8 sequence
o Each port bit can assume digital levels of 0 and 3.3 V
o Ports are current limited – max 8 mA
TM4C123
Bit3
R3
Static
testing
R2
Bit2
R1
Voltmeter
bit1
Bit0
R0
Bard, Gerstlauer, Janapa Reddi, Telang, Tiwari, Valvano, Yerraballi
8-30
Music Generation (cont.)
DAC software
Interactions via device drivers
Two device driver functions required
void DAC_Init(void);
void DAC_Out(unsigned char data);
// initializes the device
// transfers data to device
(Device driver provides the functions associated
with the device but hides the detailed actions
necessary to implement the functions.)
Bard, Gerstlauer, Janapa Reddi, Telang, Tiwari, Valvano, Yerraballi
8-31
Music Generation (cont.)
Interpretation of data
Note has three parameters
o Amplitude (loudness)
o Frequency (pitch)
o Duration
Amplitude is a digitally approximated sinusoid
o Sinusoid varies between 0 and 3.3 volts
Frequency is selected by switches
o Four states – stop, note_1, note_2, and note_3
Duration is period switch(es) activated
Bard, Gerstlauer, Janapa Reddi, Telang, Tiwari, Valvano, Yerraballi
8-32
4-bit Sinusoid Table
4-bit DAC output
4-bit sin table
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
1
2
3
4
5
6
7
theta (radians)
SinTab
8,9,11,12,13,14,14,15,15,15,14
14,13,12,11,9,8,7,5,4,3,2
32 value sinusoid
2,1,1,1,2,2,3,4,5,7
Bard, Gerstlauer, Janapa Reddi, Telang, Tiwari, Valvano, Yerraballi
8-33
Musical Notes
Note
C
B
Bb
A
Ab
G
b
G
F
E
Eb
D
Db
C
f
523
494
466
440
415
392
370
349
330
311
294
277
262
T (ms)
1.91
2.02
t - ouput (μs for 32 points)
59.75
63.26
2.15
2.27
67.06
71.02
2.41
2.55
75.30
79.72
2.70
2.87
3.03
84.46
89.54
94.70
3.22
3.40
100.48
106.29
3.61
3.82
112.82
119.27
Bard, Gerstlauer, Janapa Reddi, Telang, Tiwari, Valvano, Yerraballi
8-34
Tone Generation
unsigned long I;
// 4-bit 32-element sine wave
const uint8_t wave[32]= {
8,9,11,12,13,14,14,15,15,15,14
14,13,12,11,9,8,7,5,4,3,2
2,1,1,1,2,2,3,4,5,7};
SysTick ISR
Output one
value to DAC
 For a 440Hz tone
 Assume a bus clock frequency of 50 MHz
o SysTick count every 20ns
 Each cycle of the 440 Hz sinusoid requires:
o (50*106 counts/s)/440 Hz = 113636.36 SysTick counts
 Each cycle consists of 32 values each of duration:
o 113636.36 interrupt counts/32 values =
3551 SysTick counts/value
o DAC values change every 71.02 us
Bard, Gerstlauer, Janapa Reddi, Telang, Tiwari, Valvano, Yerraballi
8-35
Lab 6 ISR
Each Systick interrupt
Output one value from the array to DAC
Increment index to array (wrap back to zero)
In main program
If a switch is pressed set SysTick period (arm)
If no switches are pressed then disarm
SysTick ISR
Output one
value to DAC
Bard, Gerstlauer, Janapa Reddi, Telang, Tiwari, Valvano, Yerraballi
8-36
Other Instruments
// 6-bit 64-element bassoon wave
const uint8_t Bassoon[64] = {
33,37,37,36,35,34,34,33,31,30,29,
30,33,43,58,63,52,31,13,4,5,10,16,
23,32,40,46,48,44,38,30,23,17,12,11,
15,23,32,40,42,39,32,26,23,23,24,25,
25,26,29,30,31,32,34,37,39,37,35,34,
34,34,33,31,30};
Bassoon
70
60
50
40
30
20
10
0
1
// 6-bit 64-element guitar wave
const uint8_t Guitar[64] = {
20,20,20,19,16,12,8,4,3,5,10,17,
26,33,38,41,42,40,36,29,21,13,9,
9,14,23,34,45,52,54,51,45,38,31,
26,23,21,20,20,20,22,25,27,29,
30,29,27,22,18,13,11,10,11,13,13,
13,13,13,14,16,18,20,20,20};
4 7 10 13 16 19 22 25 28 31 34 37 40 43 46 49 52 55 58 61 64
Guitar
60
50
40
30
20
10
0
1
4
7 10 13 16 19 22 25 28 31 34 37 40 43 46 49 52 55 58 61 64
Bard, Gerstlauer, Janapa Reddi, Telang, Tiwari, Valvano, Yerraballi
8-37