EE 319K
Introduction to Embedded Systems
Lecture 10: Sampling,
Analog-to-Digital Conversion
Bard, Tiwari, Telang, Janapa Reddi, Gerstlauer, Valvano, Yerraballi
10-1
Agenda
Recap
Local Variables
Stack frames
Recursion
Fixed-point numbers
LCD device driver (Lab 7)
Outline
Sampling, Nyquist theorem
Analog to Digital Conversion
Bard, Tiwari, Telang, Janapa Reddi, Gerstlauer, Valvano, Yerraballi
10-2
Analog to Digital Converter (ADC)
32
28
24
20
16
Discrete digital signal
12
8
Continuous analog signal
4
0
0
1
2
3
4
5
6
7
8
9 10
Time (s)
Bard, Tiwari, Telang, Janapa Reddi, Gerstlauer, Valvano, Yerraballi
10-3
Nyquist Theorem
 A bandlimited analog signal that has been sampled can be
perfectly reconstructed from an infinite sequence of
samples if the sampling rate fs exceeds 2fmax samples per
second, where fmax is the highest frequency in the original
signal.
 If the analog signal does contain frequency components
larger than (1/2)fs, then there will be an aliasing error.
 Aliasing is when the digital signal appears to have a
different frequency than the original analog signal.
 Valvano Postulate: If fmax is the largest frequency
component of the analog signal, then you must sample
more than ten times fmax in order for the reconstructed
digital samples to look like the original signal when plotted
on a voltage versus time graph.
http://www.ece.utexas.edu/~valvano/UTx319K/nyquist2.html
Bard, Tiwari, Telang, Janapa Reddi, Gerstlauer, Valvano, Yerraballi
10-4
Sampling (option 1)
200Hz signal sampled at 2000Hz
4000
Points are digital data, solid curve is the truth. What is the frequency?
Signal
3000
2000
1000
0
0.000
0.001
0.002
0.003
0.004
0.005
0.006
0.007
0.008
Time (sec)
http://www.ece.utexas.edu/~valvano/Volume1/Nyquist.xls
Bard, Tiwari, Telang, Janapa Reddi, Gerstlauer, Valvano, Yerraballi
10-5
Sampling (option 1)
1000Hz signal sampled at 2000Hz
4000
Points are digital data, solid curve is the truth. What is the frequency?
Signal
3000
2000
1000
0
0.000
0.001
0.002
0.003
0.004
0.005
0.006
0.007
0.008
Time (sec)
http://www.ece.utexas.edu/~valvano/Volume1/Nyquist.xls
Bard, Tiwari, Telang, Janapa Reddi, Gerstlauer, Valvano, Yerraballi
10-6
Sampling (option 1)
2200Hz signal sampled at 2000Hz
4000
Points are digital data, solid curve is the truth. What is the frequency?
Signal
3000
2000
1000
This is aliasing
0
0.000
0.001
0.002
0.003
0.004
0.005
0.006
0.007
0.008
Time (sec)
http://www.ece.utexas.edu/~valvano/Volume1/Nyquist.xls
Bard, Tiwari, Telang, Janapa Reddi, Gerstlauer, Valvano, Yerraballi
10-7
Sampling (option 2)
100Hz signal sampled at 1600Hz
Sampled Data
3
2.5
Sampled Data
T rue Data
2.0
Voltage (V)
Voltage (V)
2
1
0
-1
0
2
4
-2
-3
6
8
FFT Magnitude
10
1.5
1.0
0.5
0.0
0.0
Time (ms)
0.2
0.4
0.6
0.8
1.0
Frequency (kHz)
http://www.ece.utexas.edu/~valvano/EE345L/Labs/Fall2011/FFT16.xls
Bard, Tiwari, Telang, Janapa Reddi, Gerstlauer, Valvano, Yerraballi
10-8
Sampling (option 2)
A signal with DC, 100Hz and 400Hz
sampled at 1600Hz
Sampled Data
3
2.5
Sampled Data
T rue Data
2.0
1
0
0
2
4
8
10
1.5
1.0
0.5
-2
-3
6
Voltage (V)
Voltage (V)
2
-1
FFT Magnitude
0.0
Time (ms)
0.0
0.2
0.4
0.6
0.8
1.0
Frequency (kHz)
http://www.ece.utexas.edu/~valvano/EE345L/Labs/Fall2011/FFT16.xls
Bard, Tiwari, Telang, Janapa Reddi, Gerstlauer, Valvano, Yerraballi
10-9
Sampling (option 2)
1500Hz signal sampled at 1600Hz
This is aliasing
Sampled Data
3
2.5
Sampled Data
T rue Data
2.0
Voltage (V)
Voltage (V)
2
1
0
-1
0
2
4
8
1.5
1.0
10
0.5
-2
-3
6
FFT Magnitude
0.0
0.0
0.2
Time (ms)
0.4
0.6
0.8
1.0
Frequency (kHz)
http://www.ece.utexas.edu/~valvano/EE345L/Labs/Fall2011/FFT16.xls
Bard, Tiwari, Telang, Janapa Reddi, Gerstlauer, Valvano, Yerraballi
10-10
Analog to Digital Converter (ADC)
 Successive approximation ADC
 VIN is approximated as a
static value in a sample and
hold (S/H) circuit
 the successive approximation
register (SAR) is a counter
that increments each clock
as long as it is enabled by
the comparator
 the output of the SAR is fed
to a DAC that generates a
voltage for comparison with
VIN
 when the output of the DAC =
VIN the value of SAR is the
digital representation of VIN
Bard, Tiwari, Telang, Janapa Reddi, Gerstlauer, Valvano, Yerraballi
end of conversion
10-11
Sample-And-Hold Circuit
S/H
 Analog Input (AI) is sampled when
the switch is closed and its value is
held on the capacitor where it
becomes the Analog Output (AO)
Bard, Tiwari, Telang, Janapa Reddi, Gerstlauer, Valvano, Yerraballi
10-12
ADC on TM4C123
Sampling Range/Resolution
3.3V internal reference voltage
0x000 at 0 V input
0xFFF at 3.3 V
resolution = range/precision
= 3.3V/4096 alternatives < 1mV
Bard, Tiwari, Telang, Janapa Reddi, Gerstlauer, Valvano, Yerraballi
10-13
ADC on TM4C123
PE2=Ain1 used for Lab 8, 9, 10
Twelve analog input channels
Single-ended and differential-input configurations
On-chip internal temperature sensor
Sample rate up to one million samples/second
40 Hz
Flexible, configurable analog-to-digital conversion
Four programmable sample conversion sequences from one to
eight entries long, with corresponding conversion result FIFOs
 Flexible trigger control











Controller (software)
Timers
Analog Comparators
PWM
GPIO
We will use software initiated trigger
 Hardware averaging of up to 64 samples for improved accuracy
 Converter uses an internal 3V reference
Bard, Tiwari, Telang, Janapa Reddi, Gerstlauer, Valvano, Yerraballi
10-14
ADC on TM4C123
PE2=Ain1 used for Lab 8, 9, 10
Ain1
PE2
Software
initiated
Use sequencer 3
Bit 3 is done flag
Bard, Tiwari, Telang, Janapa Reddi, Gerstlauer, Valvano, Yerraballi
10-15
ADC on TM4C123
PD4=Ain4 used for DLL testing
IO
PB4
PB5
PD0
PD1
PD2
PD3
PE0
PE1
PE2
PE3
PE4
PE5
Ain
Ain10
Ain11
Ain7
Ain6
Ain5
Ain4
Ain3
Ain2
Ain1
Ain0
Ain9
Ain8
0
Port
Port
Port
Port
Port
Port
Port
Port
Port
Port
Port
Port
1
SSI3Clk
SSI3Fss
SSI3Rx
SSI3Tx
U7Rx
U7Tx
U5Rx
U5Tx
2
3
4
5
6
SSI2Clk
M0PWM2
SSI2Fss
M0PWM3
SSI1Clk I2C3SCL M0PWM6 M1PWM0
SSI1Fss I2C3SDA M0PWM7 M1PWM1
SSI1Rx
M0Fault0
SSI1Tx
IDX0
7
T1CCP0
T1CCP1
WT2CCP0
WT2CCP1
WT3CCP0
WT3CCP1
I2C2SCL M0PWM4 M1PWM2
I2C2SDA M0PWM5 M1PWM3
8
CAN0Rx
CAN0Tx
9
14
USB0epen
USB0pflt
CAN0Rx
CAN0Tx
PE2=Ain1 used for Lab 8, 9, 10
PE4=Ain9 used in book and ADCSWTrigger_4C123
Twelve different pins can be used to sample analog inputs.
Bard, Tiwari, Telang, Janapa Reddi, Gerstlauer, Valvano, Yerraballi
10-16
ADC on TM4C123
TM4C ADC registers
Address
$400F.E638
31-2
31-14
$4003.8020
13-12
SS3
11-10
31-16
$4003.8014
31-4
$4003.8000
$4003.80A0
$4003.80A4
$4003.8028
$4003.8004
$4003.8008
$4003.8FC4
9-8
SS2
7-6
15-12
EM3
3
ASEN3
TS0
SS3
INR3
MASK3
31-12
$4003.80A8
1
ADC1
0
ADC0
5-4
SS1
3-2
11-8
EM2
7-4
EM1
2
1
ASEN2
ASEN1
MUX0
IE0
END0
SS2
SS1
INR2
INR1
MASK2
MASK1
Speed
1-0
SS0
ADC0_SSPRI_R
3-0
EM0
ADC0_EMUX_R
0
ASEN0
D0
SS0
INR0
MASK0
11-0
DATA
Bard, Tiwari, Telang, Janapa Reddi, Gerstlauer, Valvano, Yerraballi
Name
SYSCTL_RCGCADC_R
ADC0_ACTSS_R
ADC0_SSMUX3_R
ADC0_SSCTL3_R
ADC0_PSSI_R
ADC0_RIS_R
ADC0_IM_R
ADC0_PC_R
ADC0_SSFIFO3_R
10-17
ADC on TM4C123
TM4C123 ADC
Operation
select
select
select
select
select
o0
o1
o1
o0
rate
sequencer
trigger
channel
sample mode
Value
0x7
0x5
0x3
0x1
Description
1M samples/second
500K samples/second
250K samples/second
125K samples/second
Speed bits in ADC0_PC_R
not temperature
set completion flag
end sequence
EM3, EM2, EM1, and EM0 bits in ADC_EMUX_R
not differential
ADC0_SSCTL3_R = 0x06;
Bard, Tiwari, Telang, Janapa Reddi, Gerstlauer, Valvano, Yerraballi
10-18
ADC on TM4C123
 Initialization
 Enable ADC clock: set bit 0 in SYSCTL_RCGCADC_R
 Set 125kHz ADC conversion speed: write 0x01 to
ADC0_PC_R
 Set sequencer priority: 0,1,2,3 in ADC0_SSPRI_R
 Disable selected sequence 3: zero bit 3 of ADC0_ACTSS_R
 Set software start trigger event: zero bits 15-12 of
ADC0_EMUX_R
 Set input source (0-11): write channel number in bits 3-0
of ADC0_SSMUX3_R (channel 9 is PE4, channel 1 is PE2)
 Set sample control bits: write 0110 in bits 3-0
ADC0_SSCTL3_R to disable temp measurement, notify on
sample complete, indicate single sample in sequence, and
denote single-ended signal mode
 Disable interrupts: zero bit 3 of ADC0_IM_R
 Enable selected sequencer 3: set bit 3 of ADC0_ACTSS_R
Bard, Tiwari, Telang, Janapa Reddi, Gerstlauer, Valvano, Yerraballi
10-19
Channel 9 is PE4
ADC on TM4C123
void ADC0_InitSWTriggerSeq3_Ch9(void){
SYSCTL_RCGCGPIO_R |= 0x10;
// 1) activate clock for Port E
while((SYSCTL_PRGPIO_R&0x10) == 0){};
GPIO_PORTE_DIR_R &= ~0x10;
// 2) make PE4 input
GPIO_PORTE_AFSEL_R |= 0x10;
// 3) enable alternate fun on PE4
GPIO_PORTE_DEN_R &= ~0x10;
// 4) disable digital I/O on PE4
GPIO_PORTE_AMSEL_R |= 0x10;
// 5) enable analog fun on PE4
SYSCTL_RCGCADC_R |= 0x01;
// 6) activate ADC0
delay = SYSCTL_RCGCADC_R;
// extra time to stabilize
delay = SYSCTL_RCGCADC_R;
// extra time to stabilize
delay = SYSCTL_RCGCADC_R;
// extra time to stabilize
delay = SYSCTL_RCGCADC_R;
ADC0_PC_R = 0x01;
// 7) configure for 125K
ADC0_SSPRI_R = 0x0123;
// 8) Seq 3 is highest priority
ADC0_ACTSS_R &= ~0x0008;
// 9) disable sample sequencer 3
ADC0_EMUX_R &= ~0xF000;
// 10) seq3 is software trigger
ADC0_SSMUX3_R = (ADC0_SSMUX3_R&0xFFFFFFF0)+9; // 11) Ain9 (PE4)
ADC0_SSCTL3_R = 0x0006;
// 12) no TS0 D0, yes IE0 END0
ADC0_IM_R &= ~0x0008;
// 13) disable SS3 interrupts
ADC0_ACTSS_R |= 0x0008;
// 14) enable sample sequencer 3
}
Book shows Ain9=PE4
Lab 8, 9, 10 use Ain1=PE2
Bard, Tiwari, Telang, Janapa Reddi, Gerstlauer, Valvano, Yerraballi
10-20
ADC on TM4C123
Analog to digital conversion
Set software trigger
ADC_In
o Write to PSSI bit 3
Start
ADC
Busy-Wait
o Raw Interrupt Status = RIS bit 3
o Poll until sample complete
Status
Read sample
o Read from SSFIFO3
Clear sample complete flag
o Write to ISC bit 3
Busy
Done
Read data
Clear flag
return(data)
Bard, Tiwari, Telang, Janapa Reddi, Gerstlauer, Valvano, Yerraballi
10-21
ADC on TM4C123
//------------ADC_InSeq3-----------// Busy-wait analog to digital conversion
// Input: none
// Output: 12-bit result of ADC conversion
uint32_t ADC0_InSeq3(void){
uint32_t data;
ADC0_PSSI_R = 0x0008;
while((ADC0_RIS_R&0x08)==0){};
data = ADC0_SSFIFO3_R&0xFFF;
ADC0_ISC_R = 0x0008;
return data;
}
ADC_In
Start
ADC
Status
Busy
Done
Read data
Clear flag
return(data)
Bard, Tiwari, Telang, Janapa Reddi, Gerstlauer, Valvano, Yerraballi
10-22