EE 319K
Introduction to Microcontrollers
Lecture 1: Introduction,
Embedded Systems, Product
Life-Cycle, ARM Programming
Bard, Gerstlauer, Valvano, Yerraballi
1-1
Agenda
Course Description
Book, Labs, Equipment
Grading Criteria
Expectations/Responsibilities
Prerequisites
Embedded Systems
Microcontrollers
Product Life Cycle
Analysis, Design, Implementation, Testing
Flowcharts, Data-Flow and Call Graphs
ARM Architecture
Programming
Integrated Development Environment (IDE)
Bard, Gerstlauer, Valvano, Yerraballi
1-2
EE306 Recap: Digital Logic
+3.3V
p-type
A p-type n-type ~A
0 V active off +3.3V
+3.3V off active 0V A
gate
n-type
gate
Digital
Analog 0
"0"
Illegal
1.3
2.0
Positive logic:
True is higher voltage
False is lower voltage
Bard, Gerstlauer, Valvano, Yerraballi
source
drain
~A
drain
source
"1"
5V
~A
A
74HC04
A
0
1
~A
1
0
 AND, OR, NOT
 Flip flops
 Registers
Negative logic :
True is lower voltage
False is higher voltage
1-3
EE302 Recap: Ohm’s Law
V=I*R
I=V/R
R=V/I
Voltage = Current * Resistance
Current = Voltage / Resistance
Resistance = Voltage / Current
I = 3.7mA
I
V
R
•P = V * I
•P = V2 / R
•P = I2 * R
Battery
V=3.7V
R = 1k
Resistor
Power = Voltage * Current
Power = Voltage2 / Resistance
Power = Current2 * Resistance
Bard, Gerstlauer, Valvano, Yerraballi
1-4
Embedded System
automotive
medical
communications
microcomputer
appliances
consumer electronics
LM3S or LM4F
Processor
I/O Ports
RAM
ROM
Bus
ADC
 Ubiquitous, invisible
 Hidden (computer inside)
 Dedicated purpose
 MicroProcessor
Embedded system
Microcontroller
 Embedded Systems are
everywhere
Electrical,
mechanical,
chemical,
or
optical
devices
DAC
Analog
signals
Bard, Gerstlauer, Valvano, Yerraballi
 Intel: 4004, ..8080,..
x86
 Motorola: 6800, ..
6812,.. PowerPC
 ARM, DEC, SPARC, MIPS,
PowerPC, Natl. Semi.,…
 MicroController
 Processor+Memory+
I/O Ports (Interfaces)
1-5
Embedded Systems
A reactive system continuously
accepts inputs
performs calculations
generates outputs
A real time system
Specifies an upper bound on the time
required to perform the
input/calculation/output in reaction to
external events
Bard, Gerstlauer, Valvano, Yerraballi
1-6
Microcontroller
 Processor – Instruction Set
 CISC vs. RISC
 Memory
 Non-Volatile
o ROM
o EPROM, EEPROM, Flash
 Volatile
o RAM (DRAM, SRAM)
 Interfaces
 H/W: Ports
 S/W: Device Driver
 Parallel, Serial, Analog, Time
 I/O
 Memory-mapped vs. I/O mapped
Bard, Gerstlauer, Valvano, Yerraballi
1-7
Texas Instruments TM4C123
Systick
NVIC
Cortex M4
System Bus Interface
GPIO Port A
PA7
PA6
PA5/SSI0Tx
PA4/SSI0Rx
PA3/SSI0Fss
PA2/SSI0Clk
PA1/U0Tx
PA0/U0Rx
PC7
PC6
PC5
PC4
PC3/TDO/SWO
PC2/TDI
PC1/TMS/SWDIO
PC0/TCK/SWCLK
GPIO Port B
Eight
UARTs
Four
I2Cs
Four
SSIs
CAN 2.0
GPIO Port C
GPIO Port D
USB 2.0
Twelve
Timers
JTAG
Six
64-bit wide
GPIO Port E
PE5
PE4
PE3
PE2
PE1
PE0
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
GPIO Port F
Two Analog
Comparators
ADC
2 channels
12 inputs
12 bits
Advanced High Performance Bus
PB7
PB6
PB5
PB4
PB3/I2C0SDA
PB2/I2C0SCL
PB1
PB0
Two PWM
Modules
ARM Cortex-M4
+ 256K EEPROM
+ 32K RAM
+ JTAG
+ Ports
+ SysTick
+ ADC
+ UART
PF4
PF3
PF2
PF1
PF0
Advanced Peripheral Bus
Bard, Gerstlauer, Valvano, Yerraballi
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Product Life Cycle
• Specifications
• Constraints
Requirements
Constraints
Design
Analyze
the
problem
• Block diagrams
• Data flow graphs
Development
New requirements
New constraints
Deployment
Done
Testing
• Hardware
• Software
Implementation(Real)
Analysis (What?)
Hardware, Software
Requirements ->
Specifications
Testing (Works?)
Design (How?)
Validation:Correctness
High-Level: Block Diagrams
Performance: Efficiency
Engineering: Algorithms,
Maintenance (Improve)
Data Structures, Interfacing
Bard, Gerstlauer, Valvano, Yerraballi
1-9
Data Flow Graph
Lab 8: Position Measurement System
Position Voltage
0 to 3 cm 0 to +3V
Position
Sensor
Sample
0 to 4095
ADC
hardware
ADC
driver
Sample
0 to 4095
SysTick
ISR
SysTick
hardware
LCD
display
Bard, Gerstlauer, Valvano, Yerraballi
Fixed-point
0 to 3.000
LCD
driver
1-10
Call Flow Graph
Position Measurement System
SysTick
ISR
main
SysTick
init
ADC
driver
SysTick
hardware
ADC
hardware
Bard, Gerstlauer, Valvano, Yerraballi
LCD
driver
LCD
hardware
1-11
Structured Programming
Common Constructs (as Flowcharts)
Sequence
Conditional
While-loop
Block 1
Block 2
Parallel
Fork
Join
Block 1
Block 2
Distributed
Block
Interrupt-driven concurrent
Trigger
main
interrupt
main1
main2
Init1
Init2
Init
Body1
Body2
Body
Bard, Gerstlauer, Valvano, Yerraballi
Return from
interrupt
1-12
Flowchart
Toaster oven:
Cook
main
Output heat
is on
Input from
switch
Start
Not pressed
Input toast
temperature
Pressed
Cook
Too cold
toast < desired
toast  desired
Output heat
is off
return
Coding in assembly and/or high-level language (C)
Bard, Gerstlauer, Valvano, Yerraballi
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Flowchart

Example 1.3. Design a flowchart for a system that performs two independent
tasks. The first task is to output a 20 kHz square wave on PORTA in real time
(period is 50 ms). The second task is to read a value from PORTB, divide the
value by 4, add 12, and output the result on PORTD. This second task is repeated
over and over.
main
A
Input n from B
PORTB
n = (n/4)+12
C
Output n to
PORTD
D
Clock
PORTA =
PORTA^1
Bard, Gerstlauer, Valvano, Yerraballi
<
E
>
void SysTick_Handler(void){
PORTA = PORTA^0x01;
E
}
>
void main(void){
unsigned long n;
while(1){
n = PORTB;
n = (n/4)+12;
PORTD = n;
}
}
A
B
C
D
1-14
ARM Cortex M4-based System
System bus
Microcontroller
ARM® CortexTM-M
processor
Input
ports
PPB
Internal
peripherals
Advanced
High-perf
Bus
Instructions
Flash ROM
ICode bus
DCode bus
Output
ports
Data
RAM
 ARM Cortex-M4 processor
 Harvard architecture
 Different busses for instructions and data
 RISC machine
 Pipelining effectively provides single cycle operation for many
instructions
 Thumb-2 configuration employs both 16 and 32 bit instructions
Bard, Gerstlauer, Valvano, Yerraballi
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ARM ISA: Thumb2 Instruction Set
 Variable-length instructions
ARM instructions are a fixed
length of 32 bits
Thumb instructions are a fixed
length of 16 bits
Thumb-2 instructions can be
either 16-bit or 32-bit
 Thumb-2 gives approximately 26%
improvement in code density over
ARM
 Thumb-2 gives approximately 25%
improvement in performance over
Thumb
Bard, Gerstlauer, Valvano, Yerraballi
1-16
ARM ISA: Registers, Memory-map
General
purpose
registers
Stack pointer
Link register
Program counter
Condition Code Bits
N negative
Z zero
V overflow
C carry
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13 (MSP)
R14 (LR)
R15 (PC)
Indicates
Result is negative
Result is zero
Signed overflow
Unsigned overflow
Bard, Gerstlauer, Valvano, Yerraballi
256k Flash
ROM
32k RAM
0x0000.0000
0x0003.FFFF
0x2000.0000
0x2000.7FFF
I/O ports
0x4000.0000
0x400F.FFFF
Internal I/O
PPB
0xE000.0000
0xE004.1FFF
TI TM4C123
Microcontroller
1-17
LC3 to ARM - Data Movement
LEA R0, Label
;R0 <- PC + Offset to Label
ADR R0,Label or LDR R0,=Label
LD
R1,Label
LDR R0,=Label
LDRH R1,[R0]
LDR R1,R0,n
; R1 <- M[PC + Offset]
; Two steps: (i) Get address into R0
; (ii) Get content of address [R0] into R1
; R1 <- M[R0+n]
LDRH R1,[R0,#n]
LDI
R1,Label
; R1 <- M[M[PC + Offset]]
; Three steps!!
ST R1,Label
LDR R0,=Label
STRH R1,[R0]
STR R1,R0,n
; R1 -> M[PC + Offset]
; Two steps: (i)Get address into R0
; (ii) Put R1 contents into address in R0
; R1 -> M[R0+n]
STRH R1,[R0,#n]
STI R1,Label
; R1 -> M[M[PC + Offset]]
; Three steps!!
Bard, Gerstlauer, Valvano, Yerraballi
1-18
LC3 to ARM – Arithmetic/Logic
ADD R1, R2, R3
ADD R1,R2,R3
ADD R1,R2,#5
ADD R1,R2,#5
AND R1,R2,R3
AND R1, R2, R3
; R1 <- R2 + R3
; 32-bit only
; R1 <- R2 + 5
; 32-bit only, Immediate is 12-bit
; R1 <- R2 & R3
; 32-bit only
AND R1,R2,#1
AND R1, R2, #1
; R1 <- Bit 0 of R2
; 32-bit only
NOT R1,R2
; R1 -> ~(R2)
EOR R1,R2,#-1
; -1 is 0xFFFFFFFF,
; so bit XOR with 1 gives complement
Bard, Gerstlauer, Valvano, Yerraballi
1-19
LC3 to ARM – Branches
BR Target
; PC <- Address of Target
B Target
BRnzp Target
; PC <- Address of Target
B Target
BRn Target
BMI Target
BRz Target
; PC <- Address of Target if N=1
; Branch on Minus
; PC <- Address of Target if Z=1
BEQ Target
BRp Target
; PC <- Address of Target if P=1
No Equivalent
BRnp Target
; PC <- Address of Target if Z=0
BNE Target
BRzp Target
BPL Target
BRnz Target
; PC <- Address of Target if N=0
; Branch on positive or zero (Plus)
; PC <- Address of Target if P=0
No Equivalent
Bard, Gerstlauer, Valvano, Yerraballi
1-20
LC3 to ARM – Subs,TRAP,Interrupt
JSR Sub
BL Sub
JSRR R4
BLX R4
RET
BX LR
JMP R2
BX R2
TRAP x25
; PC <- Address of Sub, Return address in R7
; PC<-Address of Sub, Ret. Addr in R14 (Link Reg)
; PC <- R4, Return address in R7
; PC <-R4, Return address in R14 (Link Reg)
; PC <- R7 (Implicit JMP to address in R7)
; PC <- R14 (Link Reg)
; PC <- R2
; PC <- R14 (Link Reg)
; PC <- M[x0025], Return address in R7
SVC #0x25 ; Similar in concept but not implementation
RTI
BX LR
; Pop PC and PSR from Supervisor Stack…
; PC <- R14 (Link Reg) [same as RET]
Bard, Gerstlauer, Valvano, Yerraballi
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SW Development Environment
Editor
Source code
KeilTM uVision®
Start
; direction register
LDR R1,=GPIO_PORTD_DIR_R
LDR R0,[R1]
ORR R0,R0,#0x0F
; make PD3-0 output
STR R0, [R1]
Start
Debug
Session
Simulated
Microcontroller
Processor
Memory
I/O
Build Target (F7)
Object code
0x00000142
0x00000144
0x00000146
0x0000014A
4912
6808
F040000F
6008
Address Data
Bard, Gerstlauer, Valvano, Yerraballi
Download
Real
Microcontroller
Start
Debug
Session
Processor
Memory
I/O
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