CEC 220 Digital Circuit Design
Latches and Flip-Flops
Friday, March 04
CEC 220 Digital Circuit Design
Slide 1 of 13
Lecture Outline
•
•
•
•
D Flip-Flop review
VHDL code for a D Flip-Flop
S-R, J-K, T Flip-Flops
Registers
Friday, March 04
CEC 220 Digital Circuit Design
Slide 2 of 13
Latches and Flip-Flops
Example with a Gated D-Latch
• Complete the timing diagram below for a gated D latch
 Assume that Q begins at 0
𝐷
Friday, March 04
CEC 220 Digital Circuit Design
Slide 3 of 13
Latches and Flip-Flops
• An edge triggered D Flip-Flop from gated D Latches
P & Q are
initially ‘0’
Master
Slave

𝐶𝑘
P
Q
Friday, March 04
CEC 220 Digital Circuit Design
Slide 4 of 13
Latches and Flip-Flops
VHDL Code for a D Flip-Flop
• VHDL architecture code is concurrent except for code
inside a “PROCESS” statement
process (CLK)
–- If clock changes
begin
if (CLK’event and CLK=‘1’) then –- Rising edge
Q <= D;
-- Q and QNot
QN <= not D; Statements in here
are “Sequential”
end if;
end process;
Friday, March 04
CEC 220 Digital Circuit Design
Slide 5 of 13
Latches and Flip-Flops
VHDL Code for a D Flip-Flop
Friday, March 04
CEC 220 Digital Circuit Design
Slide 6 of 13
Latches and Flip-Flops
The J-K Flip-Flop
J
0
0
1
1
• The J-K Flip-Flop
Inputs
State
Next State
J(t) K(t) Q(t) Q(t+t)
0
0
0
0
Hold
0
0
1
1
0
1
0
0
Reset
0
1
1
0
1
0
0
1
Set
1
0
1
1
1
1
0
1
Toggle
1
1
1
0
Friday, March 04
Q(t+t)
J(t)
0
1
00
0
1
01
1
1
11
0
0
10
0
1
K(t)Q(t)
Q  J Q  K Q
CEC 220 Digital Circuit Design
K
Q
0 Hold
1 Reset
0
Set
1 Toggle
Slide 7 of 13
Latches and Flip-Flops
The J-K Flip-Flop
• An example with the J-K Flip-Flop
 Assume initially Q=0
Set
Reset
Toggle
1
0
1
0
1
1
Q
Friday, March 04
CEC 220 Digital Circuit Design
Slide 8 of 13
Latches and Flip-Flops
The Toggle Flip-Flop
• The T Flip-Flop
Input
Hold
Toggle
Friday, March 04
State
Next State
T(t) Q(t) Q(t+t)
0
0
0
1
0
1
1
1
0
0
1
1
CEC 220 Digital Circuit Design
Q  T Q  T Q
Slide 9 of 13
Latches and Flip-Flops
The Toggle Flip-Flop
• An example with the T Flip-Flop
 Assume initially Q=0
Hold
Toggle
Hold
0
1
0
Toggle
1
Q
Friday, March 04
CEC 220 Digital Circuit Design
Slide 10 of 13
Latches and Flip-Flops
Flip-Flop Summary
Flip-Flop
Name
S-R
J-K
D
Flip-Flop
Symbol
S
Q
R
Q
Clk
J
Q
K
Q
Clk
Q
D
Clk
T
Q
T
Clk
Friday, March 04
Q
Q
Characteristic
Table
S R
Q++
0
0
1
1
Q
0
1
NA
0
1
0
1
J K
Q++
0
0
1
1
Q
0
1
Q
0
1
0
1
D
Q++
0
1
0
1
T
Q++
0
1
Q
Q
Hold
Reset
Set
NA
Hold
Reset
Set
Toggle
Reset
Set
Hold
Toggle
Characteristic
Equations
Q+ = S + R Q
Q++ = J Q + K Q
Q++ = D
Q++ = T Q + T Q
CEC 220 Digital Circuit Design
Excitation
Table
+
QQ
0
0
00
11
1
1
Q++
Q
SS R R
0
0
1
1
0
0
1
1
0
11
00
X
QQ
00
00
1
11
1
Q
Q+++ J J K
0 X
X
00
11
0
X 0
K
00XX
11XX
X 1
XX 0 1
X 0
00
11
0
10
1
+
QQ
0
0
00
11
1
1
+
+
QQ
D
QQ
0
0
00
111
1
+
+
QQ
T
0
0
11
00
1
0
1
0
1
1
+
0
0
11
00
1
1
0
1
1
0
D
0
1
0
1
T
0
1
1
0
Slide 11 of 13
Latches and Flip-Flops
• Fill in the timing diagram for a falling-edge triggered
S-R flip-flop.
 Assume Q begins at 0
Friday, March 04
CEC 220 Digital Circuit Design
Slide 12 of 13
Next Lecture
• Shift registers
• Counters
• State Graphs
Friday, March 04
CEC 220 Digital Circuit Design
Slide 13 of 13