Simulation Lab 3b
Introduction to VHDL – Using Multiple Components
National
Science
Foundation
Funded in part, by a grant from the
National Science Foundation
DUE 1003736 and 1068182
Acknowledgements
Developed by Craig Kief, Alonzo Vera, and Alexandria Haddad, at the Configurable Space Microsystems
Innovations & Applications Center (COSMIAC). Based on original tutorial developed by Bassam Matar,
Engineering Faculty at Chandler-Gilbert Community College, Chandler, Arizona. Funded by the National
Science Foundation (NSF).
Introduction
These labs will be using what is known as a Field Programmable Gate Array (FPGA). The FPGA will be on
a Digilent Nexys 3 board. FPGAs are different than traditional integrated circuits, because interconnects
between the gates are programmable, which means the hardware itself is configurable.
Lab Summary
This lab will be an introduction to design techniques for FPGAs using a hardware descriptive language
(VHDL) design. Xilinx ISE 14.x is the design tool provided by Xilinx for this purpose. Xilinx makes a free
version of this tool called Webpack which would be virtually identical for this purpose. The board is a
Digilent Nexys 3 board with a Xilinix Spartan 6 XC6LX16-CS324 chip. Please avoid putting your fingers
on the chips, as they are extremely electrostatic discharge sensitive.
Lab Goals
1. Create two separate components
2. Reuse those components in a third module
Learning Objectives
Understand how to create and simulate a single component. Once this is done, then two different single
components will be replicated in a third VHDL module. The resulting simulation will help understand the
process.
Grading Criteria
Your grade is determined by your instructor.
Time Required
4 - 5 hours
Special Safety Requirements
When working with electronic components, such as the Xilinx FPGA board, there is potential of
Electrostatic Discharge (ESD) hazards. Static electricity can damage the FPGA devices used in this lab.
Use appropriate ESD methods to protect the devices. No serious hazards are involved in this laboratory
experiment, but be careful to connect the components with the proper polarity to avoid damage.
Lab Preparation
 Review Lab 1-3

Print out the laboratory experiment procedure that follows.

Acquire required hardware components/equipment.
Equipment and Materials
Students should work in teams of two or three. Each team of students will need the following supplies:
Supplies
Quantity
1. ISE® Design Suite (or WebPACK™ ) software from the Xilinx website,
www.xilinx.com, if you don’t already have it installed. Your classroom should have
a full working version of Xilinx ISE® Design Suite.
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2. FPGA kit including download and power cable(s).
3. Free Digilent Adept software (instructions for download and installation are included
at the beginning of this lab):
http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,66,828&Prod=ADEPT2
Additional References
The FPGA reference manual, ISE Design Suite User Guide, Digilent Adept User Guide, and any other
supporting documents that may be of use.
Nexys 3 Reference Manuel:
http://www.digilentinc.com/Data/Products/NEXYS3/Nexys3_rm.pdf
ISE Design Suite User Guide :
http://www.xilinx.com/support/index.htm#nav=sd-nav-link-106173&tab=tab-dt
Digilent Adept User Guide:
http://www.digilentinc.com/Data/Software/Adept/Adept%20Users%20Manual.pdf
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Lab Procedure (optional): Download and install Digilent Adept Software
In this lab, you download and install Digilent Adept which allows you to communicate with the Digilent
FPGA boards that we use in lab. If Adept is already installed on your system, you can skip this Lab
Procedure.
Step 1:
Navigate your browser to http://www.digilentinc.com/Products/Detail.cfm?Prod=ADEPT2.
Figure 1. Digilent Adept Website
Step 2:
Click the Download button for Adept 2.9.4 System, 32/64-bit Windows (or latest version) and click Save
file when prompted. The installation .exe file will download to your computer.
Step 3:
When the download is complete, run the .exe file and install Adept onto your computer.
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Lab Procedure 1: FPGA Overview from Lab 1 and 2
Lab 1 Review: Xilinx Design Process overview:
Step 1: Design Entry
 Two design methods:
1. HDL (Verilog or VHDL)
or
2. Schematic drawings.
For the simulation part of our class, we will use the
schematic method and VHDL.
Step 2: Design Synthesis
 Translate VHDL and schematic files into an
industry standard format EDIF file.
Figure 2. VHDL Design Process
Lab 2 Review: Nexys 3 overview:
Step 3: Design Implementation
 Translate Map, Place and Route. This process will
generate a configuration file (.BIT) for FPGA
programming.
Step 4: Xilinx Device Programming
 Download JED file into FPGA
NOTE: We used the Digilent Nexys-3 Xilinx®
Spartan 6 XC6LX16-CS324 board.
Your board may be a different version
or from a different vendor. However,
most of the components are similar. If
you have a different board, review your
board’s documentation.
The Nexys-3 is a powerful digital system
design platform built around a Xilinx Spartan 6
FPGA. The advantage of this board is that it is
programmed and powered through a USB port.
A list of the key features and their location on
the board are shown in Figure 3.
Figure 3. Nexys 3, Spartan 6 FPGA
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User I/O
The Nexys-3 board includes several input and output devices, and data ports allowing many implementation
designs without the need for any other components. We will focus on the following inputs [slide switches,
push buttons, and reset button] and outputs [LEDs, and 7-segment display].
The five pushbuttons and eight slide switches are provided for circuit inputs. There is also a reset button.
Pushbuttons normally generate a low output when at rest, driven high when the pushbutton is pressed. Slide
switches generate constant high or low inputs depending on their position. Pushbutton and slide switch
inputs use a series resistor for protection against short circuits (a short circuit would occur if an FPGA pin
assigned to a pushbutton or slide switch was inadvertently defined as an output). Figure 4 shows the pin
assignments for each of the aforementioned inputs/outputs. Please refer the reference manual for any
additional information.
Figure 4. FPGA Button, Switch, Anode and Cathode Schematic
Original image from the Nexys3™ Board Reference Manual
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Lab Procedure 2: Reusing Components
One of the advantages of VHDL is the ability to develop and use packages of code repeatedly. Many
experienced VHDL designers develop a component to perform a specific task. They debug and rework this
component until it is perfect. Once this is done, the component can be used again and again for new
projects. This lab will be an introduction to reusing the same components in a single file using a hardware
descriptive language (VHDL) design.
We are using ISE Design Suite 14.x. ISE has the capability of implementing a variety of different design
methodologies including: Schematic Capture, Finite State Machines, and Hardware Descriptive Language
(VHDL or Verilog). ISE also provides its own simulation tool to test your designs before programming
them on the FPGA.
Step 1: Implement a Basic Gate in VHDL
There are two sections of design for this lab. The first is the VHDL program design of what the project has
to do, where the circuit in question will be implemented. We will use the Dog component shown in Figure 5
and the Cat component shown in Figure 6. The Dog component says, if you pat or feed the dog (you can do
either), the dog will bark. The Cat component says if you Water and Rub (you must do both) then the cat
will meow. We are using an OR logic gate, as discussed in Lab 3 and 3a and an AND logic gate. Although
the components are simple, the same concepts and instantiation techniques can apply to more complicated
designs.
Figure 5. Dog Component: Pat OR Feed = Barking Dog
Figure 6. Cat Component: Water AND Rub = Meow
Task A: Create a New Project
1. Open Xilinx ISE Design Tool Project
Navigator.
Your system might have slightly different
Start Menu options.
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2. The ISE Project Navigator window opens,
with the Tip of the Day displayed. Click OK
to close the Tip of the Day.
3. Start a new project by selecting File  New
Project from the menu. The New Project
Wizard starts.
a. Type LAB3b in the Name text
box.
b. Select a location on your
computer to save your project
files by clicking the ellipsis (…)
button to the right of the
Location text box.
c. Under Top-level source type,
select HDL.
d. Click Next.
The Project Settings dialog box opens.
NOTE: File names must start with a letter. Use underscores ( _ ) for readability. Do not use hyphens (-);
although the file name will work, the entity name will not. More on this later.
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4. Select Spartan-6 SP601 Evaluation
Platform from the Evaluation
Development Board drop down menu.
The Product Category, Family, Device,
Package, and Speed should all
automatically populate (top half of the
screen). You will need to set some
options in the lower half of the dialog
box.
Select VHDL from the Preferred
Language drop down menu.
The Project Settings should resemble the
figure to the right.
5. Click Next.
NOTE: The options specified are for the Spartan 6 LX FPGA. Your board might be different than the board
used for these instructions. Chip specifications are printed on the FPGA chip in the middle of the
board. The board information is also listed on the box it came in.
6. Verify the file type and name are correct
in the Project Summary then click Finish
to complete the New Project creation
process.
4. NOTE: For this project, the source files have already been created for you. You will add them to the
project. Copy the source files into the LAB3b project folder that ISE created. There are seven files
for this project: Dog.vhd, Dog_tb.vhd, Cat.vhd, Cat_tb.vhd, ManyPets.vhd, ManyPets_tb.vhd, and
ManyPets.ucf. If you don’t have the zip file you can download it from the COSMIAC website
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(http://cosmiac.org/Projects_FPGA.html). The project files are in the lab3b.zip file. We will be
adding two of the files from the lab3b.zip file to our new project. Since we’ve already covered
creating the Dog component in Lab 3a, this lab will focus on creating the Cat and ManyPets
components.
7. Using Windows Explorer, extract or move
these all five files to your project folder.
8. Select Project  Add Source from the menu
or Right-click in the Hierarchy pane and select
Add Source from the shortcut menu. The Add
Source dialog box opens.
9. Select the Cat.vhd an and Cat_tb.vhd files
that were extracted to the project directory
earlier. Click the Open button. The Adding
Source Files… dialog box opens.
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10. Click the OK button to complete the add files
process.
NOTE: All three project files display with a green
checkmark to the left of the file name.
This lets us know that ISE understands the
design association of each of the files.
11. The files are added to the LAB3b project.
Clicking the Implementation or Simulation
options displays the files that were just added.
NOTE: Refer to Labs 1 – 3 for information about
the file Hierarchy pane. Recall that when
Implementation is selected the UCF file
should be below the design file it is
associated with. When Simulation is
selected, the UUT should be under the
associated testbench file.
Task B: Run the Cat Simulation
12. Select the Simulation pane and Double-click
the testbench – testbench_arch
(Cat_tb.vhd) file name. The Cat_tb.vhd file
opens in the Workspace.
13. Select the testbench file and double-click on
the “Simulate Behavioral Model”.
14. The simulator will start and the Elaborating
status will display. Once the simulation is
complete the ISim application window will
open.
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15. Click the Zoom to Full View button
, then
click Zoom In to better view the simulation.
The resulting waveform confirms that anytime
water and rub are high, meow is also high.
16. Close the ISim Window and return to the ISE
Design Window.
Lets take a minute to look at the code we have so far. Figure 7 shows the code for the simple OR gate that
tells us what will make our dog bark.
Figure 7. Cat.vhd
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Step 2: Instantiate the Dog and Cat in one Module
17. Like in Lab 3a, we will first remove the
Cat_tb.vhd file. Right-Click on the file name
and select Remove.
18. Confirm the removal and click Yes.
19. Now add the Dog.vhd, ManyPets.vhd,
ManyPets_tb.vhd, and ManyPets.ucf files.
Use the Add files method we have used
previously. Right-click in the
Implementation Hierarchy pane and select
Add Source.
20. Select the four files, and click Open.
21. In the Adding Source Files confirmation
dialog, click OK.
NOTE: The files added can be explored. They are the dog component and the ManyPets file that calls for
an instance of dog and cat. This is the critical part. Just as dog and cat are created, verified and
used individually, any creation of a quality (and verified) component can be reused.
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22. If you click on the plus next to the PetPack –
behavioral (ManyPets.vhd) line, you will see
the instantiations of the Dog.vhd and
Cat.vhd components.
The expansion of the file hierarchy in the
Behavioral Simulation pane shows how the
ISE software believes the components are
developed. ManyPets has two identical
components called Dog.vhd and Cat.vhd.
The two instantiations are: Poodle and
Mixed.
When creating instantiations of different
components you must first declare each
component in the section after Architecture but
before the Begin. The component declaration
must have all the ports (inputs and outputs)
exactly as they appear in the Component’s
Entity Statement. You can copy and past the
Entity Statement and change the word Entity to
Component.
Next in the behavioral section, after Begin, you
“hook” up the component to the main module
using the port map statement. This simply
entails telling ISE what port signal of the
component should be hooked to which port
signal, or Architecture signal, of the Main
Module.
Each instantiation is given a unique name,
Poodle (for the dog) and Mixed (for the cat).
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Task A: Run the ManyPets Test Bench
23. Select the Simulation pane
and Double-click the
testbench –
testbench_arch
(ManyPets_tb.vhd) file
name to run the simulation
for the ManyPets module as
we have for prior modules.
24. Once the simulation is
complete the ISim
application window will
open.
25. Zoom In to better view the
simulation. When compared
to the Cat simulation, the
ability to visualize that all
three instantiations are
identical is clear. Three
identical instantiations of the
dog have been created. \
26. Close the ISim Window and
return to the ISE Design
Window.
Task B: Review the UCF (User Constraints File)
27. In the sources pane, choose Implementation.
28. Double-click the ManyPets.ucf file in the
Processes pane to review the UCF code.
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Step 3: Program to the FPGA board
As mentioned earlier, there are four distinct stages to any FPGA project: Design, Synthesis,
Implementation, and Programming. The design portion of this project is now finished. Now we can move
on to the Synthesize, Implementation, and Programming stages. We will use the Generate Programming file
option to go through all three stages at once.
Task A: Synthesize, Implement, Map, Place and Route, Generate Bitstream (.bit)
1. Insert the small end of the USB cable into the Adept
USB Port on the FPGA board. Insert the USB end into
your computer.
2. Turn on the FPGA board.
NOTE: The display may alternately flash PASS and 128 if
the board’s ROM hasn’t been overwritten from the
factory.
3. Select the ManyDog.vhd file and then, double-click
Generate Programming File.
As the program is going through the compile process
the compiling the process status icon spins and
displays the current process that is running.
The Console Panel also displays textually what is
happening.
4. Once the process has stopped running, and there are no
errors or warnings, there will be three green
checkmarks next to the Synthesize, Implement Design,
and Generate Programming File processes.
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NOTE: If you have errors or warnings you will need to find and fix the errors. You may or may not need to
fix warnings. Click the Errors (and/or Warnings) Panel tab to display a list of all errors (and/or
warnings) (1).
Clicking the hyperlink (2) of a particular Error (or Warning) will take you to the file and line (3) of
the Error (or Warning). Note in the example the semicolon is missing at the end of line 37.
Clicking the hyperlink word Error (4) (or Warning) will display context sensitive information about
the particular error/warning.
After fixing any errors, re-generate the programming file. To re-generate the programming file,
right-click on Generate Programming File and select Rerun All.
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Task B: Implement design to FPGA board
Finally, we will start the “Digilent Adept” program. Adept is the software provided by Digilent that allows
us to communicate through the JTAG chain to the programming pins on the FPGA. Because the FPGAs we
are working with use a single USB cable for power and PC connection we need to use Digilent Adept to
transfer the .bit code to the board.
1. Open Digilent Adept by selecting
Start  All Programs Digilent
 Adept  Adept.
NOTE: Your system might have
slightly different Start Menu
options.
2. Choose Nexys3 from the Connect
Product drop down menu.
NOTE: If you do not see Nexys3 as an
option, check the USB
connection to ensure the board
is connected to the computer.
3. Click the Browse button. The
Open dialog box displays.
4. Navigate to the folder of the
Full_Adder project and select the
full_adder.bit file.
5. Click the Open button. The file is
displayed in the dropdown list
next to the FPGA icon.
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6. Click the Program button. The bit
file is programmed to the FPGA
board. The green status bar at the
bottom of the Adept screen
displays the status as the chip is
programmed.
7. The program gets downloaded to
the FPGA board.
8. Test the FPGA by sliding the
programmed switches ON (up
toward the middle of the board)
and OFF (down toward the edge
of the board). The LED0 and
LED1 should light according to
the truth table.
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VHDL Code – SingleDog
--VHDL files contain three parts: library declarations, entity and
--behavior. The library describes what each function will do. Entity
--describes the inputs and outputs. Behavior is the working
--portion of the project.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Declaration of the module's inputs and outputs
-- for part 1 of Lab3a
entity Dog is port (
pat: in std_logic;
feed: in std_logic;
bark: out std_logic
);
end Dog;
--Defining the modules behavior
Architecture behavioral of Dog is
begin
process (pat, feed) begin
bark <= pat OR feed;
end process;
end behavioral;
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VHDL Code – ManyDogs
--VHDL files contain three parts: library declarations, entity and
--behavior. The library describes what each function will do. Entity
--describes the inputs and outputs. Behavior is the working
--portion of the project.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--Declaration of the module's inputs and outputs for part 1 of tutorial 2
entity dogPack is port (
dog1_Pat: in std_logic;
dog1_Feed: in std_logic;
dog1_Bark: out std_logic;
dog2_Pat: in std_logic;
dog2_Feed: in std_logic;
dog2_Bark: out std_logic;
dog3_Pat: in std_logic;
dog3_Feed: in std_logic;
dog3_Bark: out std_logic
);
end dogPack;
--Defining the modules behavior
Architecture behavioral of dogPack is
component Dog is port (
pat: in std_logic;
feed: in std_logic;
bark: out std_logic
);
end component Dog;
begin
Poodle : Dog
port map (
pat
=> dog1_Pat,
feed => dog1_Feed,
bark => dog1_Bark
);
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Chow : Dog
port map (
pat
=> dog2_Pat,
feed => dog2_Feed,
bark => dog2_Bark
);
Collie : Dog
port map (
pat
=> dog3_Pat,
feed => dog3_Feed,
bark => dog3_Bark
);
end Behavioral;
VHDL Testbench -- ManyDogs
--This is a VHDL testbench. It is used to stimulate the inputs to
--file we are testing. A good design practice is to create a testbench
--for each component you are developing. Test each component separately
--before combining them.
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;
USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE STD.TEXTIO.ALL;
ENTITY testbench IS
END testbench;
ARCHITECTURE testbench_arch OF testbench IS
COMPONENT dogPack
PORT (
dog1_Pat: in std_logic;
dog1_Feed: in std_logic;
dog1_Bark: out std_logic;
dog2_Pat: in std_logic;
dog2_Feed: in std_logic;
dog2_Bark: out std_logic;
dog3_Pat: in std_logic;
dog3_Feed: in std_logic;
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dog3_Bark: out std_logic
);
END COMPONENT;
--develop signals to stimulate
SIGNAL dog1_Pat : std_logic := '0';
SIGNAL dog1_Feed : std_logic := '0';
SIGNAL dog1_Bark : std_logic := '0';
SIGNAL dog2_Pat : std_logic := '0';
SIGNAL dog2_Feed : std_logic := '0';
SIGNAL dog2_Bark : std_logic := '0';
SIGNAL dog3_Pat : std_logic := '0';
SIGNAL dog3_Feed : std_logic := '0';
SIGNAL dog3_Bark : std_logic := '0';
--UUT means unit under test
BEGIN
UUT : dogPack
--map signals on right to entitys on the left
PORT MAP (
dog1_Pat => dog1_Pat,
dog1_Feed => dog1_Feed,
dog1_Bark => dog1_Bark,
dog2_Pat => dog2_Pat,
dog2_Feed => dog2_Feed,
dog2_Bark => dog2_Bark,
dog3_Pat => dog3_Pat,
dog3_Feed => dog3_Feed,
dog3_Bark => dog3_Bark
);
signal_Pat: process
begin
dog1_Pat <= NOT dog1_Pat;
dog2_Pat <= NOT dog2_Pat;
dog3_Pat <= NOT dog3_Pat;
wait for 1 ns;
end process;
signal_Feed: process
begin
dog1_Feed <= NOT dog1_Feed;
dog2_Feed <= NOT dog2_Feed;
dog3_Feed <= NOT dog3_Feed;
wait for 2 ns;
end process;
END testbench_arch;
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User Constraints File (UCF)
NET "dog1_Pat"
NET "dog1_Feed"
NET "dog1_Bark"
NET "dog2_Pat"
NET "dog2_Feed"
NET "dog2_Bark"
NET "dog3_Pat"
NET "dog3_Feed"
NET "dog3_Bark"
LOC = "T10";
LOC = "T9";
LOC = "U16";
LOC = "V9";
LOC = "M8";
LOC = "V16";
LOC = "C4";
LOC = "D9";
LOC = "U15";
#SW0
#SW1
#LED0
#SW2
#SW3
#LED1
#BTN L
#BTN R
#LED2
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