MicroTESK: An ADL-Based
Reconfigurable Test Program
Generator for Microprocessors
Alexander Kamkin, Andrey Tatarnikov
{kamkin, andrewt}@ispras.ru
Institute for System Programming of the Russian Academy of Sciences (ISPRAS)
http://hardware.ispras.ru
Design and Verification of Microprocessors
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Hardware Description Languages (HDL)
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Verilog
VHDL
Architecture Description Languages (ADL)
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nML
Sim-nML
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Levels of Microprocessor Verification
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Unit-Level (via Input and Output Signals)
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Core-Level Verification (via Test Programs)
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Approaches to Test Program Construction
Design
Requirements
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?
lui s1, 0x2779
ori s1, s1, 0x0
lui s3, 0x4ee
ori s3, s3, 0xf
add v0, a0, a2
sub t1, t3, t5
add t7, s1, s3
Test Programs
Manual Development
Random Generation
Template-Based Generation
Advanced Model-Based Generation
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Constraint-Based Test Program Generation
Input Values
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Constraints
(Invariants)
Output Values
(Test Data)
Features:
Context-Independent Solver Engines (e.g. Z3)
Flexible Language (SMT-LIB)
Rich Set of Supported Theories
Benefits:
Less Effort to Create Tests
Better Coverage
Less Testing Bugs
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Evolution of Test Program Generators
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Generator for a Particular Microprocessor
Model-Based Generator
 Generation
Core
 Microprocessor Model
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Instruction Set Model
Testing Knowledge
Reconfigurable Model-Based Generator
 Generation
Core
 Microprocessor Description/Configuration
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Motivation of the Project MicroTESK
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Reduce Effort Needed to Switch to New Designs
Simplify Development of Test Cases
Main Requirements:
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It should be easy to change the instruction set:
 add/remove microprocessor instructions
 modify instructions’ semantics
It should be easy to change microarchitectural properties:
 cache memory configuration
 address translation algorithm
It should be able to generate test programs automatically according
to high-level parameters
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General Structure of MicroTESK
MicroTESK
Specifications
(ADL, Configuration)
Modeling
Engineer
Engine
Libraries
Model
ADL Translator
Model API
Design Model
(Instruction Set,
Resources)
Test Template
Generator
Basic TK
Testing
Knowledge
Test Program
Generator
CSP Solver
API
Test Templates
Testprograms
programs
Test
Test
Programs
CSP Solver
Testtemplates
templates
User–Defined
Test
Test Templates
Verification
Engineer
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Architectural Description (nML/Sim-nML)
op ADD(rd: GPR, rs: GPR, rt: GPR)
Test Template
action = {
if(NotWordValue(rs) || NotWordValue(rt)) then
UNPREDICTABLE();
ALU r(), r(), r(); Precondition
endif;
ADD R, r(), r();; default;
tmp_word = rs<31..31>::rs<31..0>
SUB +r(), R, r();; overflow;
rs<31..31>::rt<31..0>;
if(tmp_word<32..32> != tmp_word<31..31>) then
SignalException("IntegerOverflow");
else
Test Situations
rd = sign_extend(tmp_word<31..0>);
endif;
}
syntax = format("add %s, %s, %s",
rd.syntax, rs.syntax, rt.syntax)
op ALU = ADD | SUB | ...
Equivalence Classes
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Memory Configuration
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Buffer Configuration
Test Template
Buffer associativity
Number of rows LD
in a r(),
buffer 0x0, r();; hit(TLB, loaded::PFN1);;
miss(L1);; hit(L2);
Structure of data item (fields and their size)
...
Index function that
the position
data by itsloaded::PFN2);;
address
SDcalculates
r(), 0x0,
r();; of
hit(TLB,
Predicate checking whether
it is hit or miss
equals(PFN1,
PFN2);; hit(L1);
Data displacement strategy
buffer L1 = {
set = 4
length = 128
line = { tag:card(27), data:card(32) }
index(addr:36) = { addr<8..2> }
match(addr:36) = { addr<35..9> == tag<0..26> }
policy = LRU
}
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Constraints
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Preconditions
(define-sort
DWORD64
() (_ BitVec 64))
Possible
Value
Ranges
(define-fun
INT_ZERO () DWORD64 (_ bv0 64))
Value
Dependencies
(define-fun INT_BASE_SIZE () DWORD64 (_ bv32
Pseudorandom
Values
(define-fun INT_SIGN_MASK () DWORD64
64))
(bvshl (bvnot INT_ZERO) INT_BASE_SIZE))
(declare-const rs DWORD64)
(define-fun IsValidPos ((x!1 DWORD64)) Bool
(declare-const
rt DWORD64)
(ite (= (bvand x!1 INT_SIGN_MASK) INT_ZERO)
true false))
(define-fun
IsValidNeg ((x!1rs))
DWORD64)) Bool
(assert
(IsValidSignedInt
(= (bvand x!1 INT_SIGN_MASK) INT_SIGN_MASK) true false))
(assert (ite
(IsValidSignedInt
rt))
(assert
(not (IsValidSignedInt
rt))))
(define-fun
IsValidSignedInt ((x!1 (bvadd
DWORD64))rs
Bool
(assert (ite
(not(or(=(IsValidPos
rs rt)))x!1) (IsValidNeg x!1)) true false))
(check-sat)
(get-value (rs rt))
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Test Templates
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Preconditions
Whole Class of Values
Custom Sequencing
Combinatorics
class MyTemplate < Template
def test()
data = [ [0xEF, 0xFF], [0x1EF, 0x1FF], [0xFEF, 0xFFF] ];
data.each { |d|
xor r0, r0, r0;
ori r(2), r0, d[0];
ori r(4), r0, d[1];
ld tmp1=r(1), 0x0, r(2);; hit([L1(), L2()], [25, 50, 75]);
ld tmp2=r(3), 0x0, r(4);; hit([L1(), L2()], [25, 50, 75]);
dadd r(5), tmp1, tmp2;; overflow;
}
end
end # class MyTemplate
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Conclusion
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Adapting the Model-Based Testing Approach
for Verification Engineers
 Domain-Oriented

Languages
Handling Frequent Design Changes and
Maintenance of the Models
 Easy-to-Modify
Specifications / Configurations
 Push-Button Test Generation Techniques
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Thank You!
Questions?
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