MURALI.
Contact No: +91-958-101-4767
Email: amurali3@gmail.com
Objective:
Skilled Digital Hardware Design and Verification Engineer with 3.5 years. Seeking a Challenging
Position in Digital FPGA and ASIC Design, Development, Verification or Test in a State of the
Art Technology Leading Company. Open to Relocation and Travel.
Summary:
 Currently associated with NANO SCIENTIFIC RESEARCH CENTRE Pvt. Ltd.,
Hyderabad as Digital Design Engineer.
 Systematic Design from Behavioral/RTL Modeling, Design, Implementation, Verification,
Simulation, Synthesis and FSM based design.
 Good understanding of the ASIC and FPGA design flow and Digital Design
 Proficient in RTL design, Behavioral simulation and synthesis, Implementation using Xilinx
ISE, Plan Header, Chip scope pro analyzer.
 Strong fundamentals in Digital circuit Design, State Machine Design and VLSI design flow.
 Expertise in Communication and Bus Protocols such UART, SPI, I2C, Router,
 Knowledge on AMBA Bus Protocol.
 Proficient in RTL design, simulation and synthesis using Xilinx ISE.
 Specs to RTL coding, proficient in both Verilog and VHDL. Very efficient in converting specs
to RTL, supported by strong background in digital logic design.
 Good knowledge in verification on test benches using Verilog HDL
 Experienced with Lab Equipments such as Altera FPGA Cyclone-II DES FPGA Board,
SPARTAN series and VIRTEX series FPGA Board
 CMOS circuit design and Simulation. Cell level layout design, DRC LVS using Magic Layout.
 Knowledge in CMOS VLSI design.
 Embedded C programming, VxWorks.
 Result oriented with strong analytical, problem solving, and communication skills.
 Self-driven and has the ability to work independently.
Skill Set:
Programming Languages
EDA Simulation Tools
FPGA Design Flow Tool
Mask Layout
Bus Architecture Protocols
Scripting Language
Web Technologies
Operating Systems
:VerilogHDL, VHDL, Matlab, C, System Verilog (Exposure)
: Modelsim, Questasim and ISE, Quartus II
: Xilinx ISE Series
: MAGIC Layout Editor, Micro wind, DSCH3 Schematic
: I2C, SPI, USB2.0, Router, AMBA
: Basics of Perl Scripting
: HTML
: Windows family, Linux
Work Experience:
 Currently working as a Sr. Design Engineer with Nano Scientific Research Centre Pvt Ltd,
Hyderabad Since Nov’ 2011.
 Worked as S/W Testing Engineering at Electronics Arts Inc from May 2004 to July 2007
Educational Qualifications:
 M.Tech. Microelectronics and VLSI Design. from IIT Madras, Chennai.
 B.Tech (ECE) from Nagarjuna University, Guntur, Andhra Pradesh.
Project Profile
Project # 1 : :
I2C Protocol
Description
This project is to design a I2C protocol with single master and three slaves RTC, two
EPROM of 2kbytes block should be communicated with processor communication
Myrole
 Complete Design is developed in Verilog
 Developing the Control sub module and test bench modules.
 Coding, Unit Testing and Code reviews.
 EDA tool used is Xilinx ISE 12.2i
 Conducting debugging with chipscope pro with FPGA implementation.
 Delivery documents, Implementation support.
Project #2:
Project
:
Serial Peripheral Interface (SPI)
Description:
SPI is a synchronous protocol that allows a master device to initiate Communication with
Exchanged between these devices. It allows communication between two or more devices at a high
speed.
Myrole:
 Complete Design is developed in Verilog
 Architectural design,
 Test bench writing.
Project #3:
Project
:
1X4 port network Switch verification
Description
This project is design and verification of a 4port switch for network routing between
different co-processors application.
Myrole
 Developed arbiter module, memory module, in verilog
 verification is done using Verilog
 simulator used is Questasim
Project #4:
Project
:
PCI Interfacing Module
Description
This project PCI Arbiter core is used to efficiently manage access to a PCI bus that is
shared by several masters. Access to the PCI bus is automatically determined by the individual
priorities of each master, Cover the functionalities of read and write operations in the memory
with the concepts of FIFO modules. It is a 32 bit.
Myrole
 Developed arbiter module, memory module, test bench modules in Verilog
 Unit Testing and Code reviews.
 EDA tool used is Xilinx ISE
Scholastic Achievements:
 Scored 99.98 percentile in GATE 2007 (All India 18th Rank).
 Qualified Faculty Eligibility Test (FET-2010) conducted by JNTU Hyderabad.
 Published and Presented 13 papers at National/International Conferences and
International Journals.
Major Strengths
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Strong determination to succeed
Highly organized - can priorities work schedules, manage time effectively and meet deadlines
Resourceful, proactive and have initiative
Quick learner and hardworking.
Murali.A