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Ryan Loos
Everistus Obiakor
Alex Toombs
IC Fabrication
10/26/12
Lab Report
Wafer Characterization
Before anything else was to be done, the first step was to characterize each of the six
provided wafers. In order to do this, we used the Veeco FPP 5000 four-point probe (see Figure 1
below). Additionally, from the resistivity, we can calculate the doping of the wafer. Before
testing the resistivity, we set the device for a wafer thickness of 620 microns. Before putting our
wafers into the chuck, we wiped the rim with a dry clean room wipe to ensure there were no
particles that might damage the wafer. Then, we assembled the chuck with the wafers face-down
against the probe, and held the device lid down while the resistivity and doping type were
measured. Our results are tabulated in Table 1 below.
Figure 1 - Veeco FPP 5000 Four-Point Probe, Lid Open, Chuck In
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Table 1 - Wafer Resistivity and Type
Wafer Number
Wafer Type
Wafer Resistivity (Ohms per centimeter)
1
p
1.556x10^1
2
p
1.390x10^1
3
p
1.151x10^1
4
p
1.172x10^1
5
p
1.134x10^1
6
p
1.374x10^1
Using graphs in the textbook (Wolf 30), we were able to calculate doping concentration,
assuming Boron-doped substrate. The results of that are listed in Table 2 below.
Table 2 - Wafer Doping Concentrations
Wafer Number
Doping Concentration (carriers per cubic centimeter)
1
9.1x10^14
2
1.2x10^15
3
1.4x10^15
4
1.4x10^15
5
1.4x10^15
6
1.2x10^15
Alignment Mark Lithography and Etch
After characterizing each wafer, the next step was to RCA clean the wafers, since they
had not been cleaned before. The baths were fresh enough that we only had to spike them all
with 200 mL hydrogen peroxide. This involves loading each wafer into a special cassette on the
MOS clean bench, and then bathing all six in a solution of hot acids, hot bases, and more acids
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(piranha, RCA1, RCA2) in order to remove each type of particle that could contaminate the
wafers. They also had a shorter dip in HF to etch any oxide and remove anything else.
We had an issue wherein the vacuum of the photoresist spinner appeared to malfunction,
giving us an error. When they worked once more, we returned to prepare the wafers for
lithography. This first involved exposure to HMDS, an adhesion agent that helps photoresist
adhere to silicon wafers. During this, we made the mistake of disposing of old HMDS into the
caustic hood, which we immediately notified lab staff of. When the wafers had been exposed
and remove, we then applied photoresist. Specifically, we applied the SR 700-1.2 photoresist,
contained in the yellow cabinet. For each wafer, we used approximately three quarters of a
disposable pipette full, dispensing it on the direct center, and spinning using the ICFAB recipe
on the spinner. After spinning wafer 1, we noticed some streaking and/or discoloration on wafer
1, enough to cause us to use the PVA PS 210 10 minute recipe to remove the photoresist and try
again. We scratched wafer 4’s photoresist coating when trying to replace it in the box, and it was
also stripped in the PVA and re-spun. The resist spinner we used to spin photoresist can be seen
below in Figure 2.
Figure 2 - Used Photoresist Spinner Before Being Cleaned
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After each wafer was spun, they were baked on a hotplate at 90 C for approximately one
minute. A wafer can be pictured on the hot plate in Figure 3 below.
Figure 3 - Wafer on Hot Plate, After Bake
Now that the wafers had photoresist spun, the next part of the procedure was to use the GCA
AutoStep 200 Stepper. After logging in, we loaded each wafer onto the chuck, using the
alignment notch and left-hand side to hold it against the pin before the chuck vacuum was
switched on. The command used for the alignment mark lithography was EXEC IC0\1. Each
wafer was exposed, removed, placed into developer solution, and held there for 45 seconds
before receiving an extensive rinse and a nitrogen dry.
After lithography, we kept the photoresist on in order to etch the alignment marks into the
substrate. To do this, we used the Plasma Therm 790 Reactive Ion Etching system, or RIE. This
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involved using an O2 clean followed by a CF4 etch to season the chamber. However, the first
time we attempted to pump down the chamber after loading two wafers onto the puck, (loading
is pictured in Figure 4 below) the RIE would not pump below 45 mTorr. After trying again,
eventually a grinding sound was heard, and that was that for the turbo pump.
Figure 4 - Loading Wafers into RIE Puck for Etching
When the RIE was finally fixed, we performed and O2 clean and seasoned the
chambers. Then, we etched the alignment marks into each wafer, using the recipe IClayer_0 for
1 minute and 30 seconds per group of wafers. The recipe is as follows:
3.8 O2
26.2 CF4
Throughout the process, the pressure varied between 54 and 67, the power stayed at 250,
ref spiked from 0 to 24 occasionally, and DC ranged between 0 and 500. Each wafer was etched,
even though the RIE pump could not pump below about 38 mTorr. The wafers were then
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inspected under the microscope. An example alignment mark etch can be seen below in Figure
5.
Figure 5 – Alignment Mark Lithography for Wafer 2, 10x
Before our oxidation, we stripped the photoresist using the PVA once more.
First Oxide
Once more, we RCA cleaned the wafers, spiking each bath with 200 mL hydrogen
peroxide before doing so. Now, we removed the clean pig carefully, placing it into the MOS
clean bench. The wafers are RCA cleaned and stripped of photoresist before any furnace run
takes place to prevent contamination. Our wafers were loaded carefully into the pig, which was
then loaded into furnace tube 2. While the furnace heated up, we slowly pushed our wafers
down into the end of the tube. For this, we used the long push rod. The recipe for this oxidation
is the IC_FirstOxide recipe, which is as follows:
Temp: 950 C
Time: 45 min. Dry O2
Time: 30 min. High N2
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The oxidation can be seen on the left-hand side of Figure 6 below. After the furnace run
ended, we waited for the tube to cool to 750 C before removing the wafers from the
furnace. During this time, the ‘Unload’ step was running. They were then left to cool for about
half an hour in the pig, seen on the right hand side of Figure 6.
Figure 6 - First Oxidation; Wafers Cooling after Oxidation
N-Well Implant Lithography
After the wafers were cooled, we brought them back over to the spinner bench, as seen in
Figure 2. The next step was to spin photoresist again and expose the next mask onto the
wafers. During the transport of the wafers into the HMDS evaporator, the embrittled wafer 2
broke at the top, removing the alignment mark. The damage can be seen below in Figure 7.
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Figure 7 - Broken Alignment Mark on Wafer 2
Despite the broken notch, we still proceeded with spinning photoresist and even aligning
the wafer. All six wafers were exposed, with the broken wafer being very carefully aligned,
manually. The alignment for the stepper involved doing our best to center the chuck in the
stepper, allowing it to look for the already-etched marks in the substrate. We could fine-tune
how close it was by rotating the part of the stepper that contained the chuck, or moving it in the x
and y directions. When each wafer was done, we inspected it in the microscope and took some
pictures. These pictures are outlined in Figures 8 through 11 below.
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Figure 8 - Wafer 1, N-Well Lithography, 10x
Figure 9 - Wafer 2, N-Well Lithography, 10x
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Figure 10 - Wafer 3, N-Well Lithography, 10x
Figure 11 - Wafer 6, Resolution Test Pattern, 10x
Some blurriness was evident across wafer 1, showing it slightly out of focus. Alignment
mark etches were very clear. After this lithography, our wafers were sent out for their first
implant. The remaining photoresist served as the mask.
N Well Drive-In
First step before next oxidation was to remove the photoresist. Despite some difficulties
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with Coral, we were able to remove the photoresist of all six wafers at once using the IC clean 10
minute recipe.
There were some major technical difficulties with this oxidation. First, Coral was still
not working the next day. After we were able to enable the MOS clean bench another way, it
turned out that the piranha waste tank was full and we had to mix new baths for all three. The
heater for RCA2 was also not working. To get wet oxidation at such a high temperature, we
need an H2 torch, which was also broken. Eventually, everything was mostly worked out, and
our wafers proceeded to be processed.
In the same way as the first oxide, we loaded the wafers carefully into the boat, avoiding
touching the glassware. Touching the glassware requires that it be washed in hydrofluoric acid
once more, which isn’t fun. The recipe for this oxidation, once we had loaded the wafers into the
furnace tube, was IC_Nwell. The recipe is as follows:
Temp: 1200 C
Time: 2 min. Dry O2
Time: 120 min. High N2
Following the same procedure, we waited until the wafers were cooled enough to slowly remove
them from the furnace tube. They then cooled on the ground, and were soon ready for an
implant.
Active Layer Lithography, Etch, and Channel Stop Implant
We received our wafers back, and the first thing noticeable was a blue color on
them. The color is shown in Figure 12 below.
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Figure 12 - Wafers Returned with Blue Color
First part of the procedure was to deposit silicon nitride onto each wafer using the Unaxis
PECVD. This tool allows up to four wafers in at a time for deposition for materials onto their
surfaces. We loaded the first three wafers into the chamber, sealed it, and ran the sinxb
process. The first part of this was to wait for the substrate temperature to heat up to 350 C,
which took about 20 minutes. Then, we selected a process time of 6 minutes. The first run of
the process took about 25 minutes. We noted a heat exchange of 60 C and a substrate temp of
250 C. After cooling down, we opened the chamber and removed the wafers, placing another
three into the PECVD. The monitor display while the process is running is shown in Figure 13
below. After we were done, we ran a clean and season in order to better prepare the machine for
the next user.
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Figure 13 - PECVD Display during Sinxb Deposition Process
The wafers were then taken back to the spinner bench and more photoresist was
applied. Two wafers had streaks from solids in the photoresists, so we ran them both in a 10
minute PVA clean before re-applying photoresist. Each wafer went through the stepper, this
time with the IC12_ACT reticle. Our exposure was done by entering MAP
ACTIVE\RDFAS. As per a class suggestion, and our own experience, we had better results with
RDFAS over LDFAS. After exposing each wafer, we developed and dried them, then examined
each under the microscope. Wafer 1 had some issues with resolution across the whole wafer. As
shown in Figure 14 below, under the same microscope height and focus, opposite sides of the
wafer were blurry.
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Figure 14 - Wafer 1, Two Sides, Same Focus and Height, 10x
Wafer 2 was largely okay, even under 20x resolution. The comparison between sides can
be seen in Figure 15.
Figure 15 - Wafer 2, Two Sides, Same Focus and Height, 20x
We took a picture of the edge where the alignment notch broke off, shown in Figure 16
below.
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Figure 16 - Wafer 2, Former Alignment Mark
Wafer 3 had clear focus across the wafer, but many dust particles. The best example of
this is shown in Figure 17.
Figure 17 - Wafer 3, Dust Particles
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These particles did not appear to be on the scope itself. Wafer 4 was very clear, as Figure
18 shows. It showed even resolution across the whole surface.
Figure 18 - Wafer 4, Resolution Test Pattern, 20x
Wafers 5 and 6 also appeared to be largely in focus across the whole surface. Wafer 5 is
likely the most clear, while wafer 1 is the least. The wafers were taken to the PVA and
descummed with the Faraday cage inside.
The next step was to etch the recently lithographed marks into the nitride. Before etching
our wafers, however, we ran the IC_nitrd process with just the empty puck in the chamber. This
was to prepare the chamber for our wafer etching. After, the first two wafers were loaded into
the chamber, as shown in Figure 19 below. After nitride deposition, the wafers appeared green.
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Figure 19 - Loaded wafers into the RIE for Nitride Etching
Each wafer was sequentially etched and removed. The only thing of note was that wafer
3, while appearing clean before the etch, came out with streaks all over the surface. The
streaking is shown in Figure 20 below.
Figure 20 - Wafer 3, Strange Post-Etch Pattern
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This pattern is on the same wafer we noted as being dirty after the active area
lithography. The wafers were stripped of photoresist once more in preparation for the LOCOS
field oxidation.
Field Oxidation
Now that the channel stop implant is complete it is time for the LOCOS field oxidation.
The first step in this process is to remove the photoresist from the wafers. This is done by
putting the wafers into the PVA and running the ICFab_10min recipe. After the wafers have had
the photoresist removed, they are ready for an RCA clean. After the wafers have gone through
the RCA clean, they are ready to be loaded into the pig. In Figure 21 below, the picture on the
left shows our wafers in the pig before being loaded in the furnace and the picture on the right
shows them oxidizing in the furnace.
Figure 21 - Wafers Loaded and Running in Furnace for LOCOS Field Oxidation
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After the wafers are loaded it is time to begin the oxidation. The recipe used on the
furnace for the LOCOS field oxidation is the IC_FieldOxide recipe. This recipe calls for a
furnace temp of 1100˚C starting with a 10 min. dry oxidation, then a 70 min. wet oxidation, and
finally a 30 min. Dry O2. Looking at Figure 1 below, the top portion shows what the wafers
currently look like before being loaded into the furnace. The nitride layer will act as a mask so
the only place the oxide will grow on the actual surface of the wafers is in the gaps where the
silicon layer is exposed. The purpose of growing the field oxide is so it acts as an insulator
between MOSFETs which is accomplished by growing an oxide that penetrates the surface of the
wafer so the Si-SiO2 interface ends up below the Si surface. After the wafers are done with the
field oxidation, they should look like the bottom portion of Figure 22 below.
Nitride
Nitride
Figure 22 - LOCOS Field Oxidation Cross-Section
Once the furnace run is completed, the wafers are unloaded from the furnace and placed
back in our boxes. Then using Filmetrics, the thickness of the wafers should be measured and
should at least be 0.3µm or the oxidation will have to be completed. Our measured thickness
was 0.4µm. The next step now is to remove the nitride from the wafers.
Nitride Removal and Threshold Adjust
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Once the LOCOS field oxidation is complete, the next step is to remove the nitride layer.
The first step is to make sure the phosoporic acid bath is at the correct level and add more if
needed. The acid should be heated up to 165˚C before you begin. The next step is to remove the
oxide that has grown on top of the nitride during the field oxidation. In order to etch the oxide,
the wafers were placed in the 10:1 buffered HF bath for 15 secs and then rinse them in QDR for
two cycles. Once the oxide is removed, it is time to remove the nitride. The nitride is removed
by placing the wafers into the phosoporic acid bath for 1-3 hours until all the nitride is removed.
After all the nitride is removed, the wafers will look like Figure 23 below with oxide as the top
layer.
Figure 23 - Wafers after Nitride Removal
After all the nitride is removed, the wafers can be removed from the phosphoric acid bath
and rinsed of with DI water and placed in the QDR for two cycles. Then the wafers are dried
and placed back in our boxes. Finally we measured the thickness of our field oxide to be 0.3µm.
Now the wafers are ready to send out for the threshold adjust implant.
Gate Oxide
After the wafers come back from the threshold adjust implant, it is time for the gate
oxidation. The first step of the gate oxidation is to etch the wafers in the 10:1 buffered HF for 45
secs. to remove the pad oxide from the active areas. This is done because pad oxide is an older
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oxide and we want to grow a nice new oxide for the gate oxide. Next, the wafers are put through
an RCA clean. After that they are ready to load in the furnace.
The furnace recipe used for the gate oxidation is the IC_GateOxide recipe. The
temperature of the furnace is set to 950˚C, beginning with a 3 min. Dry O2, followed by 20 min.
Trans LC, then a 3 min. Dry O2, and finally a 20 min. High N2 (Anneal). The purpose of this
oxidation is to grow a nice oxide on the gate of the MOSFETs to serve as a dielectric. After the
wafers are done they should look like Figure 24 below.
Figure 24 - Wafers after Gate Oxidation
After the furnace run is completed, the wafers are removed from the furnace and then the
thickness of the gate oxide is measured using the ellipsometer. The thickness of or wafers were
measured at 19.1nm when it was supposed to be 20nm which was acceptable. Now the gate
oxidation is complete, it is time to deposit polysilicon on the wafers.
Polysilicon Gate
The first step in creating the polysilicon gate was to send the wafers out for deposition of
polysilicon and implant. When the wafers came back, they had a 200nm layer of polysilicon.
The next step in the process is to do the poly lithograph. First, apply SPR 700-1.2 photoresist to
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the wafers. The after the photoresist has been applied it is time to put the wafers in the stepper
for the lithography. The reticle used for the Poly layer is the IC12_Poly reticle and the program
is MAP POLY\RDFAS. RDFAS is used instead of LDFAS because the RDFAS marks have
been working better for aligning the wafers. For this lithography, align to the alignment mark
from the active layer. Once the wafers are aligned expose the wafers. After they have been
exposed the need to be dipped in the developer for 50 secs. to develop the photoresist. The
wafers should be post baked for 1 min. at 100˚C. After this, use the Alpha-Step 500 to insure the
resist is at least 1µm thick. The thickness is very important for this step because for the poly
etch, ideally you want to end up etching through all the poly and end in the oxide layer and not
go too deep into substrate if you end up etching past the oxide layer.
After you confirm the thickness of the photoresist, now it is time for the poly etch in the
RIE. The first step is to season the chamber if it is not already seasoned. To do this run the
o2cleanprocess and then the ICpoly process for 10 mins. without the wafers inside. After the
chamber is seasoned, load the wafers into the RIE two at a time. The etch time is 2:30. Make
sure to pay attention to wafers and look at the color afterwards to make sure they look about the
same as they did after the gate oxidation step so you know all the poly has been etched away.
The polysilicon that is left under the photoresist will serve as the gate contact. In Figure 25
below, (a) shows what the wafers looked like after gate oxidation and (b) shows what they
should look like now that the polysilicon has been deposited etched properly.
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Figure 25 - Wafers before and after Poly gate is added
Once all the wafers have been etched, they can be placed back in the box. They are now
ready for the N-select lithography.
N-Channel Source-Drain
The first step of the N-select lithography is to remove the leftover photoresist from the
poly etch. This is done by placing the wafers in the PVA and running the ICFab_10min recipe.
After the wafers are done, load them into the photoresist spinner and apply SPR 700-1.2
photoresist. Once the photoresist has been applied, load the wafers one by one into the stepper.
For this lithography, use the IC12_NSEL reticle and the MAP NSEL\RDFAS program. After
the wafers are aligned expose the wafers. Then take them out of the stepper and develop them in
the developer and dry them off. Now the wafers can be placed back in the box and are ready to
ship out for implant of the N dopants which it this case is phosphorus. Figure 26 below shows
what the wafers look like during implant of the N dopants.
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Figure 26 - Wafers during N-dopant implant
After the wafers have been doped and sent back to our lab, the next step is the P-select
lithography.
P-Channel Source-Drain
P-select lithography starts by removing the leftover photoresist from the N-select
lithography. This is done by placing the wafers in the PVA and running the ICFab_10min
recipe. Since the photoresist has undergone a high dose implant, it may take longer than usual to
remove the photoresist on the wafers. After the wafers are done, load them into the photoresist
spinner and apply SPR 700-1.2 photoresist. Once the photoresist has been applied, load the
wafers one by one into the stepper. For this lithography, use the IC12_PSEL reticle and the
MAP PSEL\RDFAS program. After the wafers are aligned expose the wafers. Then take them
out of the stepper and develop them in the developer and dry them off. Now the wafers can be
placed back in the box and are ready to ship out for implant of the P dopants, which in our case is
boron. Figure 27 below shows the wafers undergoing implant of the P dopants.
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Figure 27 - Wafers undergoing P dopant implant
Once the wafers come back from implant, they will remain in house the rest of the time.
Now it is time for the implant activation step.
Source-Drain Implant Activation
Before all this is done, the photoresist on the wafers have to be removed thoroughly
because of the high dose of implant they earlier received and then gone through an RCA bath.
This is the source-drain where we try to activate the n-select and the p-select implants at
the same time; the wafers are also oxidizing at the same time. This is done in the furnace at about
950o C and the program runs for about 15 minutes (2 minutes for the dry oxygen and 13 minutes
for the high nitrogen anneal). When the temperature drops (to below 800o C), then the wafers can
be slowly removed from the furnace. Then they are let to cool for about half an hour before they
are unloaded from the boat.
Interlevel Dielectric
The first step here is to deposit a layer of silicon dioxide (about 300nm) on the wafers
using the PECVD. This dielectric acts as a ‘sacrificial layer’ or planarization layers for the
processes that follow.
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Figure 28 - Cross-section of the dielectric for interlevel dielectric reliability measurements.
We then apply photoresist and then do photolithography on the wafers. They are exposed
using Contact reticle (reticle IC12_CONT) on the stepper. We use the RMSDIR to ensure the
correct reticle is in place and later then make sure the wafers are aligned. The number 3 below
the marks should be seen.
We then have to descum the wafers to remove any left residue on the wafers. Next, we
etch the wafers on the RIE using fluoroform (not hydrogen) until the vias and contacts are clear.
As the etching is done, we should pay careful attention to the horizontal bars in the middle of the
left side chip (the n-TLM or p-TLM can be used). The TLM squares ought to be etched all the
way to bare silicon and looking silver-ish in color.
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Figure 29 - Reflection image of TLM Structures recorded in the center and at the edge of wafers.
After this, the wafers should be put back in the PVA to remove the photoresist and also
any residue left on them.
After which, an RCA clean of the wafers is carried out. The only exception here is that
the wafers don’t go in the HF bath. This is very important.
Metal Interconnects (Metal Lithography and Etch)
Aluminum (about 200nm thick and 2% of silicon) will be deposited on the wafers. When
this is done, the wafers are not to undergo any RCA bath afterwards; this is because no metal
should be in the RCA bath and having the wafers in the RCA baths will destroy the aluminum.
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Figure 30 - Metallization applied and etched using aluminum mask.
Photoresist is then applied for the wafers to get them ready for lithography. The wafers
are then exposed on the wafers using the Metal reticle (reticle IC12_MET) program. Care should
be taken to ensure that the correct reticle is in the system and also is the metal makes a rough
contact on the surface, the “MAP METAL\RDFAS” can be used or the “EXEC
METAL\NODFAS” can be used to skip it altogether.
The wafers are then dry etched in the RIE using the aluminum etch recipe, “ICAIEtch”.
This makes use of the dangerous and corrosive chlorine gas and care should be taken. Normally,
it takes 3:45 and 5:00 for the etching and ashing time respectively.
After the etching is complete, the wafers are soaked in DI for about 60 seconds. This is done to
remove any remaining chlorine residue on the wafers.
Final Anneal
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Figure 31 - Optical micrographs of cleaved cross-section of wafers annealed at Hi-Lo-Hi
treatment at high temperatures.
Annealing is used to repair the damage to the x-tal during the implantation process. The
wafers are loaded into the furnace and the recipe “IC_Anneal” is used. It runs at about 450 o C.
One important caution in loading the boat is that the loaded are loaded in the load station with
the phosphoric acid (and NOT in the RCA bath loading station). This is because of the metal on
the wafers and metals shouldn’t be near the RCA hood. The anneal takes about 30 minutes and
then the wafers can be left to cool before unloading.
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Figure 32 - Wafers being brought out by a scientist after the annealing process.
Overlayer (Overglass Photolithography and Etch)
A layer of silicon nitride is deposited on the wafers on the PECVD. This is an overglass
layer of silicon nitride, of about 200nm.
Figure 33 - Picture g shows the membrane sealing with silicon nitride deposition.
Picture h shows the top electrode deposition and patterning.
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Photoresist is then applied on the wafers in preparation for the lithography. The wafers
are then exposed on the stepper using the Overglass reticle, “reticle IC12_M2VIA” recipe. The
stepper program can be used to align the marks on the wafer and also it should be ensured that
the correct reticle is being used.
After exposing the wafers on the stepper, they are then etched. The pad openings are
etched; two wafers at a time. This is done until all the etching has occurred all the way to the
aluminum pads. The recipe “ICnitrd” is used.
The wafers are now then put in the PVA to remove all photoresist and clean it for the
final time before dicing.
Once this is done, the wafers are now ready. The next fun – the fun part - involves dicing
the wafers - in which the wafers are broken/sliced carefully. The individual silicon chips are then
played into chip carriers and for use in our devices.
Figure 34 - Photo of diced wafers.