VHDL Intro
• What does VHDL stand for?
VHSIC Hardware Description Language
VHSIC = Very High Speed Integrated Circuit
Developed in 1982 by Govt. to standardize the
coded representation of hardware for govt.
projects
Why use VHDL
• VHDL is for coding models of a digital system...
• Reasons for modeling
–
–
–
–
documentation
testing using simulation
formal verification
Synthesis – can optimize designs beyond practical
means possible by regular person
• Goal
– most ‘reliable’ design process, with minimum cost and
time
– avoid design errors!
– Reuse libraries and designs already provided
VHDL Design Process
• Write module code
• Write a VHDL Driver program (TestBench)
• Simulation – Simulate your design using
Modelsim on your TestBench
• Synthesis – Synthesize your design using
a given set of constraints
• Verification (timing, etc) – Verify that the
synthesized design works
VHDL Models
• Every VHDL model generally consists of
one entity declaration
– Entity
• Name/Identity of the module you want to design
• Declares number and types of ports that module
uses
• Allows the internal algorithm or hardware
representation of that entity to separated from its
module reference (the entity is the black box)
VHDL Models
• VHDL models have one or more
Architecture descriptions
– The architecture description is the actual
implementation of the entity reference (the
inside of the black box)
– Can have more than one architecture
description to handle varying design cases
• Example, with a 32bit adder entity, you can have
architecture descriptions for a slow, small carryripple adder, and a faster, bigger carry look ahead
VHDL Models
• Architectures for your entities can be coded
using three different VHDL language constructs
– Behavioral
• Sequential statements done in a special VHDL construct
called a process
– Dataflow
• Concurrent assignment statements
– Structural
• Component instantiation and port mapping
Behavioral
• Used to model things that are sequential in
nature (sequential logic for example)
– Uses the idea of something called a process
• A process holds a block of sequential statements inside its
code area
• A process is only executed when something in its sensitivity
list changes
– Inside process statement
• Can declare variables
• Use := operator with variable assignments
• Can use specialized keywords (such as wait, after) to
simulate real world delays (example can include a global
variable that simulates delay time of basic gates, then
simulation timing will be more accurate
Behavioral Example
process( S1, S2 ) Sensitivity list
variable V1, V2: BIT;
Variable Declarations
begin
V1 := ’1’; –– This sets the value of V1
V2 := ’1’; –– This sets the value of V2
V1 := ’0’; –– This sets the new value of V1
V2 := ’0’; –– This sets the new value of V2
end process;
Dataflow
• Used to assign changes concurrently, value gets
propagated from input to output whenever input
changes
• Use the <= operator
• Remember, everything happens concurrently
• Generally a Dataflow item will synthesize to
some sort of memory based hardware (latch or
flip flop for clocked processes ) as storage is
implied
Dataflow Example
library IEEE;
use IEEE.std_logic_1164.all;
entity simpleAnd is
port (
A: in STD_LOGIC;
B: in STD_LOGIC;
OUT: out STD_LOGIC
);
end simpleAnd;
architecture dataflowAnd of simpleAnd is
begin
OUT <= A & B;
end dataflowAnd;
Structural
• Used when you want to include other
modules in your current design.
– First you instantiate a module and give it a
unique name
– Then you map its input/output ports into your
current module using a port map
Structural Example
architecture struct of comb_ckt is
component AND_GATE is
port( A:
in std_logic;
B: in std_logic;
F1:
out std_logic
);
end component;
-- as entity of AND_GATE
component OR_GATE is
port( X:
in std_logic;
Y: in std_logic;
F2: out std_logic
);
end component;
-- as entity of OR_GATE
begin
Gate1: AND_GATE port map (A=>input1, B=>input2, F1=>wire);
Gate2: OR_GATE port map (X=>wire, Y=>input3, F2=>output);
end struct;
Overall Design
• All three different methods of design can
be mixed in one architecture block
• Example – Finite State Machine Design
– Data Flow design used to pick the next state
assigned to state storage flip flop
– Behavioral process block used to write logic
that determines what the next state is
Other VHDL keywords
• Signals
– Syntax: signal <= value
– Used mostly in structural, dataflow designs
– Cause simulation events to be created, but they will
be handled during the next simulation delta
– Can be considered as a wire (with the understanding
of how the simulation delta affects it)
• Variables
– Syntax: var:=expression
– Can only be used in processes (behavioral designs)
– Do not cause simulation events
Example - Variables
• Process statement using variables
process (y)
variable x,z : bit;
begin
x:=y; x now has the value of y after this line executes
z:=x; z now has the value of x after this line executes
end process;
• Question: Is z == x ?
– Yes, because variables are updated immediately during the
CURRENT simulation delta after every assignment
Example -Signals
• Process statement using signals
…
signal x,y,z : bit;
…
process (y)
begin
x<=y; x is assigned the value of y as soon as the process starts
z<=x; z is assigned the OLD value of x as soon as the process starts
end process;
• Question: Is z == x ?
– NO, because when the assignment x<=y takes place, on the next
simulation delta the change of x will be available not in the current
simulation delta
– z == old value of x