ECE 3220 Digital Design with VHDL
Introduction to VHDL #1
Lecture 3
Introduction to VHDL
The two Hardware Description Languages that are most often
used in industry are:
n VHDL
you will learn this one
n Verilog
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Syntax and appearance of the two languages are different
Have similar capabilities and scopes
If you learn one you can pick up the other quickly.
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Introduction to VHDL
n
VHDL is a language for describing digital hardware used by industry worldwide
VHDL is an acronym for VHSIC (Very High Speed Integrated Circuit) Hardware Description Language California State University
Introduction to VHDL
VHDL Descriptions consist of two main parts:
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The entity declaration
The architecture declaration
design entity
Interface
entity declaration
Body
architecture
The combination of these two parts is called a design entity
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Example of VHDL Code
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3 sections to a piece of VHDL code
File extension for a VHDL file is .vhd
Name of the file should be the same as the entity name (nand_gate.vhd) LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY nand_gate IS
PORT(
a
: IN STD_LOGIC;
b
: IN STD_LOGIC;
z
: OUT STD_LOGIC);
END nand_gate;
ARCHITECTURE model OF nand_gate IS
BEGIN
z <= a NAND b;
END model;
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LIBRARY DECLARATION
ENTITY DECLARATION
ARCHITECTURE BODY
Entity Declaration
The entity declaration describes the circuit as it appears from the "outside"
– from the perspective of its inputs and outputs.
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The actual operation of the circuit is not defined in the entity declaration.
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Entity Declaration
The entity declaration is comprised of 3 statements:
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name statement
port statement
end statement
Port statement
entity example is
port(
A,B
: in bit;
Z
: out bit);
end example;
Name of the design entity
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Entity Declaration
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The port statement defines all of the signals that will be visible to external design entities.
Each of the ports is given a port mode, a signal name, and a signal type.
entity example is
port(
A,B
: in bit;
Z
: out bit);
end example;
Signal names
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Signal type
Entity Declaration-Signal Type
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Signals of type “BIT” can take on values from the set {0,1}
Signals can also be arrays of values. An example is the
“BIT_VECTOR” type.
entity example is
port(
A,B
: in bit_vector (7 downto 0);
Z
: out bit);
end example;
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Signals A and B are defined as 8-element arrays with each array
element being of type bit.
The MSB is element 7 and the LSB is the element with index 0
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Entity Declaration-Signal Type
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The “BIT” and “BIT_VECTOR” types are built-in to VHDL
(i.e. are defined by the VHDL standard)
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Other types can be user-defined (usually defined in
packages that are included into your code).
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Entity Declaration-Signal Type
STD_LOGIC Type
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Designed to model electrical signals on single wires
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Used to represent signals driven by:
active drivers (forcing strength)
resistive drivers (pull-ups and pulldowns – weak strength)
tri-state drivers (which add a high-impedance state)
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Entity Declaration-Signal Type
There are 9 different values that a signal of type STD_LOGIC
can take on. Operators for signals of this type must handle
all of the possible combinations.
type std_logic is (
‘U’,-- Uninitialized
‘X’, -- Forcing unknown
‘0’, -- Forcing zero
‘1’, -- Forcing one
‘Z’, -- High Impedance
‘W’, --Weak Unknown
‘L’, -- Weak zero
‘H’, -- Weak one
‘-’); -- Don’t care
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Entity Declaration-Signal Type
STD_LOGIC_VECTOR Type
n
Unconstrained array type for vectors of standard-logic
values (std_logic values)
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Similar to bit_vector signals but are arrays of std_logic
signals.
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The ranges of bit_vector and std_logic_vector signals can
be defined in two different ways:
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Entity Declaration-Signal Type
Example of Style 1:
C : in std_logic_vector(0 to 2);
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This way is often used to represent a collection of wires that
are not intended to represent a number.
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In this example C(0) is the MSB and C(2) is the LSB.
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Entity Declaration-Signal Type
Example of Style 2:
C : in std_logic_vector(2 downto 0);
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This way is preferred when the signal represents a binary
number.
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In this example C(0) is the LSB and C(2) is the MSB.
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Entity Declaration-Port Mode
There are 4 different port modes:
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in - the associated signal can only be read, and not set
out - the associated signal can only be set, and not read
inout - the associated signal can be read and set
buffer - indicates a port which can be used for both input and output, and it can have
only one source. A buffer port can only be connected to another buffer port or to a
signal that also has only one source.
entity example is
port(
A,B
: in bit;
Z
: out bit);
end example;
Port modes
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Entity Declaration
Entity declaration example: NAND gate
a
z
b
Entity name
Port statement
Port names
Port type
entity nand_gate is
port(
a
: in std_logic;
b
: in std_logic;
z
: out std_logic
);
end nand_gate;
Port modes (data flow directions)
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Semicolon
No Semicolon
after last port
Architecture Declaration
The architecture body consists of two parts:
n Declarations area
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declare internal (non-port) signals
declare component types
declare user-defined signal types
declare constants
other declarations
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Statements area
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signal assignments
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Architecture Declaration
Architecture name
Associated entity name
architecture implementation1 of example is
signal C : bit;
Declaration area
begin
C <= A and B;
Concurrent statements area
Z <= A or C;
end implementation1;
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Architecture Declaration-Signal Declaration
A signal declaration includes—in this order:
n the reserved word "signal",
n the name of the signal,
n the type of the signal,
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optionally, an indication of the signal’s kind (which must be
either "register" or "bus"),
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optionally, an expression specifying the initial value of the
signal.
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Architecture Declaration-Signal Declaration
Some examples of signal declarations:
signal data, reset : bit;
signal clk : std_logic := ‘0’;
signal memory_bus : bit_vector(7 downto 0);
Signal names
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Signal types
Initial value
Architecture Declaration-Statement Area
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The statements area is where you describe the functionality
of the circuit.
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This place is found between the begin and end statements
of an architecture body.
architecture implementation1 of example is
signal C : bit;
begin
C <= A and B;
Concurrent statements area
Z <= A or C;
end implementation1;
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Architecture Declaration-Statement Area
Signal Assignment Statements:
n Circuit functionality is described using various types of
signal assignment statements.
Signal Assignments:
n Specify how events on some signals are created in
response to events on other signals.
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Architecture Declaration-Statement Area
Concurrency:
n VHDL models physical circuits, therefore there is no natural
ordering of signals and signal assignments. Many events
can happen at the same time in a physical circuit.
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All signal assignments are therefore considered to be
concurrent, and can be written in any order.
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Architecture Signal Assignment
Forms of signal assignment statements:
§Simple
Concurrent Assignment
§Selected Assignment
§Conditional Assignment
§Component Instantiation
§Generate Statements
§Process Blocks
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Architecture Signal Assignment-Simple Concurrent
Simple Concurrent Assignment Statements
signal <= expression;
Examples:
A_out <= not (A_in or B_in)and Enable;
Data
<= x nor D2 xor (flag_A and flag_B);
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The “not” operator has the highest precedence.
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Operators in parentheses are evaluated first.
All binary operators have equal precedence.
Operators with the same precedence are evaluated left-to-right.
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Example
Let’s make a VHDL description of the following circuit:
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Example
entity example is
port(
A,B
: in std_logic;
C
: out std_logic);
end example;
architecture implementation1 of example is
signal I1 : std_logic;
begin
C <= A or I1;
The order of these statements is
I1 <= not B;
not important !
end implementation1;
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Signal Assignment Statements-Selected
Selected Signal Assignment Statements
A selected signal assignment is a means of conveniently
describing multiplexer structures
with Dsel select
Y <=
A when
B when
C when
D when
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“00”,
“01”,
“10”,
others;
Order is not important !
Signal Assignment Statements-Selected
Selected Signal Assignment Statements
n Note: All conditions must be defined in a selected signal
assignment, otherwise your code will not conform to the
VHDL standard and you will probably get an error from
whatever software happens to be reading your code.
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Coverage of all conditions can be tricky to ensure –which is
why the “when others” clause is useful
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Signal Assignment Statements-Selected
An example of possible problems:
with Dsel select
Y <=
A when
B when
C when
D when
“00”,
“01”,
“10”,
“11”;
This assignment statement will give an error if Dsel is of type
STD_LOGIC_VECTOR (but not if Dsel is of type BIT_VECTOR).
Why?
Because the type of signal Dsel has more possible values than just 0 and 1
(e.g. a high-impedance value –Z) so that not all possibilities are covered.
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Signal Assignment Statements-Conditional
Conditional Signal Assignment Statements
Conditional signal assignment is similar to selected signal
assignment. It is often used for circuits which implement
some sort of priority.
Y <=
A when “00” else
B when “01” else
C when “10” else
D;
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Order is important !
Signal Assignment Statements-Conditional
Unlike in selected assignment it is not absolutely required that
all conditions be covered.
Y <=
A when “00” else
B when “01” else
C when “10”;
If all conditions are not accounted for in a conditional
assignment statement, a storage element (e.g. a flipflop) will
be created, a phenomenon known as implied memory.
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Implied Memory
Consider the following conditional statement:
Y <= A when D = ‘1’;
This statement does not say what happens when D is 0.
Therefore no events can be created on Y when D is 0, no
matter what events occur on other signals. Thus the value
of Y is held (memory) when D is 0.
To remove the implied memory we can write:
Y <= A when D = ‘1’ else
‘0’;
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VHDL Libraries
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VHDL Libraries
To use the STD_LOGIC type, VHDL code must include the two
lines given at the beginning of the code. They are needed
because the original VHDL standard, IEEE 1076, did not
include the STD_LOGIC type.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY nand_gate IS
PORT(
a
: IN STD_LOGIC;
b
: IN STD_LOGIC;
z
: OUT STD_LOGIC);
END nand_gate;
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Library declaration
VHDL Libraries
n
The first line of the code is to declare that the code will make
use of the IEEE library.
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The second line of code tells the VHDL compiler to use the
definitions in this file when compiling the code.
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The file encapsulates the definition of STD_LOGIC in what
is known as a package. The package is named
std_logic_1164.
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VHDL Library declarations - syntax
LIBRARY library_name;
USE library_name.package_name.package_parts;
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VHDL Libraries
n ieee
Specifies multi-level logic system,
including STD_LOGIC, and
STD_LOGIC_VECTOR data types
n std
Specifies pre-defined data types
(BIT, BOOLEAN, INTEGER, REAL,
SIGNED, UNSIGNED, etc.), arithmetic
operations, basic type conversion
functions, basic text i/o functions, etc.
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