EEE324 Digital Electronics
Lecture 6: VHDL for simple Digital Logic
Ian McCrum
Room 5B18, 02890366364
IJ.McCrum@ulster.ac.uk
http://www.eej.ulst.ac.uk/~ian/modules/EEE342
VHDL: A text based hardware
description language.
• Developed by DARPA to provide vendor independent
design specifications for Very high speed Ics. (under
their VHSIC program)
• Hence the name, the V stands for VHSIC
• There are other HDLs (Hardware Description
Languages) of which Verilog is the most common.
Based on C.
• VHDL is based on the ADA programming language –
designed to support concurrency.
• Started in the early 80’s, standardised by IEEE in ’87
updated ’92. minor differences for most people, be
careful if getting code from net…
Uses; many and varied, it has evolved
•
•
•
•
Documentation and Specification
Modeling a system at differing levels
Circuit simulation
Developing different versions; increasing in
implementation detail (each can be simulated)
• Circuit synthesis
• Algorithm experimentation
• Creating simulation models for libraries (e.g Viewlogic
used it internally in its schematic capture and
simulation system – its model for a gate was a few lines
of VHDL, with detailed timing data etc.,
Is it like ‘C’
• Yes – There are statements, block structure,
variables, constants, operators, loops and
conditionals, even uses ; as statement terminator
• No – C is a sequential Computation model; line 1,
line 2, line 3 etc
• No – HDL statements translate to gates not
instructions
• No HW is always “on” everything operates
concurrently. AND gates do their thing at the
same time as the OR gates do their thing…
Can use VHDL in many ways
Three ways to describe a circuit
• Structural – Instantiate specific library components and
“wire” them together. – the concept or a netlist helps
to understand this.
• Dataflow (RTL) use VHDL equations to specify how
combinational logic works, design system to flow data
from one combinational block to another. (can use
simple storage registers if needed)
• Behavioural - code the entire algorithm let the VHDL
compiler infer what to do.
Think of a MP3 compression design; algorithm, then
block diagram, function of each block well described.
Then finally a netlist and parts list.
Basic VHDL – a block in a block diagram
• 2 parts; ENTITY and ARCHITECTURE
• (also can have PACKAGE and CONFIGURATION
sections but you can ignore these if you just want
a mini-introduction to VHDL.)
• Entity – what you need to use a VHDL model; it
simply lists inputs and outputs and tells you their
type, size and name.
• (can also pass generic information like your
desired propagation delay then each instantiation
of the model can be different)
Basic Logic Gate
library ieee;
use ieee.std_logic_1164.all;
x
y
F
architecture behav1 of AND_ent is
begin
process(x, y)
entity AND_ent is
begin
port( x: in std_logic;
-- compare to truth table
y: in std_logic;
if ((x='1') and (y='1')) then
Comment
F: out std_logic
F <= '1';
);
else
end AND_ent;
F <= '0';
end if;
architecture behav2 of AND_ent is
end process;
begin
end behav1;
F <= x and y;
end behav2;
Operation
Signal
defined on
assignment
std_logic
(a “wire”)
7
Ports carry signals from the outside
world.
• We sometimes need intermediate signals
TEMP
A
B
C
F
VHDL – you can declare signals
library ieee;
use ieee.std_logic_1164.all;
entity simp is
port(a,b,c : in std_logic; f : out std_logic);
end simp;
architecture first of simp is
Signal temp : std_logic ; -- no need to state in/out
begin -- Note all concurrent statements between begin
-- and end execute simultaneously
temp <= a and b; -- note we use <= for signal assignment
f <= c or temp; -- i.e “will become equal to”
-- or “a change to this signal is scheduled”
end first;
-- usually called “scheduling a transaction”
-- signal transactions can specify time delays
VHDL – you can also declare variables, these use the equal sign for variable
assignment and have no time dependencies – the change happens
immediately.
VHDL is known as a strongly “typed”
language
• You cannot compare two values if they are of
different types. A 4 bit number 1001 is not
the same as an integer of 9.
• There are a number of conversion functions
available and you have to use these (or write
your own).
• The reason is to make the synthesis tools job
easier (and to make you think more – error
checking)
The different types
•
•
•
•
VHDL has bits, booleans, integers and more.
Bits can have one of two values
Ok for “theoretical” logic
Real systems need more values – uninitialised,
unknown, high – impedance (both transistors
off – known as tristate) and zero,one and
unknown can be strong or weak. Finally we
need a don’t care/never happen value.
Std_logic and Std_logic_vector
• Used for real world signals.
• 9 values
U
X
0
1
Z
W
L
H
-
Uninitialized
Unknown
Zero
One
High Impedance (tristate not driving output)
Weak Unknown
Weak Zero (low)
Weak One (high)
Don’t Care
Data in VHDL
• You can prefix Binary with a B if you surround the bits with double quotes,
likewise for hex e.g
• B”101”
• X”5”
• Bits use single quotes ‘1’ or ‘0’
• Groups of bits are of type std_logic_vector we give the start position and
usually the phrase DOWNTO. We can change that…
• E,g
• PORT( DIN
: in
std_logic_vector(7 downto 0);
-- can use with signals as well
Summary of what we have covered
• VHDL needs an entity and an architecture
• Has keywords begin and end
• Uses ; to terminate statements and -- for
comments
• Ports need a “mode” of in or out
• Ports and signals need their type specified
• Can use B”101” or X”5”
• We can use functions and, or etc.,
Truth tables in VHDL
We have to make a 3 bit vector out of 3 separate inputs
This is an exampe of the WITH…. WHEN statement, used like CASE statements
Most sequential programming constructs have concurrent versions, with different names.
Entity t is Port(a,b,c : in std_logic; y : out std_logic); End entity t;
Architecture truth of t is
Signal inputs : std_logic_vector(2 downto 0);
Begin
Inputs <= a & b & c; -- concatenate (join) bits to become a vector
With inputs select
Y <=
‘0’ when “000”,
‘1’ when “001”,
‘0’ when “010”,
‘1’ when “011”,
‘1’ when “100”,
‘0’ when “101”,
‘0’ when “110”,
‘0’ when “111”,
‘-’ when others;
End truth;
Concurrent statements
Put in the body of an architecture – between begin and end
• Signal assignment
S <= a and not (b or c);
• Selected signal assignment
With s select f <= ‘1’ when ‘0’, ‘0’ when “1”
• Conditional signal assignment
f <= ‘1’ when s = ‘0’ else
‘0’ when s = ‘1’ else
‘Z’;
• Process statement (the entire process is treated as a
single concurrent statement – the process itself is
comprised of sequential statements)
Sequential statements
Found inside processes, bit like C, signals however still
have a time behavious – the updates take place at the
very end of the process
If (f = s ) then
x <= ‘1’;
else
x <= ‘0’;
end if;
case f is
when ‘0’ => x <= ‘1’;
when ‘1’ => x <= ‘0’;
when others => x <= ‘z’;
end case;
There are also while loops and for loops
Using VHDL
• In Altera you can begin with a VHDL top level, but at
the beginning avoid this
• You can write a VHDL program, in altera (use the file>new command)
• Compile it and select “Create default symbol for the
current file” option in the file menu.
• If you start a new file, make it the top level entity by
rightclicking it in the file navigator.
• You can now instantiate your vhdl program as a
symbol. You can repeat this so your top level is actually
a block diagram of your system and the lower levels are
just (each) simple VHDL progams. A powerful way of
designing – quick!
VHDL Tutorials
• Implement Q1-Q4 of tutorial 4 as VHDL programs
– for Q1 and Q2 use the answers and VHDL and,or,not
functions.
– For Q3 and 4 use the truth table method
• Create a symbol and then create a toplevel that
will contain the symbol (and pins)
• Simulate and demonstrate it works as expected.
• Compare simulation results to a pure schematic
solution.
• For Q5 in Tutorial 4, can you express an equation
to implement it