Address Decoding for
Memory and I/O
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Address Decoding
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Address Decoding Designs
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Implementation
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Full Address Decoding
Partial Address Decoding
Block Address Decoding
Random, Decoders, PROM, FPGA
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Address Decoding
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Required for a microcomputer where memory
and I/O support are essential
Needed for embedded system when on chip
microcontroller memory is not sufficient
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The Memory Space
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2 basic approaches
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Memory mapped system – main memory and I/O
space are just different addresses or regions – or
memory mapped I/O (MMIO)
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Port Mapped I/O – have unique pins (signals) that
differentiate memory and I/O address spaces
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Addressing is the same pins for memory and I/O
Advantage – less pin and hardware complexity
Advantage – If limited memory, memory is memory
Advantage – Large I/O space
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Other architectures
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Harvard Architecture
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Separate memory spaces for instructions and data
Requires pin(s) to differentiate
I/O is MMIO
Check these out on www.wikipedia.com
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The 68000 Memory Space
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23 address lines
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223 words with
UDS* and LDS*
This is 8M words
or 16M bytes
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Address Map
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When
implementing a
system the designer
creates a memory
map.
Map would include
where RAM, ROM
and I/O are.
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Full address decoding
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Each addressable
location within the
memory
components
responds to only a
single unique
address.
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Example of full address decoding
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Ex continued
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Partial Address Decoding
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Some of address lines are unused
Least complex and most inexpensive
Each component will actually respond to
several addresses
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Partial Address decoding example
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Block Address decoding
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Compromise between full and partial.
Don’t decode all of address lines but do
decode more than the bare minimum.
Less repeated addresses for each populated
device
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Designing the decode logic
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Multiple methods of implementing the decode
logic
One method is of course to implement it with
“random logic” – i.e., AND gates, OR gates,
inverters, NAND gates, NOR gates
Advantage – speed
Disadvantage – possibly the number of chips
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Decoders
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USE m-line-to-n-line decoders
Decode an m-bit input into one of n outputs
where n = 2m
Popular 74LS138 – 3-to-8 decoder
Another 74LS154 – 4-to-16 decoder
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Decoder Truth table
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Example of decoder use
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Implementation
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PROMS
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A PROM can also be use to
implement logic functions
Can use it to do address
decoding
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Example of PROM use
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Decoder design must be cheap and versitle.
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PROM Programming
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PROM System
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Advantage
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Ability to
select blocks
of differing
size
Versitility
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FPGA, PLA, PAL
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Programmable
Logic Arrays
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Programmable
Array Logic
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AND plane – OR
plane
Limited PLA
FPGA – A
network of CLBs
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PAL vs PLA
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In a PAL the
ouput’s
connection to
product terms is
fixed
More limited
logic equation
support
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Special devices
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There are also special chips specifically
designed for address decoding
Some may be designed for a specific family
of chips
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