180
INPUT – OUTPUT DESIGN AND ORGANIZATION
Req-1
Potential
Master 1
Potential
Master 2
Potential
Master n
Grant-1
Req-2
Central
Bus
Arbiter
Grant-2
Grant-n
Req-n
Bus Busy
Figure 8.13
Centralized arbiter with independent request and grant lines
bus requests from different levels, it grants the bus to the level with the highest
priority. Daisy chaining is used among the devices of that level. Figure 8.14
shows an example of four devices included in two priority levels. Potential
master 1 and potential master 3 are daisy-chained in level 1 and potential master
2 and potential master 4 are daisy-chained in level 2.
Decentralized Arbitration In decentralized arbitration schemes, priority-based
arbitration is usually used in a distributed fashion. Each potential master has a
unique arbitration number, which is used in resolving conflicts when multiple
requests are submitted. For example, a conflict can always be resolved in favor of
the device with the highest arbitration number. The question now is how to determine which device has the highest arbitration number? One method is that a requesting device would make its unique arbitration number available to all other devices.
Each device compares that number with its own arbitration number. The device with
the smaller number is always dismissed. Eventually, the requester with the highest
arbitration number will survive and be granted bus access.
Grant level 1
Potential
Master 1
Central
Bus
Arbiter
Potential
Master 2
Potential
Master 3
Grant level 2
Request level 1
Request level 2
Bus Busy
Figure 8.14
Centralized arbiter with two priority levels (four devices)
Potential
Master 4
8.6. INPUT – OUTPUT INTERFACES
181
8.6. INPUT –OUTPUT INTERFACES
An interface is a data path between two separate devices in a computer system. Interface to buses can be classified based on the number of bits that are transmitted at a
given time to serial versus parallel ports. In a serial port, only 1 bit of data is transferred at a time. Mice and modems are usually connected to serial ports. A parallel
port allows more than 1 bit of data to be processed at once. Printers are the most
common peripheral devices connected to parallel ports. Table 8.4 shows a summary
of the variety of buses and interfaces used in personal computers.
TABLE 8.4
Descriptions of Buses and Interfaces Used in Personal Computers
Bus/Interface
Description
PS/2
A type of port (or interface) that can be used to connect mice and
keyboards to the computer. The PS/2 port is sometimes called the
mouse port.
Industry standard
architecture (ISA)
ISA was originally an 8-bit bus and later expanded to a 16-bit bus in
1984. In 1993, Intel and Microsoft introduced a plug and play
ISA bus that allowed the computer to automatically detect and set
up computer ISA peripherals such as a modem or sound card.
Extended industry
standard
architecture
(EISA)
EISA is an enhanced form of ISA, which allows for 32-bit data
transfers, while maintaining support for 8- and 16-bit expansion
boards. However, its bus speed, like ISA, is only 8 MHz. EISA is
not widely used, due to its high cost and complicated nature.
Micro channel
architecture
(MCA)
MCA was introduced by IBM in 1987. It offered several additional
features over the ISA such as a 32-bit bus, automatically
configured cards and bus mastering for greater efficiency. It is
slightly superior to EISA, but not many expansion boards were
ever made to fit MCA specifications.
VESA (Video
electronics
standards
association) local
bus (VLB)
The VESA, a nonprofit organization founded by NEC, released the
VLB in 1992. It is a 32-bit bus that had direct access to the system
memory at the speed of the processor, commonly the 486 CPU
(33/40 MHz). VLB 2.0 was later released in 1994 and had a
64-bit bus and a bus speed of 50 MHz.
Peripheral
component
interconnect (PCI)
PCI was introduced by Intel in 1992, revised in 1993 to version 2.0,
and later revised in 1995 to PCI 2.1. It is a 32-bit bus that is also
available as a 64-bit bus today. Many modern expansion boards
are connected to PCI slots.
Advanced graphic
port (AGP)
AGP was introduced by Intel in 1997. AGP is a 32-bit bus designed for
the high demands of 3D graphics. AGP has a direct line to memory,
which allows 3D elements to be stored in the system memory
instead of the video memory. AGP is geared towards data-intensive
graphics cards, such as 3D accelerators; its design allows for data
throughput at rates of 266 MB/s.
(continued )