IKI10230
Pengantar Organisasi Komputer
Bab 4.2: DMA & Bus
Sumber:
1. Hamacher. Computer Organization, ed-5.
2. Materi kuliah CS152/1997, UCB.
26 Maret 2003
Bobby Nazief (nazief@cs.ui.ac.id)
Qonita Shahab (niet@cs.ui.ac.id)
bahan kuliah: http://www.cs.ui.ac.id/kuliah/iki10230/
1
DMA
2
Improving Data Transfer Performance
° Thus far: OS give commands to I/O,
I/O device notify OS when the I/O device completed
operation or an error
° What about data transfer to I/O device?
• Processor busy doing loads/stores between memory and I/O Data
Register:
Wait:
sbis DiskControl,1
; is Disk ready?
rjmp Wait
; no
in
r0,DiskData
; get byte
st
X+,r0
; store it
dec r16
; done?
bne Wait
; not yet
° Ideal: specify the block of memory to be transferred,
be notified on completion?
• Direct Memory Access (DMA) : a simple computer transfers a
block of data to/from memory and I/O without involving the
processor, interrupting upon done
3
Delegating I/O Responsibility from the CPU: DMA
CPU sends a starting address,
direction, and length count
to DMAC. Then issues "start".
° Direct Memory Access (DMA):
CPU
• External to the CPU
• Act as a maser on the bus
• Transfer blocks of data to or from
memory without CPU intervention
Memory
Issue:
• Who controls the BUS?
(CPU or DMAC may do so)
• How?
DMAC
IOC
device
DMAC provides handshake
signals for Peripheral
Controller, and Memory
Addresses and handshake
signals for Memory.
4
Arbitration: Obtaining Access to the Bus
Bus Arbitration
5
Multiple Potential Bus Masters: the Need for Arbitration
° Bus arbitration scheme:
• A bus master wanting to use the bus asserts the bus request
• A bus master cannot use the bus until its request is granted
• A bus master must signal to the arbiter after finish using the bus
° Bus arbitration schemes usually try to balance two
factors:
• Bus priority: the highest priority device should be serviced first
• Fairness: Even the lowest priority device should never
be completely locked out from the bus
° Bus arbitration schemes can be divided into four
broad classes:
• Daisy chain arbitration: single device with all request lines.
• Centralized, parallel arbitration: see next-next slide
• Distributed arbitration by self-selection: each device wanting the
bus places a code indicating its identity on the bus.
• Distributed arbitration by collision detection: Ethernet uses this.
6
The Daisy Chain Bus Arbitrations Scheme
Device 1
Highest
Priority
Grant
Bus
Arbiter
Device N
Lowest
Priority
Device 2
Grant
Grant
Release
Request
wired-OR
° Advantage: simple
° Disadvantages:
• Cannot assure fairness:
A low-priority device may be locked out indefinitely
• The use of the daisy chain grant signal also limits the bus speed
7
Centralized Parallel Arbitration
Device 1
Grant
Device 2
Device N
Req
Bus
Arbiter
° Used in essentially all processor-memory busses
and in high-speed I/O busses
8
Types of Buses
More on BUS
9
A Computer System with One Bus: Backplane Bus
Backplane Bus
Processor
Memory
I/O Devices
° A single bus (the backplane bus) is used for:
• Processor to memory communication
• Communication between I/O devices and memory
° Advantages: Simple and low cost
° Disadvantages: slow and the bus can become a major
bottleneck
° Example: IBM PC - AT
10
A Two-Bus System
Processor Memory Bus
Processor
Memory
Bus
Adaptor
I/O
Bus
Bus
Adaptor
Bus
Adaptor
I/O
Bus
I/O
Bus
° I/O buses tap into the processor-memory bus via bus
adaptors:
• Processor-memory bus: mainly for processor-memory traffic
• I/O buses: provide expansion slots for I/O devices
° Apple Macintosh-II
• NuBus: Processor, memory, and a few selected I/O devices
• SCCI Bus: the rest of the I/O devices
11
A Three-Bus System
Processor Memory Bus
Processor
Memory
Bus
Adaptor
Bus
Adaptor
Backplane Bus
(e.g., PCI)
Bus
Adaptor
I/O Bus (e.g., SCSI)
I/O Bus
° A small number of backplane buses tap into the
processor-memory bus
• Processor-memory bus is used for processor memory traffic
• I/O buses are connected to the backplane bus
° Advantage: loading on the processor bus is greatly
reduced
12
What defines a bus?
Transaction Protocol
Timing and Signaling Specification
Bunch of Wires
Electrical Specification
Physical / Mechanical Characterisics
– the connectors
13
Synchronous and Asynchronous Bus
° Synchronous Bus:
•
•
•
•
Includes a clock in the control lines
A fixed protocol for communication that is relative to the clock
Advantage: involves very little logic and can run very fast
Disadvantages:
- Every device on the bus must run at the same clock rate
-
To avoid clock skew, they cannot be long if they are fast
° Asynchronous Bus:
• It is not clocked
• It can accommodate a wide range of devices
• It can be lengthened without worrying about clock skew
• It requires a handshaking protocol
14
Simplest bus paradigm
° All agents operate syncronously
° All can source / sink data at same rate
° => simple protocol
• just manage the source and target
15
Simple Synchronous Protocol
BReq
BG
R/W
Address
Data
Cmd+Addr
Data1
Data2
° Even memory busses are more complex than this
• memory (slave) may take time to respond
• it need to control data rate
16
Typical Synchronous Protocol
BReq
BG
R/W
Address
Cmd+Addr
Wait
Data
Data1
Data1
Data2
° Slave indicates when it is prepared for data xfer
° Actual transfer goes at bus rate
17
Asynchronous Handshake
Write Transaction
Address
Master Asserts Address
Data
Master Asserts Data
Next Address
Write
Req
Ack
t0
t1
t2
t3 t4 t5
° t0 : Master has obtained control and asserts address, direction, data
°
Waits a specified amount of time for slaves to decode target
° t1: Master asserts request line
° t2: Slave asserts ack, indicating data received
° t3: Master releases req
° t4: Slave releases ack
18
Read Transaction
Address
Master Asserts Address
Next Address
Data
Read
Req
Ack
t0
t1
t2
t3 t4 t5
° t0 : Master has obtained control and asserts address, direction, data
°
Waits a specified amount of time for slaves to decode target\
° t1: Master asserts request line
° t2: Slave asserts ack, indicating ready to transmit data
° t3: Master releases req, data received
° t4: Slave releases ack
19
The I/O Bus Problem
I/O BUS
20
PCI: Peripheral Component Interconnect
21
PCI Read/Write Transactions
° All signals sampled on rising edge
° Centralized Parallel Arbitration
° All transfers are (unlimited) bursts
° Address phase starts by asserting FRAME#
° Next cycle “initiator” asserts cmd and address
° Data transfers happen on when
• IRDY# asserted by master when ready to transfer data
• TRDY# asserted by target when ready to transfer data
• transfer when both asserted on rising edge
° FRAME# deasserted when master intends to
complete only one more data transfer
22
PCI Read Transaction
– Turn-around cycle on any signal driven by more than one agent
23
PCI Write Transaction
24
PCI Optimizations
° Push bus efficiency toward 100% under common
simple usage
• like RISC
° Bus Parking
• retain bus grant for previous master until another makes request
• granted master can start next transfer without arbitration
° Arbitrary Burst length
• intiator and target can exert flow control with xRDY
• target can disconnect request with STOP (abort or retry)
• master can disconnect by deasserting FRAME
• arbiter can disconnect by deasserting GNT
° Delayed (pended, split-phase) transactions
• free the bus after request to slow device
25
1993 Backplane/IO Bus Survey
Bus
SBus
TurboChannel MicroChannel PCI
Originator
Sun
DEC
IBM
Intel
Clock Rate (MHz) 16-25
12.5-25
async
33
Addressing
Virtual
Physical
Physical
Physical
Data Sizes (bits)
8,16,32
8,16,24,32
8,16,24,32,64
8,16,24,32,64
Master
Multi
Single
Multi
Multi
Arbitration
Central
Central
Central
Central
32 bit read (MB/s) 33
25
20
33
Peak (MB/s)
89
84
75
111 (222)
Max Power (W)
16
26
13
25
26
SCSI: Small Computer System Interface
° Asynchronous Bus
° Distributed Arbitration by Self-selection
° Data transfers happen on when:
• C/D is deasserted by initiator
• I/O determines transfer direction between initiator & target
• REQ is asserted by target to request transfer cycle
• ACK is asserted by initiator when it has completed a transfer
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SCSI Signals Description
Signal
Description
BSY
indicates that the bus is being used
SEL
used by an initiator to select a target, or by a target to
reselect an initiator.
C/D
indicates control or data information is on the data bus
I/0
control the direction of data movement on the data bus
MSG
driven by a target during the Message phase
REQ
driven by a target to request a REQ/ACK handshake
ACK
driven by an initiator to acknowledge a REQ/ACK
ATN
driven by an initiator to indicate the attention condition
(indicator has a message for the target).
RST
hard reset condition
DB
• 8 data-bit signals, plus a parity-bit signal that form a
Data Bus
• DB(7) is the most significant bit and has the highest
prioty
• Bit number, significance, and priority decrease
downward
28
SCSI Arbitration
29
SCSI Read/Write Transactions
30
SCSI Roadmap
31
SCSI Bus Characteristics
Bus Width
(bits)
Bus Speed
(MB's/sec)
Max.
Devices
Bus Length
(Meters)
SCSI-1
8
5
8
6
Fast SCSI
8
10
8
3
Ultra SCSI
8
20
8
1.5
Ultra2 SCSI LVD
8
40
8
12
Fast Wide SCSI
16
20
16
3
Ultra Wide SCSI
16
40
16
1.5
Ultra2 Wide SCSI
16
80
16
12
Ultra3 SCSI
16
160
16
12
Ultra320 SCSI
16
320
16
12
Type
32
Summary of Bus Options
°Option
High performance
Low cost
°Bus width
Separate address
& data lines
Multiplex address
& data lines
°Data width
Wider is faster
(e.g., 32 bits)
Narrower is cheaper
(e.g., 8 bits)
°Transfer size Multiple words has
less bus overhead
Single-word transfer
is simpler
°Bus masters Multiple
Single master
(requires arbitration) (no arbitration)
°Clocking
Synchronous
Asynchronous
°Protocol
pipelined
Serial
33