Understanding and Protecting Against Electrical
Overstress (EOS) of Operational-Amplifiers
By Thomas Kuehl – Senior Applications Engineer
Precision Analog – Linear Applications Engineering

This could be your IC after an electrical overstress event!

Presentation Subjects
• ESD and EOS definitions
• Amplifier input range
• ESD models
• Internal ESD and consequently EOS protection circuits
• Amplifier EOS operating situations
• External EOS protection

ESD and EOS: What’s the difference?
• Electrostatic Discharge (ESD) – The transfer of electrostatic charge between bodies or surfaces at different electrostatic potential.
•
Electrical Over Stress (EOS)
– The exposure of an item to current or voltage beyond its maximum ratings.
ESD
High voltage (kV’s)
Short duration event (1-100ns)
Fast edges
Low power
Out of circuit event
EOS
Low voltage >Vs
Longer duration event
Low power
In-circuit event

Two very different environments
Handling and assembly
environments
-
+
+
OP1 !OPAMP
ESD
PC Board
-5V bus
L1 50n
V1 5
C1 100n
EOS
10V
0V
VG1
R1 1k
-
+
+
R3 1k
L2 50n
R2 10k
C2 100n
OP2 !OPAMP
Vout
R4 1k
+5V bus
V2 5

The TI data sheet Absolute Maximum Ratings is a good place to check and assure EOS problems are avoided

Input voltage range of an op-amp
+
+2kV –
+100V
≈
ESD protect region
Safe with Rs
+5.5V
+5.0V
Non-linear input
+3.5V
In-circuit max positive
Pos Safe
Pos rail
CMV input range
Input voltage
0V
-0.1V
-0.5V
Safe with Rs
-5.0V
-100V –
≈
-2kV
ESD protect region
_
Neg rail
Neg safe
In-circuit max negative
OPA735 low
Drift CMOS
Op-amp
Vi 2.5
Rs 1k
*
-
+
+
U1 OPA735
Vo
C1 100n
V1 5
* Selected to limit input current to 10mA max.

ESD Stress Models
R1 1.5k
L1 7.5u
VG1 d
2 ( i ) dt
2

R
L di
* dt

1
LC
* i

0
ESD model
Human Body Model
Machine Model
Charged Device Model
R L C V
HBM 1.5 kΩ 7500 nH 100 pF ≥ 2kV
MM 20 Ω
CDM 20 Ω
750 nH
5 nH
200 pF
2-10pF
100 - 200V
200V - 1kV

Human Body model
Human Body ESD Model
modeled in TINA Spice
T 1.5
1.0
AM1 (Amps)
500.0m
0.0
15.0
VF1 (Volts)
10.0
5.0
0.0
0
Rdut = 10 Ohms
50n 100n
Time (s)
150n
2kV
IC1
IC L1 7.5u
R1 1.5k
SW1 t
C1 100p
C2 2p
DUT
Rdut 10
VF1
200n
Rdut is the “on” resistance of an ESD protection circuit
+
A AM1

Machine Model
T 4.0
AM1 (Amps)
2.0
0.0
-2.0
40.0
VF1 (Volts)
20.0
0.0
-20.0
0
Rdut = 10 Ohms
50n 100n
Time (s)
150n
Machine ESD Model modeled in TINA Spice
DUT
200V
IC1
IC L1 500n R1 10
SW1 t
C1 200p
C2 2p Rdut 10
VF1
+
A AM1
200n
Rdut is the “on” resistance of an ESD protection circuit

CDM - ESD by induction
T 400
200
Charge Device Model modeled in TINA Spice
250V
IC1
IC
L1 5n
C1 10p
2 - 10pF
R1 20
SW1
Rdut 10
VF1
Cp 2p
0
-200
0.0
T 5.0
2.5
+
A AM1
Rdut is the “on” resistance of an ESD protection circuit
0.0
-2.5
-5.0
0.0
1.0n
1.0n
2.0n
Time (s)
3.0n
2.0n
Time (s)
3.0n
4.0n
4.0n

Common input/output ESD protection circuits
Input steering diodes
Vdd / Vcc bus
Pad input or output circuit
D2 1N914
D1 1N914
-Vdd / Vee bus
Vcer input clamp
Pad
Absoption
circuit
Rb
Vee
CMOS input/output protection output
pad
Ouput Pad
V+
C1 20f
Pad/Pin
SCR
R1 190
R2 74
R3 74
C1 20f
V-
IC level SCR model
D1 PMLL4448 T1 Noname is more complex
OR
Input Pad input
pad
C1 20f
V-

Supply clamp circuits
Bipolar BVcer Clamp
V+
T1 !NPN
Avalanche generating
IS1 1u current - internal or external source
RB 500 RB s et by des ign
and process
V-
V+
T2 Noname
V-
NMOS Clamp
V+
NMOS parasitic
NPN trans istor
RB 500
≈
T3 !NPN
V-
Rsub 500
NPN bipolar on high-speed process
ON →
← OFF

NMOS parasitic bipolar transistor
Drain
(collector)
Gate n
I sub
Sub (base)
I
DS
I
C
R sub
P-sub/epi n p
Source
(emitter)

A commonly applied ESD protection method for analog integrated circuits
In+
In-
Input protection ultra low leakage diodes
Rs 1k
Rs 1k
V+
+
-
IOP1
Output protection
T1 !NPN
Rb 2k
Vo
V-
Power supply absorption device

INA168 ESD cell layouts
Input pin
ESD2 N-sinker – BL
ESD1 NPN B-E
Supply clamp
NPN transistor / resistor
Output pin
ESD7 NPN B-E
ESD8 N-sinker – BL

ESD pulse source
In+
VG1
In-
Rs 1k
Rs 1k
The ESD protection paths
V+
V+ pin at GND
+
-
IOP1
T1 !NPN
Rb 2k
Vout at
GND
Vo
V-
V- pin at GND

Input overdrive may activate
ESD protection circuits
VG2
VG1
VG2 unintended trans ients, noise
impuls es , etc.
Vi n+
TL1
V-
-
+
+
V+
VG1 intended
linear range signal
Vp = 2.25V, f = 100Hz
V+
V1 2.5
C1 100n
V2 2.5
U1 OPA364
V-
Vo
R3 10k
T
VG1
2.25
0.00
-2.25
1.00
VG2
500.00m
0.00
3.25
Vin+
500.00m
Vo
-2.25
2.50
0.00
-2.50
0.00
C2 100n
VG1 + VG2 sum may activate
ESD circuit on peaks
5.00m
10.00m
Time (s)
15.00m
20.00m

Intended signal
VG1
VG2
Input
EOS source
RI 1k
ESD cell paths may be activated during an
EOS event
V2 5
L2 50n
C2 1u
+ -
* L4 10n
Rs 1k
Rs 1k
+
-
IOP1
T1 can become a near short between supplies!
Vout
T1 !NPN
RL 10k
Rb 2k
V1 5
L1 50n
* L3 10n
C1 1u
+
RF 10k
* may no longer represent a nearzero impedance at high frequencies

A supply clamp transistor failure during resulting from an input EOS/ESD event
VG1
One channel of RGB
amplifier application
TL1 GRN OUT
R1 500
GRN IN
R4 75
R2 500
C2 10u
V-
+
-
R3 75
V+
+
+
C1 10u
+ -
OP1 !OPAMP
OUT
TERM
R5 2k
T1 !NPN
V+/V- wall-wart power s upply
without on/off switch
Vcer clamp transistor

EOS-related CMOS operational-amplifier field failures
•
TI quad CMOS operational amplifier failing unexpectedly in air conditioner application
• TI FA report indicated the operational amplifier die had carbonized material on die and pin 4 (V+) to pin 11 (V-) short
•
EOS analysis of the customer application input and output ESD circuits did not reveal any likely candidates

EOS-related CMOS operational-amplifier field failures
20 Vpk EOS on V+ line
•
A request for the Field Applications Engineers to observe and monitor the amplifier pins during the various operational cycles was made and provided
•
They found that a 20 Vpk pulse was appearing on the V+ line during operation of the air conditioner. The nominal supply voltage was +5 V
• The EOS was causing either the supply-to-supply ESD clamp to break down, or voltage breakdown of the amplifier transistor structures
• A higher voltage operational amplifier and a transient voltage suppressor on the V+ line were recommended

Input current limiting by external series-R
Where does the 10mA
I
OVERLOAD maximum originate?

Parasitic circuit latch testing
Compliance
Range +/-7.5V
I max 150mA
VG1
-
+
VCCS1
+
VS1 5
I/O hi gh
I/O low
Pi n under
test
+
A AM1
U1 OPA348
+
+
-
SW1
Input pins connected together
during output pin test
VS2 0
+
Ouput floats during input pi n tests
Current injection latch test
The continuous input overload current is set to < 1/10 th the JEDEC maximum latch test current (t ≤ 10ms)

Watch Vin during power up!
I in excessively high while supply ramps
T 30.0m
AM1
15.0m
0.0
3.50
VG1
1.75
0.00
5.00
VG2
2.50
0.00
3.50
VM1
1.75
0.00
0 10m 20m
Time (s)
30m 40m 50m

Instrumentation amplifier input protection
RG 25k
EXT
Vi n+
Vi n-
V+
Over-Vol tage
Protection
+
IOP1
-
R2 25k
Over-Vol tage
Protection
R1 25k
-
+
IOP2
R3 60k R5 60k
R4 60k
-
+
IOP3
R6 60k
V-
Vcm 0
Vd/2 1
Vo
Ref
Vi n+
Ib Comp 1n
Vbias 0
Vbias
+
IS1 10u
A1
+
-
IOP2
T1 !NPN
C1 6p
R1 25k
A3 +i n
A3 -in
A2 +
Mirror of
A1circuit
RG 25k
Ext
Vd/2 1
Vi n-
Over-Vol tage
Protecti on
T1 Noname T2 Noname D1 1N914

Excessive differential input over-voltage
Bipolar input operational amplifier
VG1
U1 OPA227
R2 1k
R1 500
V-
-
+
+
V+
V+
V1 15 V2 15
C1 100n C2 100n
V-
Vo
R3 1k
T 10
90%
8
6
4
2
10%
0
0.0
Possible occurrences
– When operating an operational amplifier as a comparator
– During slewing
Input-output voltage difference
1.0u
SR = 2.3V/us
2.0u
Time (s)
3.0u
4.0u
5.0u
Plot for illustrative purposes only!

OPA277 input-to-input differential over-voltage protection modern bipolar op-amps have input clamps
R1 500
V2 15
I in
20mA max
Vin-
Pulse
Source
Vin+
VG1
T28 !NPN
Gain stages and bias circuits
T23 !NPN
T41 !NPN
T44 !NPN
Vo
RL 1k
V1 15
V
G1
= 2V
D
+ (I in
R
1
) + V o
If V
O
= 0V, then:
I in
= (V
G1
– 2V
D
) ∕ R
1

Input overdrive of CMOS rail-to-rail IO chopper amplifiers
Back-to-back clamp diodes are inherent and internal to the chopper switch structures
•
When Vin exceeds a Vcm maximum Vo is forced to an output rail level
• The op-amp is forced outside of its linear operating range
• The feedback loop collapses and an input differential voltage develops
•
One clamp diode or the other becomes forward biased and the input bias current can increase tremendously
• This may limit the use of this type of operational amplifier as a comparator

Overload Recovery
Auto-zero CMOS
Operational-amplifiers
OPA335
Av = -50V/V
R1 2k R2 100k
Stepped from
50m V to 0m V
VG1
C1 100n
U1 OPA335
V-
-
+
+
V1 2.5
+ VM1
-
C2 100n
V2 2.5
V-
Vin
≥ Vs / Gain
Positive input
+50mV
0mV
0V
Negative output
≥ -2.5V
Negative input
0mV
-50mV
≤ 2.5V
Positive output
0V

Output inversion during input overdrive
U1 OPA234
VG1
Vi n 5Vp-p
+ 2.0Vdc
-
+
+
+
-
VM1
R1 50 V1 5 C1 10n
+4.5V
VG1
-0.5V
+4.5V
VM1
0V
Output inversion

Supply pin over-voltage protection
VG1
L1 100u Rs 5
5V Power
supply
LOAD
C1 1u RL 1k
+ VM1
-
Smoothing a transient with an RLC filter
• Transient amplitude effectively reduced
• Ringing dependent on
RLC values and load R
• Amplifier PSRR becomes important
T 10.0
VG1
7.5
5.0
5.5
VM1
5.0
4.5
0
1us transient riding
on 5V supply voltage
20u 40u
Time (s)
60u 80u 100u

Supply pin over-voltage protection
LOAD
Rs 10
VG1
5V Power
supply
Transient voltage suppression (TVS) diode
• 6.8V- 550V reverse standoff voltage
•Unidirectional & bidirectional models
•Ppk = 1.5kW (10 x 1000us) @ 25C
•Cj ≥ 1nF @ 20V
•Littlefuse no. 1.5KE6.8, etc.
C1 10n RL 1k
+ VM1
-
Vz = 6.8V
T 10.0
Z1 1N5342
VG1
7.5
5V 1us transient riding
on +5V supply line
5.0
7.0
VM1
5.8
4.5
0 20u zener diode used in simulation
no TVS model available
40u
Time (s)
60u 80u 100u

Supply pin over-voltage protection
Features
• Multilayer ceramic construction
• Operating voltage range V
M(DC)
= 5.5 to 120V
• Non-repetitive surge current (8/ 20us)
• Non-repetitive energy (10/ 1000us)
• response time <1ns for zinc oxide
• Inherent bidirectional clamping
• Wider temperature range and flatter response than solid-state TVS

Externally connected input protection devices
Transient voltage suppressors
For CMOS, bipolar and SiGe
Features:
Available from 5.6 to 18V
DC working voltage ≤ 18V
AC working voltage ≤ 14V
Turn-on-time <1ns
Repetitive spike capability watch capacitance uA J A pF

Externally connected input protection devices

Externally connected input protection devices
Schottky diodes provide enhanced input protection
VG1
V1 5
SD1 BAS40 C1 100n
U1 OPA374
+
+
SD2 BAS40
-
R1 5k
R2 5k
+ VM1
-
Features:
• Forward voltage V
F
≤ 380mV, I
F
= 1mA
• Forward current I
F
= 200mA max (cont.)
• Leakage current * I
R
≤ 100nA, V
R
= 30V
• Diode capacitance C tot
≤ 5pF, V
R
= 0V
* A small-signal silicon diode (IN4148) will likely turn on at lower voltage than the internal
ESD silicon diode and may exhibit lower leakage current than a Schottky diode.

Externally connected input protection devices

An important point about added protection devices in the signal circuit
• Protection components such as transient voltage suppressors (TVS), diodes and zener diodes all exhibit capacitance even when biased off
• The capacitance will vary to some extent with the voltage applied across the protection device
• Most often the capacitance does not have a linear capacitance to voltage relationship (voltage coefficient)
•
This non-linear capacitance to voltage relationship may increase distortion in the protected circuit
• It will be most evident in a very low THD circuits, but may not degrade performance significantly

Power Line Communications (PLC)
EOS environment – IEC61000-4-5
Open-circuit surge pulse test
4kV, 1.2us t front
, 50us t half-value

PLC – EOS protection
Actual protection scheme will vary with application and layout
High voltage MOV and low-voltage TVS clamping
Fast rectifier and
Schottky clamps
The internal output ESD cell is unlikely to withstand the open-circuit HV pulse
- latching is probable

In Summary
• EOS and ESD events may activate ESD protection but result in different outcomes
• Internal ESD circuits may sufficiently handle EOS
• Be aware of unique EOS situations such as power up and input slewing
• External EOS protection circuits will be required if device damage is likely to occur without it