Intel Hub
Architecture
Overview
®
Chapter 1
Copyright © 1996-2003 Intel Corp.
PC Chipset: Bus Architecture
Intel® Hub Architecture
OBJECTIVES: At the end of this section, the
student will be able to do the following:
 Explain
Intel® Hub Architecture block diagram
 Identify
Intel® Hub Link Bus attributes
 Explain
the MCH, GMCH and ICH block diagrams
 Explain
the FWH block diagram
 Describe
the CNR interface
IATT Web Site:http://iatt.intel.com
PC Chipset: Bus Architecture
 CH-1 Slide-2
M-1
Host Bus (PSB)
100/133/200MHz
64-bit
AGP Bus
System
Memory
Processor
North
Bridge
(MCH)
Clock
Gen
HubLink Bus
CNR
SM Bus
South
Bridge
(ICH)
PCI Bus
33 MHz 32-bit
LAN
LPC Bus
Audio
USB
Mouse
FWH
SIO
IDE
Keybrd
Floppy
Parallel
PC Chipset: Bus Architecture
Host Clock
PCI Clock
USB Clock
Hublink Clock
The Chipset
consists of the
North Bridge,
South Bridge
and
Firmware Hub
Serial
 CH-1 Slide-3
Intel® PC Chipsets
 Include
North Bridge, South Bridge and Firmware Hub
 Various
chipsets available from Intel to meet specific
performance requirements

Value PC (810, 815)
 Pentium
III or Celeron Processor
 SDRAM
 Integrated

Graphics controller (Direct AGP)
Mainstream & Performance PCs (845, 850)
 Pentium
4 Processor
 SDRAM,
DDR or RAMbus
 Support
for AGP, DVO or Direct AGP
 Support
for Hyper-Threading Technology (later 845’s)
PC Chipset: Bus Architecture
 CH-1 Slide-4
Chipset Components
 The

Northbridge may be either:
Memory Controller Hub (MCH)
 Interfaces
between the CPU and the rest of the system
 Memory
 AGP Bus
 Hublink Bus

Graphics and Memory Controller Hub (GMCH)
 Includes
integrated graphics accelerator
 Supports either: (depends on version)
» Direct AGP - fully integrated graphics engine - no
external AGP slot - used for “Value PC”
» or AGP 2.0 (with AGP slot)
 Support for analog video, Digital Video Out (DVO) and Display
Data Channel (DDC)
PC Chipset: Bus Architecture
 CH-1 Slide-5
M-1
Which device supports
"Direct AGP"?
1: MCH
2: ICH
3: GMCH
4: FWH
PC Chipset: Bus Architecture
 CH-1 Slide-6
Chipset Components
 The

South Bridge or I/O Controller Hub (ICH)
Interfaces to I/O devices
 PCI
Bus
 IDE
 USB
 LPC
 The
bus to Firmware Hub and Super I/O (Legacy I/O)
Firmware Hub (FWH)

Stores BIOS code/data in 512KB or 1MB flash memory

Random number generator

Can be reprogrammed in place
PC Chipset: Bus Architecture
 CH-1 Slide-7
 Proprietary
point-to-point interface between MCH and
ICH

Expandable to multiple Hublink bus structure in some
chipsets
 Eight
bit data bus, two strobe signals, 3 special signals

66.6MHz clock signal derived from AGP clock

May also be 16 bit data and/or 100MHz clock
 Data

can be transferred at 4 bytes per clock cycle
4 bytes x 66.6MHz clock = 266MB/sec
 Hublink
design and operation is Intel proprietary
PC Chipset: Bus Architecture
 CH-1 Slide-8
 Each
contain PCI devices which are designated with a
one byte ID--the MCH contains 2 devices; GMCH has 3.

Device 0: Host to Hub Bridge- Resides on PCI bus 0
 Connects
Host bus to PCI bus 0 interfaces with system
memory controller

Device 1: PCI to AGP Bridge- Resides on PCI bus 0
 Connects
 AGP
bus may be designated as BUS 2
 When

to AGP bus to extend outside the MCH
card is plugged into AGP slot it will be Bus 2:Device 0
Device 2: Graphics Accelerator (GMCH only) on PCI Bus 0
 Analog
 Digital
video out
 Display
PC Chipset: Bus Architecture
video out (VGA)
Data Channel (DDC for plug and play monitor)
 CH-1 Slide-9
MCH PCI Devices
ADDR DATA
CTRL
Host Bus
BUS 0
DEVICE 0
Host-Hub Bridge
B0:D0:F0
AGP Bus
(PCI Bus 2)
BUS 2
DEVICE 0
BUS 0
DEVICE 1
AGP Slot
B2:D0:F0
PCI-AGP Bridge
B0:D1:F0
System
Memory
Interface
SCS[11:1]#
SMA[12:1]
SBS[1:0]
SRAS#
SCAS#
SWE#
SDQ[63:0]
SCB[7:0]
RDCLK0
RDCLKIN
Logical
PCI Bus 0
Hub
Interface
PC Chipset: Bus Architecture
HL [11:0]
HL_STB
 CH-1 Slide-10
82815 GMCH PCI Devices
ADDR DATA
CTRL
Host Bus
BUS 0
DEVICE 0
Host-Hub Bridge
B0:D0:F0
AGP Bus
(PCI Bus 2)
BUS 2
DEVICE 0
BUS 0
DEVICE 1
AGP Slot
B2:D0:F0
PCI-AGP Bridge
B0:D1:F0
Analog Display Out
Digital Video Out
Display Data
Channel
PC Chipset: Bus Architecture
System
Memory
Interface
SCS[11:1]#
SMA[12:1]
SBS[1:0]
SRAS#
SCAS#
SWE#
SDQ[63:0]
SCB[7:0]
RDCLK0
RDCLKIN
Logical
PCI Bus 0
BUS 0
DEVICE 2
Graphics
Accelerator
B0:D2:F0
Hub
Interface
HL [11:0]
HL_STB
 CH-1 Slide-11
 The
ICH and MCH each contain PCI devices which are
designated with a 1 byte hex number--the ICH has three:

Device 1E: Hub to PCI Bridge- Resides on PCI bus 0
 Connects

Device 1F: Multi-function- resides on PCI bus 0
 PCI
to LPC Bridge for interface to firmware hub and Super I/O
 IDE
controller
 SMB
 Two

PCI bus 0 to PCI bus1 to extend outside the ICH
controller
USB controllers
 AC97
Audio Controller
 AC97
Modem Controller
Device 08: LAN controller- Resides on PCI bus 1
 Supports
PC Chipset: Bus Architecture
10/100 Mbit/sec Ethernet and 1Mbit/sec Home PNA
 CH-1 Slide-12
ICH PCI Devices
HL [11:0]
Logical
PCI Bus 0
LAD [3:0]
LFRAME#
LDRQ[0:1]#
PDCS1#
PDA[2:1]
PDD[15:0]
PDDREQ
PDDACK#
PDIOR#
PDIOW#
PIORDY
HL_STB
Hub
Interface
PCI Bus 1
BUS 0
DEVICE 1E
HUB-PCI Bridge
B0:D1E:F0
PCI-LPC Bridge
B0:D1F:F0
LAN Cntr.
B1:D8:F0
IDE Controller
B0:D1F:F1
USB Ctr. 2
B0:D1F:F4
USBP3[P:N]
OC[3:2]#
SMB Controller
B0:D1F:F3
SMBDATA
SMBCLK
Audio Ctr.
B0:D1F:F5
Modem Ctr
B0:D1F:F6
LAN_CLK
LAN_RXD[2:0]
LAN_TXD[2:0]
USBP0[P:N]
USBP1[P:N]
OC[1:0]#
USBP2[P:N]
USB Ctr. 1
B0:D1F:F2
DEVICE 1F
PC Chipset: Bus Architecture
BUS 1
DEVICE 8
AC97
Controller
AC_RST#
AC_SYNC
AC_BIT_CLK
AC_SDOUT
AC_SDIN0
AC_SDIN1
 CH-1 Slide-13
ICH PCI Devices
 Chipset
data books use DECIMAL numbers to identify
devices: e.g., Device 1Eh = 30(10) ; Device 1Fh = 31(10)
PCI Bus 1
Hub
Interface
Logical PCI
Bus 0
BUS 0
DEVICE 1E
HUB-PCI Bridge
B0:D1E:F0
PCI-LPC Bridge
B0:D1F:F0
BUS 1
DEVICE 8
LAN Cntr.
B1:D8:F0
USB Ctr. 1
B0:D1F:F2
IDE Controller
B0:D1F:F1
USB Ctr. 2
B0:D1F:F4
SMB Controller
B0:D1F:F3
Audio Ctr.
B0:D1F:F5
DEVICE 1F
Modem Ctr
B0:D1F:F6
PC Chipset: Bus Architecture
AC97
Controller
Chipset Data
Book Description
Bus:Dev:FN
(in decimal)
Functional
Description
0 : 30 : 0
Hub-PCI Bridge
0 : 31 : 0
PCI-LPC Bridge
0 : 31 : 1
IDE Ctlr
0 : 31 : 2
USB Ctlr 1
0 : 31 : 3
SMBus Ctlr
0 : 31 : 4
USB Ctlr 2
0 : 31 : 5
Audio Ctlr
0 : 31 : 6
Modem Ctlr
1: 8: 0
LAN Ctlr
 CH-1 Slide-14
M-1
The MCH and ICH are
connected together by:
1: the PCI Bus
2: the LPC Bus
3: the Hublink Bus
4: the ISA Bus
PC Chipset: Bus Architecture
 CH-1 Slide-15
 The

FWH contains
512KB or 1MB of Flash ROM for storing BIOS code/data
 Arranged

Block Lock Registers
 One

into 64KB lockable blocks
for each 64KB block to lock read or write ability
General Purpose Register
 Reflects
status of FGPI pins
 Typical use of FGPI pins are to gather misc. data such as jumper
settings (BIOS recovery jumper)

Random Number Generator
 Can
produce Random Numbers used for data encryption
 RNG
PC Chipset: Bus Architecture
may or may not be present (depends of version of FWH)
 CH-1 Slide-16
Firmware Hub (FWH)
Block
Lock
Regs
LPC Bus
LFRAME / FWH4
LAD[3:0] / FWH[3:0]
ID[3:0]
FGPI[4:0]
FWH
Interface
General Purpose
Inputs
Random
Number
Generator
Flash
ROM
512KB
(1MB)
Device shown as used in “FWH Mode”
See chapter 3 for details on “AAMux Mode
PC Chipset: Bus Architecture
 CH-1 Slide-17

The CNR provides the PC Industry the opportunity to
deliver a flexible and cost reduced method to
implement subsystems widely used in "connected PCs".

LAN

Wireless

Home networking

Audio

MODEM & DSL

USB

The CNR Specification is an open industry specification
and is supported by OEMs, IHV card manufacturers,
silicon suppliers and Microsoft.

CNR Spec. calls for cards to be PnP: an EEPROM on
the CNR card contains configuration information.

Upper three SMB Address bits of CNR card determined
by pull up resistors on the system board.
PC Chipset: Bus Architecture
 CH-1 Slide-18
+5v
CNR Interface to ICH
M-3
EE_SHCLK
ICH
CNR
EEPROM
Interface
BUS 1
DEVICE 8
BUS 0
DEVICE 1F
LAN Cntr.
B1:D8:F0
USB Ctr. 2
B0:D1F:F4
SMB_A2
EE_DIN
EE_DOUT
SMB_A1
EE_CS
SMB_A0
LAN_CLK
LAN_RXD[2:0]
Used to strap
lower three
bits of CNR
SMB Address
LAN_TXD[2:0]
* USB1[P:N]
* OC#
OC
(in this case: 110)
SMBDATA
SMB Controller
B0:D1F:F3
SMBCLK
AC_RST#
Audio Ctr.
B0:D1F:F5
Modem Ctr
B0:D1F:F6
AC_SYNC
AC97
Controller
AC_BIT_CLK
AC_SDOUT
CNR
Connector
Used to
communicate
with EEPROM
on CNR card
(see appendix)
AC_SDIN0
AC_SDIN1
PC Chipset: Bus Architecture
* USB lines may alternatively be routed from USB Host Controller ASIC
+12v
-12v
+3.3v
+5v
 CH-1 Slide-19
CNR Connector Pinout
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
PC Chipset: Bus Architecture
RESERVED
RESERVED
RESERVED
GND
RESERVED
RESERVED
GND
LAN_TXD1
LAN_RSTSNC
GND
LAN_RXD2
LAN_RXD0
GND
RESERVED
+5Vdual
USB_OC#
GND
-12V
+3.3VD
KEY
GND
EE_DOUT
EE_SHCLK
GND
SMB_A0
SMB_SCL
CDC_DN_ENAB#
GND
AC97_SYNC
AC97_SDATA_OUT
AC97_BITCLK
RESERVED
RESERVED
GND
RESERVED
RESERVED
GND
LAN_TXD2
LAN_TXD0
GND
LAN_CLK
LAN_RXD1
RESERVED
USB+
GND
USB–
+12V
GND
+3.3Vdual
+5VD
KEY
GND
EE_DIN
EE_CS
SMB_A1
SMB_A2
SMB_SDA
AC97_RESET#
AC97_SDATA_IN2
AC97_SDATA_IN1
AC97_SDATA_IN0
GND
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A1
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
 CH-1 Slide-20
M-4
Chapter 1 Quiz
1) The FWH is accessed via the:
A) LPC Bus
B) PCI Bus
C) Hublink Bus
D) Beaverton-Hillsdale Highway Bus
2) Which chip controls PCI Bus 1?
A) ICH
B) MCH
C) FWH
D) SIO
3) The Intel® Hublink™ Bus can transfer data at 3.2GB/s
(True / False)
4) Which of the following devices is routed to the CNR
connector?
A) IDE controller
C) AGP controller
B) Floppy controller D) Audio Controller
PC Chipset: Bus Architecture
 CH-1 Slide-21
REVIEW & SUMMARY
 Intel®

Hub Architecture
Contains:
 MCH
(GMCH in value PC applications)
 ICH
 FWH
 Intel®
Hub Link™ Bus attributes

Can transfer data between the MCH and ICH at 266MB/s

Intel® Proprietary
PC Chipset: Bus Architecture
 CH-1 Slide-22
REVIEW & SUMMARY
 MCH
and GMCH Control Memory and Graphics
MCH: AGP controller
 GMCH: Integrated Graphics Accelerator (Direct AGP)

 ICH

contains:
Hub to PCI Bridge
 Connects
PCI bus 0 to PCI bus1 to extend outside the ICH
PCI to LPC Bridge for interface to firmware hub and
Super I/O
 IDE controller
 SMB controller
 Two USB controllers
 AC97 Audio Controller
 AC97 Modem Controller

PC Chipset: Bus Architecture
 CH-1 Slide-23
REVIEW & SUMMARY
 Firmware
Hub

Contains BIOS

Utilizes Flash ROM technology
 Can
be reprogrammed “in place” on the motherboard
 Communications

and Networking Riser
Interface to devices in ICH:
 MODEM
 Audio
controller
controller
 USB
controller
 SMB
Controller
PC Chipset: Bus Architecture
End of Chapter 1
 CH-1 Slide-24