How do you make Area Constraints with PlanAhead? © 2009 Xilinx, Inc. All Rights Reserved Xilinx Confidential – Internal After completing this module, you will able to: Add Pblocks to your design with the Hierarchy viewer, Schematic viewer, and the Timing Report generator Page 2 Xilinx Confidential – Internal • Unpublished Work © Copyright 2009 Xilinx Pblocks Pblocks are used to group logic – Assignment of a Pblock to a range of locations on the die makes it an area constraint – When starting to floorplan, the intent is to minimize the routing between Pblocks – A single Pblock should not occupy over 20 percent of the design resources • Page 3 If so, try to make two Pblocks from logic at a lower level Xilinx Confidential – Internal • Unpublished Work © Copyright 2009 Xilinx UCF Syntax Pblocks form a group – INST "usbEngine1" AREA_GROUP = "pblock_usbEngine1"; Area constraints form a range constraint – AREA_GROUP "pblock_usbEngine1“ RANGE=SLICE_X0Y60:SLICE_X43Y119; Page 4 Xilinx Confidential – Internal • Unpublished Work © Copyright 2009 Xilinx Making a Pblock To create a Pblock – Select a level of hierarchy or a component from the Netlist window and use the popup menu > New Pblock – Select a block from the Hierarchy viewer and use the popup menu > New Pblock command – From a timing report, use the popup menu > New Pblock command Page 5 Xilinx Confidential – Internal • Unpublished Work © Copyright 2009 Xilinx Auto-create Pblock From the horizontal toolbar use the Tools > Auto-create Pblocks command If more modules exist than the total number of Pblocks specified, it will create Pblocks for the largest modules Page 6 Xilinx Confidential – Internal • Unpublished Work © Copyright 2009 Xilinx Device Viewer Create or view Pblocks easily using the Device viewer. The vertical toolbar has the following controls – Show/Hide I/O Nets – Show/Hide Bundle Nets – Show/Hide Loc Constraints – Show connections for selected instances – Draw Pblock Page 7 Xilinx Confidential – Internal • Unpublished Work © Copyright 2009 Xilinx Pblock Properties After selecting a Pblock use the popup menu > Pblock Properties command – Shows device utilization of Pblock • • • • • Page 8 CLB Block RAM DSP slice Number of clocks Best way to determine Xilinx Confidential – Internal • Unpublished Work © Copyright 2009 Xilinx Analyzing Connectivity Use the Show Connectivity popup menu command to identify – Widely dispersed routing – Tightly clumped logic modules Use Shift-click to select source and destination logic – Use the popup menu > Show Connectivity command You can use this command sequentially to expand a cone of logic Page 9 Xilinx Confidential – Internal • Unpublished Work © Copyright 2009 Xilinx Analyzing Timing Results Examine your timing results – Generated timing reports make it easy to display all or some paths that are failing to meet a timing constraint • • • Helps you see patterns Simply select the paths to be displayed from the report or use Shift + click to select a group of paths To remove, reselect the group and click the Hide All Timing Paths button from the vertical toolbar – After selecting a path use the popup menu > View Path Report command to see a more detailed timing report Page 10 Xilinx Confidential – Internal • Unpublished Work © Copyright 2009 Xilinx Analyzing Timing Results with the Schematic View critical paths with the Schematic viewer – Select the path(s) and use the popup menu > Schematic command – Helps you visualize the levels of hierarchy – Analyze logic modules for floorplanning – Create Pblocks from selected modules – Use the popup menu > Select Primitive Parents command to select the smallest modules containing all of the selected primitives Page 11 Xilinx Confidential – Internal • Unpublished Work © Copyright 2009 Xilinx Visualizing Hierarchy Hierarchy view displays logic hierarchy – Visualize relative size and location of selected logic in Hierarchy view – Easily select parent modules of selected logic to floorplan – Use the popup menu > Show Hierarchy command to view a selected module with this view – Note that this only shows size; it does not show how many signals are connected between the modules – Likewise, after selecting a component, use the popup menu > New Pblock command to assign the logic Page 12 Xilinx Confidential – Internal • Unpublished Work © Copyright 2009 Xilinx Case Study Design has been implemented with no area constraints Import the design into the PlanAhead™ software and perform a timing analysis – Display all of the paths that are failing to meet timing to get ideas – Note the hierarchical blocks that are part of the failing paths – In this example, note that there are long routing delays between some of the block RAMs Page 13 Xilinx Confidential – Internal • Unpublished Work © Copyright 2009 Xilinx Case Study Failing paths displayed with the Schematic viewer – Confirmed from the timing reports that most of these paths can be constrained within a few area constraints – In this case, usbEngine1 is a good candidate, but there may be others Page 14 Xilinx Confidential – Internal • Unpublished Work © Copyright 2009 Xilinx Case Study Placement reviewed in the Device view – Timing critical nets and logic in green (20% of design) – Note the use of block RAM • Is there anything wrong? – Note the pin layout • Page 15 Is there anything wrong? Xilinx Confidential – Internal • Unpublished Work © Copyright 2009 Xilinx Case Study Top-level floorplan examined (this is just Pblocks with no area constraints) 3 4 – These will have to be made by the user and are based on the design hierarchy • The white box is usbEngine1 – Note the green lines • • 2 5 These are the connections from logic to I/O pins Is there anything wrong? – Note the red lines • • Page 16 They represent the greatest concentration of routes between hierarchical blocks Where should each Pblock go? 1 Xilinx Confidential – Internal • Unpublished Work © Copyright 2009 Xilinx 6 Case Study If all the timing errors were only in usbEngine1, then an area constraint for Pblock 5 might be able to be made 3 4 – Saves some work The block RAMs and DSP slices within usbEngine1 could also be placed in the upper left corner of the die 2 5 1 – This would in effect force the tools to place the logic closer to its I/O pins Page 17 Xilinx Confidential – Internal • Unpublished Work © Copyright 2009 Xilinx 6 Case Study There were also timing errors in the usbEngine0 component – In the end, this also required similar floorplanning So the final solution is shown here Page 18 Xilinx Confidential – Internal • Unpublished Work © Copyright 2009 Xilinx UCF Syntax The following constraints are the output of this exercise – INST "usbEngine1" AREA_GROUP = "pblock_usbEngine1"; – AREA_GROUP "pblock_usbEngine1" RANGE=SLICE_X0Y60:SLICE_X43Y119; – AREA_GROUP "pblock_usbEngine1" RANGE=DSP48_X0Y24:DSP48_X2Y47; – AREA_GROUP "pblock_usbEngine1" RANGE=RAMB18_X0Y24:RAMB18_X2Y47; – AREA_GROUP "pblock_usbEngine1" RANGE=RAMB36_X0Y12:RAMB36_X2Y23; Page 19 Xilinx Confidential – Internal • Unpublished Work © Copyright 2009 Xilinx List of Questions (Revisited) In hindsight, maybe there could have been a few more questions – Were proper pin planning decisions made? – Is there any central logic that needs to be placed in the middle of the die? – Are all my area constraints touching appropriately? – Should any of my area constraints be used to place logic near dedicated hardware (such as GTs, the PCI core, or memory controllers, for example)? Page 20 Xilinx Confidential – Internal • Unpublished Work © Copyright 2009 Xilinx Summary Pblocks – Are used to group logic – Support a user-programmable utilization • • 90%+ for low speed 70–87% for high speed There are a number of utilities in the PlanAhead software that can help you make good area constraints – Hierarchy viewer, Schematic viewer, and Timing Report generator – Automatic Pblock assignment and placement Page 21 Xilinx Confidential – Internal • Unpublished Work © Copyright 2009 Xilinx More Information To learn more, visit the PlanAhead tool web site www.xilinx.com/planahead – Articles, documentation, white papers, and training enrollment User Guide – PlanAhead Software Tutorial, Design Analysis and Floorplanning for Performace, UG676 – Floorplanning Methodology Guide, UG633 View the PlanAhead tool video demonstrations – Quick Tour of the PlanAhead Design and Analysis Tool – I/O pin planning with PinAhead Technology – Improve Design Performance with the PlanAhead Design and Analysis tool Xilinx Confidential – Internal • Unpublished Work © Copyright 2009 Xilinx Where Can I Learn More? Xilinx Training – www.xilinx.com/training • Xilinx tools and architecture courses • Hardware description language courses • Basic FPGA architecture, Basic HDL Coding Techniques, and other free training videos! Page 23 Xilinx Confidential – Internal • Unpublished Work © Copyright 2009 Xilinx Trademark Information Xilinx is disclosing this Document and Intellectual Propery (hereinafter “the Design”) to you for use in the development of designs to operate on, or interface with Xilinx FPGAs. Except as stated herein, none of the Design may be copied, reproduced, distributed, republished, downloaded, displayed, posted, or transmitted in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise, without the prior written consent of Xilinx. Any unauthorized use of the Design may violate copyright laws, trademark laws, the laws of privacy and publicity, and communications regulations and statutes. Xilinx does not assume any liability arising out of the application or use of the Design; nor does Xilinx convey any license under its patents, copyrights, or any rights of others. You are responsible for obtaining any rights you may require for your use or implementation of the Design. Xilinx reserves the right to make changes, at any time, to the Design as deemed desirable in the sole discretion of Xilinx. Xilinx assumes no obligation to correct any errors contained herein or to advise you of any correction if such be made. Xilinx will not assume any liability for the accuracy or correctness of any engineering or technical support or assistance provided to you in connection with the Design. THE DESIGN IS PROVIDED “AS IS" WITH ALL FAULTS, AND THE ENTIRE RISK AS TO ITS FUNCTION AND IMPLEMENTATION IS WITH YOU. YOU ACKNOWLEDGE AND AGREE THAT YOU HAVE NOT RELIED ON ANY ORAL OR WRITTEN INFORMATION OR ADVICE, WHETHER GIVEN BY XILINX, OR ITS AGENTS OR EMPLOYEES. XILINX MAKES NO OTHER WARRANTIES, WHETHER EXPRESS, IMPLIED, OR STATUTORY, REGARDING THE DESIGN, INCLUDING ANY WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND NONINFRINGEMENT OF THIRD-PARTY RIGHTS. IN NO EVENT WILL XILINX BE LIABLE FOR ANY CONSEQUENTIAL, INDIRECT, EXEMPLARY, SPECIAL, OR INCIDENTAL DAMAGES, INCLUDING ANY LOST DATA AND LOST PROFITS, ARISING FROM OR RELATING TO YOUR USE OF THE DESIGN, EVEN IF YOU HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. THE TOTAL CUMULATIVE LIABILITY OF XILINX IN CONNECTION WITH YOUR USE OF THE DESIGN, WHETHER IN CONTRACT OR TORT OR OTHERWISE, WILL IN NO EVENT EXCEED THE AMOUNT OF FEES PAID BY YOU TO XILINX HEREUNDER FOR USE OF THE DESIGN. YOU ACKNOWLEDGE THAT THE FEES, IF ANY, REFLECT THE ALLOCATION OF RISK SET FORTH IN THIS AGREEMENT AND THAT XILINX WOULD NOT MAKE AVAILABLE THE DESIGN TO YOU WITHOUT THESE LIMITATIONS OF LIABILITY. The Design is not designed or intended for use in the development of on-line control equipment in hazardous environments requiring fail-safe controls, such as in the operation of nuclear facilities, aircraft navigation or communications systems, air traffic control, life support, or weapons systems (“High-Risk Applications”). Xilinx specifically disclaims any express or implied warranties of fitness for such High-Risk Applications. You represent that use of the Design in such High-Risk Applications is fully at your risk. © 2009 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, and other designated brands included herein are trademarks of Xilinx, Inc. All other trademarks are the property of their respective owners. Xilinx Confidential – Internal • Unpublished Work © Copyright 2009 Xilinx