Metal Oxide Semiconductor Field
Effect Transistor (MOSFET)
Dr. M A ISLAM
IIUC
Different types of FETs
• Junction FET (JFET)
• Metal-Oxide-Semiconductor FET
(MOSFET)
• Metal-Semiconductor FET (MESFET)
M A ISLAM, EEE, IIUC
Different types of FETs
• Junction FET (JFET)
M A ISLAM, EEE, IIUC
Different types of FETs
• Metal-Oxide-Semiconductor FET (MOSFET)
M A ISLAM, EEE, IIUC
Different types of FETs
• Metal-Semiconductor FET (MESFET)
M A ISLAM, EEE, IIUC
Comparison of BJT and MOSFET
• The BJT can achieve much higher gm than a MOSFET, for a
given bias current, due to its exponential I-V
characteristic.
M A ISLAM, EEE, IIUC
MOSFET Circuit
M A ISLAM, EEE, IIUC
MOSFET Symbol Circuit
M A ISLAM, EEE, IIUC
Introduction

A
MOSFET
(Metal
Oxide
Semiconductor
Field
Effect Transistor) is a semiconductor device.

A MOSFET is most commonly used in the field of power
electronics.

A semiconductor is made of manufactured material that acts
neither like a insulator nor a conductor.
M A ISLAM, EEE, IIUC
MOSFET
• Basic Properties of MOSFET
–
–
–
–
–
–
Unipolar device
Very high input impedance
Capable of power gain
3/4 terminal device, G, S, D, B
Two possible device types: enhancement mode; depletion mode
Two possible channel types: n-channel; p-channel
• Importance for LSI/VLSI
– Low fabrication cost
– Small size
– Low power consumption
• Applications
– Microprocessors
– Memories
– Power Devices
M A ISLAM, EEE, IIUC
Structure of MOSFET
M A ISLAM, EEE, IIUC
Schematic structure of MOSFET
M A ISLAM, EEE, IIUC
MOSFET-Basic Structure
M A ISLAM, EEE, IIUC
Basic MOSFET (n-channel)
• Increasing the +ve gate
voltage pushes the p-type
holes further away and
enlarges the thickness of
the created channel.
• As a result increases the
amount of current which
can go from source to
drain — this is why this
kind of transistor is
called an enhancement
mode device.
M A ISLAM, EEE, IIUC
Basic MOSFET (n-channel)
• An n-channel MOS transistor. The gate-oxide thickness, TOX, is
approximately 100 angstroms (0.01 mm). A typical transistor length,
L = 2 l. The bulk may be either the substrate or a well. The diodes
represent pn-junctions that must be reverse-biased
M A ISLAM, EEE, IIUC
Basic MOSFET (p-channel)
• These behave in a similar way, but they pass current
when a -ve gate voltage creates an effective p-type
channel layer under the insulator.
• By swapping around p-type for n-type we can make
pairs of transistors whose behaviour is similar except
that all the signs of the voltages and currents are
reversed.
• Pairs of devices like this care called complimentary
pairs.
M A ISLAM, EEE, IIUC
M A ISLAM, EEE, IIUC
• In an n-channel MOSFET, the channel is
made of n-type semiconductor, so the
charges free to move along the channel are
negatively charged (electrons).
• In a p-channel device the free charges which
move from end-to-end are positively
charged (holes).
M A ISLAM, EEE, IIUC
Working principle of MOSFET

A metal–oxide–semiconductor field-effect transistor (MOSFET) is
based on the modulation of charge concentration by a MOS
capacitance between a body electrode and a gate electrode located
above the body and insulated from all other device regions by a gate
dielectric layer which in the case of a MOSFET is an oxide, such as
silicon dioxide.
M A ISLAM, EEE, IIUC
Working principle of MOSFET

If dielectrics other than an oxide such as silicon dioxide (often referred
to as oxide) are employed the device may be referred to as a metal–
insulator–semiconductor FET (MISFET).

Compared to the MOS capacitor, the MOSFET includes two additional
terminals (source and drain), each connected to individual highly
doped regions that are separated by the body region.
M A ISLAM, EEE, IIUC
N and P channel of MOSFET
M A ISLAM, EEE, IIUC
N and P channel of MOSFET

If the MOSFET is an n-channel or nMOS FET, then the source and
drain are 'n+' regions and the body is a 'p' region.

If the MOSFET is a p-channel or pMOS FET, then the source and
drain are 'p+' regions and the body is a 'n' region.
M A ISLAM, EEE, IIUC
Cross section of NMOS with
channel- OFF state
M A ISLAM, EEE, IIUC
Cross section of NMOS without
channel- OFF state
M A ISLAM, EEE, IIUC
Working principle of MOSFET

When a negative gate-source voltage (positive source-gate) is
applied, it creates a p-channel at the surface of the n region,
analogous to the n-channel case, but with opposite polarities of
charges and voltages.

When a voltage less negative than the threshold value (a negative
voltage for p-channel) is applied between gate and source, the channel
disappears and only a very small sub threshold current can flow
between the source and the drain.
M A ISLAM, EEE, IIUC
Working principle of MOSFET
M A ISLAM, EEE, IIUC
Working principle of MOSFET

The device may comprise a Silicon On Insulator (SOI) device in
which a Buried Oxide (BOX) is formed below a thin semiconductor
layer.

If the channel region between the gate dielectric and a Buried
Oxide (BOX) region is very thin, the very thin channel region is
referred to as an Ultra Thin Channel (UTC) region with the source
and drain regions formed on either side thereof in and/or above the
thin semiconductor layer.
M A ISLAM, EEE, IIUC
Working principle of MOSFET

Alternatively, the device may comprise a Semiconductor On
Insulator (SEMOI) device in which semiconductors other than
silicon are employed.

When the source and drain regions are formed above the channel in
whole or in part, they are referred to as Raised Source/Drain (RSD)
regions
M A ISLAM, EEE, IIUC
I-V Characteristics of MOSFET
M A ISLAM, EEE, IIUC
I-V Characteristics of MOSFET
M A ISLAM, EEE, IIUC
I-V Characteristics of MOSFET
M A ISLAM, EEE, IIUC
Ideal Output Characteristics of MOSFET
M A ISLAM, EEE, IIUC
Ideal Transfer Characteristics of MOSFET
M A ISLAM, EEE, IIUC
Subthreshold region
M A ISLAM, EEE, IIUC
Channel Length
M A ISLAM, EEE, IIUC
MOSFET Dimensions - Trend
M A ISLAM, EEE, IIUC
MOSFET scaling scenario
M A ISLAM, EEE, IIUC
Voltage Scaling
M A ISLAM, EEE, IIUC
Power Supply Voltage
M A ISLAM, EEE, IIUC
Threshold Voltage
M A ISLAM, EEE, IIUC
Threshold Voltage
M A ISLAM, EEE, IIUC
Gate Oxide Thickness
M A ISLAM, EEE, IIUC
Channel Profile Evolution
M A ISLAM, EEE, IIUC
MOSFET Capacitances
M A ISLAM, EEE, IIUC
MOSFET Capacitances
M A ISLAM, EEE, IIUC
Overlap Capacitance
M A ISLAM, EEE, IIUC
Gate Resistance
M A ISLAM, EEE, IIUC
Components of Cin and Cout
M A ISLAM, EEE, IIUC
New materials needed for scaling
• Since the early 1980s, the materials used for
integrated MOSFET on silicon substrates have not
changed greatly.
• The gate “metal” is made from highly-doped
polycrystalline Si.
• The gate oxide is silicon dioxide.
• For the smallest devices, these materials will need
to be replaced.
M A ISLAM, EEE, IIUC
New Gate Oxide
• The capacitance per area of the gate oxide is
• Scaled MOSFETs require larger Cox, which has
been achieved with smaller tox.
• Increasing K can also increase Cox, and other
oxides, “high-K dielectrics” are being developed,
including for example, mixtures of HfO2 and
Al2O3.
M A ISLAM, EEE, IIUC
New Gate Metal
• The doped polycrystalline silicon used for
gates has a very thin depletion layer,
approximately 1 nm thick, which causes
scaling problems for small devices.
• Others metals are being investigated for
replacing the silicon gates, including
tungsten and molybdenum.
M A ISLAM, EEE, IIUC
Much of new research depends on reducing S !
• Increase ‘q’ by collective motion (e.g. relay)
Ghosh, Rakshit, Datta, NL ‘03
• Effectively reduce N through interactions
Salahuddin, Datta
• Negative capacitance
Salahuddin, Datta
• Non-thermionic switching (T-independent)
Appenzeller et al, PRL
• Nonequilibrium switching
Li, Ghosh, Stan
• Impact Ionization
Plummer
M A ISLAM, EEE, IIUC
Removing the substrate:
Silicon on Insulator (SOI)
• For high-frequency circuits (about 5 GHz and
above), capacitive coupling to the Si substrate
limits the switching frequency.
• Also, leakage into the substrate from the small
devices can cause extra power dissipation.
• These problems are being avoided by making
circuits on insulating substrates (either sapphire
or silicon dioxide) that have a thin, approximately
100 nm layer of crystalline silicon, in which the
MOSFETs are fabricated.
M A ISLAM, EEE, IIUC
Silicon on Insulator (SOI)
• SOI — silicon on insulator, refers to placing a thin
layer of silicon on top of an insulator such as SiO2.
• The devices will be built on top of the thin layer of
silicon.
• The basic idea of SOI is to reduced the parasitic
capacitance and hence faster switching speed.
M A ISLAM, EEE, IIUC
Silicon on Insulator (SOI)
• Every time a transistor is turned on, it must
first charge all of its internal (parasitic)
capacitance before it can begin to conduct.
• The time it takes to charge up and discharge
(turn off) the parasitic capacitance is much
longer than the actual turn on and off of the
transistor.
• If the parasitic capacitance can be reduced,
the transistor can be switched faster —
performance.
M A ISLAM, EEE, IIUC
Silicon on Insulator (SOI)
• One of the major source of parasitic
capacitance is from the source and drain to
substrate junctions.
• SOI can reduced the capacitance at the
source and drain junctions significantly —
by eliminating the depletion regions
extending into the substrate.
M A ISLAM, EEE, IIUC
SOI CMOS
• Silicon-on-insulator CMOS offers a 20–35%
performance gain over bulk CMOS.
• As the technology moves to the 0.13-µm
generation, SOI is being used by more companies,
and its application is spreading to lower-end
microprocessors and SRAMs.
• Some of the recent applications of SOI in highend microprocessors and its upcoming uses in
low-power, radio-frequency (rf) CMOS,
embedded DRAM (EDRAM), and the integration
of vertical SiGe bipolar devices on SOI are
described.
M A ISLAM, EEE, IIUC
M A ISLAM, EEE, IIUC
Illustrations of silicon transistors
a, A traditional n-channel MOSFET uses a highly doped n-type polysilicon gate electrode, a
highly doped n-type source/drain, a p-type substrate, and a silicon dioxide or oxynitride gate
dielectric.
b, A silicon-on-insulator (SOI) MOSFET is similar to the traditional MOSFET except the
active silicon is on a thick layer of silicon dioxide. This electrical isolation of the silicon
reduces parasitic junction capacitance and improves device performance.
c, A finFET is a three-dimensional version of a MOSFET. The gate electrode wraps around a
confined silicon channel providing improved electrostatic control of the channel electrons.
M A ISLAM, EEE, IIUC
Avalanche and Punch-Through (D)
• For very large VDS, IDS increases rapidly due to drain
junction avalanche.
• Can give rise to parasitic bipolar action.
• In short channel transistors, the drain depletion region
may reach the source depletion region giving rise to
‘Punch Through’.
M A ISLAM, EEE, IIUC
What’s Pinch off?
V0G
V0G
VG
VG
0
0
0
VD
Now add in the drain voltage to drive a current. Initially you get an
increasing current with increasing drain bias
When you reach VDsat = VG – VT, inversion is disabled at the drain end
(pinch-off), but the source end is still inverted
The charges still flow, just that you can’t draw more current
with higher drain bias, and the current saturates
M A ISLAM, EEE, IIUC
l and L
• The effect of channel-length modulation (l) is less for a
long-channel (L) MOSFET than for a short-channel
MOSFET.
M A ISLAM, EEE, IIUC
Square law theory of MOSFETs
I = meff ZCox[(VG – VT )VD- VD2/2]/L,
I = meff ZCox(VG – VT )2/2L,
VD < VG - VT
VD > VG - VT
J = qnv
n ~ Cox(VG – VT )
v ~ meffVD /L
M A ISLAM, EEE, IIUC
Ideal Characteristics of n-channel
enhancement mode MOSFET
M A ISLAM, EEE, IIUC
Drain current for REALLY small VD
Z
1 2

I D  m nCi  VG  VT VD  VD 
L
2


Z
I D  m nCi VG  VT VD 
L
VD  VG  VT 
Linear operation
Channel Conductance:
ID
Z
gD 
 m nCi (VG  VT )
VD V
L
G
Transconductance:
I D
Z
gm 
 m nCiVD
VG V
L
D
M A ISLAM, EEE, IIUC
In Saturation
• Channel Conductance:
I D
gD 
0
VD V
G
ID sat 
Z
2
m nCi VG  VT 
2L
• Transconductance:
gm 
I D
Z
 m nCi VG  VT 
VG V
L
D
M A ISLAM, EEE, IIUC
Equivalent Circuit – Low Frequency AC
I D
I D
I D 
VD 
VG
VD V
VG V
G
D
i  g D v d  g mv g
• Gate looks like open circuit
• S-D output stage looks like current
source with channel conductance
M A ISLAM, EEE, IIUC
Equivalent Circuit – Higher Frequency AC
• Input stage looks like capacitances
gate-to-source(gate) and gate-todrain(overlap)
M A ISLAM, EEE, IIUC
Equivalent Circuit – Higher Frequency AC
• Input circuit:
i in  jCgs  Cgd v g  j 2fCgatev g
i out  g mv g
• Input capacitance is mainly gate
capacitance
i out
gm
i in
• Output circuit:
gm 

2fCgate
I D
Z
 m nCiVD
VG V
L
D
M A ISLAM, EEE, IIUC
Maximum Frequency (not in saturation)
• Ci is capacitance per unit area and
Cgate is total capacitance of the gate
Cgate  Ci ZL
• F=fmax when gain=1 (iout/iin=1)
fmax
gm

2C gate
Z
m nVDCi
m nVD
L
fmax 

2IIUC
Ci ZL 2L2
M A ISLAM, EEE,
Maximum Frequency (not in saturation)
f max 
max
m nVD
2L2
1

L/v
v  mVD / L
(Inverse transit time)
M A ISLAM, EEE, IIUC
Switching Speed, Power Dissipation
ton = CoxZLVD/ION
Trade-off: If Cox too small, Cs and Cd take over and you lose
control of the channel potential (e.g. saturation)
(DRAIN-INDUCED BARRIER LOWERING/DIBL)
If Cox increases, you want to make sure you don’t control
immobile charges (parasitics) which do not contribute to
current.
M A ISLAM, EEE, IIUC
Switching Speed, Power Dissipation
Pdyn = ½ CoxZLVD2f
Pst = IoffVD
M A ISLAM, EEE, IIUC
CMOS
NOT gate
(inverter)
M A ISLAM, EEE, IIUC
CMOS
Vin = 1
Vout = 0
Positive gate turns nMOS on
M A ISLAM, EEE, IIUC
NOT gate
(inverter)
CMOS
Vin = 0
Vout = 1
Negative gate turns pMOS on
M A ISLAM, EEE, IIUC
NOT gate
(inverter)
So what?
• If we can create a NOT gate
we can create other gates
(e.g. NAND, EXOR)
M A ISLAM, EEE, IIUC
So what?
• More importantly, since one is open and one is shut at steady
state, no current except during turn-on/turn-off
 Low power dissipation
M A ISLAM, EEE, IIUC
BJT vs MOSFET
• RTL logic vs CMOS logic
• DC Input impedance of MOSFET (at gate end) is infinite
Thus, current output can drive many inputs  FANOUT
• CMOS static dissipation is low!!
~ IOFFVDD
• Normally BJTs have higher transconductance/current (faster!)
IC = (qni2Dn/WBND)exp(qVBE/kT)
gm = IC/VBE = IC/(kT/q)
ID = mCoxW(VG-VT) 2/L
gm = ID/VG = ID/[(VG-VT)/2]
• Today’s MOSFET ID >> IC due to near ballistic operation
M A ISLAM, EEE, IIUC
Mobility
• Drain current model assumed constant
mobility in channel
• Mobility of channel less than bulk – surface
scattering
• Mobility depends on gate voltage – carriers
in inversion channel are attracted to gate –
increased surface scattering – reduced
mobility
M A ISLAM, EEE, IIUC
Velocity Saturation
• In state-of-the-art MOSFETs, the channel is very short
(<0.1mm); hence the lateral electric field is very high and
carrier drift velocities can reach their saturation levels.
– The electric field magnitude at which the carrier velocity saturates is
Esat.
v
vsat
8 106 cm/s for electr ons in Si

6
6

10
cm/s for holes in Si

E
M A ISLAM, EEE, IIUC
Impact of Velocity Saturation
• Recall that I D  WQinv ( y)v( y)
• If VDS > Esat×L, the carrier velocity will saturate and hence
the drain current will saturate:
I D , sat  WQinvvsat  WCox VGS  VTH vsat
• ID,sat is proportional to VGS–VTH rather than
(VGS – VTH)2
• ID,sat is not dependent on L
• ID,sat is dependent on W
M A ISLAM, EEE, IIUC
Mobility dependence on gate voltage
m0
m
1  (VG  VT )
M A ISLAM, EEE, IIUC
MOSFET Small-Signal Model
(Saturation Region of Operation)
• The effect of channel-length modulation or DIBL (which
cause ID to increase linearly with VDS) is modeled by the
transistor output resistance, ro.
VDS
1
ro 

I D
lI D
M A ISLAM, EEE, IIUC
…… Thank You ……
M A ISLAM, EEE, IIUC