ECE 342
Electronic Circuits
2. MOS Transistors
Jose E. Schutt-Aine
Electrical & Computer Engineering
University of Illinois
jschutt@emlab.uiuc.edu
ECE 342 – Jose Schutt-Aine
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NMOS Transistor
Typically L = 0.1 to 3 mm, W = 0.2 to 100 mm, and the
thickness of the oxide layer (tox) is in the range of 2 to 50 nm.
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NMOS Transistor
• NMOS Transistor
–
–
–
–
N-Channel MOSFET
Built on p-type substrate
MOS devices are smaller than BJTs
MOS devices consume less power than BJTs
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NMOS Transistor - Layout
Top View
Cross Section
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MOS Regions of Operation
Resistive
VGS  VT
VDS small
Triode
Nonlinear
VGS  VT
VDS < (VGS  VT )
Saturation
Active
ECE 342 – Jose Schutt-Aine
VGS  VT
VDS  VGS  VT
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MOS Transistor Operation
•
As VG increases from zero
– Holes in the p substrate are repelled from the gate area
leaving negative ions behind
– A depletion region is created
– No current flows since no carriers are available
•
As VG increases
– The width of the depletion region and the potential at the
oxide-silicon interface also increase
– When the interface potential reaches a sufficiently
positive value, electrons flow in the “channel”. The
transistor is turned on
•
As VG rises further
– The charge in the depletion region remains relatively
constant
– The channel current continues to increase
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MOS – Triode Region - 1
W
I D  m Cox VGS  VT VDS 
L
VDS  VGS  VT 
Cox 
 ox
tox
3.9 o

tox
Cox: gate oxide capacitance
m: electron mobility
L: channel length
W: channel width
VT: threshold voltage
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MOS – Triode Region
FET is like a linear resistor with
rds 
1
W
mnCox VGS  VT 
L
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MOS – Triode Region - 2
VGS  VT
VDS  VGS  VT 
W
1 2 
I D  mnCox VGS  VT VDS  VDS 
L
2

– Charge distribution is nonuniform across channel
– Less charge induced in proximity of drain
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MOS – Active Region
VDS  VGS  VT   VDSP
Saturation occurs at pinch off when
VGS  VT
VDS  VGS  VT 
(saturation)
W
2
I D  mnCox
VGS  VT 
2L
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NMOS – Drain Current
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NMOS – Circuit Symbols
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NMOS – IV Characteristics
characteristics for a device with k’n (W/L) = 1.0 mA/V2.
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MOS Threshold Voltage
The value of VG for which the channel is “inverted” is
called the threshold voltage VT (or Vt ).
•
Characteristics of the threshold voltage
–
–
–
–
–
Depends on equilibrium potential
Controlled by inversion in channel
Adjusted by implantation of dopants into the channel
Can be positive or negative
Influenced by the body effect
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nMOS Device Types
• Enhancement Mode
– Normally off & requires positive potential on gate
– Good at passing low voltages
– Cannot pass full VDD (pinch off)
• Depletion Mode
– Normally on (negative threshold voltage)
– Channel is implanted with positive ions (VT )
– Provides inverter with full output swings
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Types of MOSFETS
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MOS – Active Region
•
Saturation
–
–
–
–
Channel is pinched off
Increase in VDS has little effect on iD
Square-law behavior wrt (VGS-VT)
Acts like a current source
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Diode-Connected Transistor
When the drain and gate of a MOSFET are connected
together the result is a two-terminal device known as
a diode-connected transistor
VGD  VT
for saturation region. Since VGD is zero, then the
device is always in the saturation region.
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Diode-Connected Transistor
1 'W
2
iD  i  kn VGS  Vt 
2 L
If we replace VGS
1 '
by V and use k  kn
2
W
ik
V  Vt

L
'
incremental
resistance
'

2
1
1
1
 i 
r 

 
W
' W
 V 
2k ' V  Vt  kn Vov
L
L
V  Vt  Vov
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Example
An MOS process technology has Lmin= 0.4
mm, tox= 8 nm, m = 450 cm2/V.s, VT = 0.7V
(a)Find Cox and kn’= mnCox
(b) W/L = 8 mm/0.8mm. Calculate VGS, VDSmin for
operation in saturation with ID= 100 mA
(c)Find VGS for the device in (b) to operate as
a 1 kW resistor for small vDS
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Example - Solution
Cox 
 ox
tox
3.45  1011
3
2
2


4.32

10
F
/
m

4.32
fF
/
m
m
8  109
Cox  4.32 fF / m m2
kn'  mnCox  450 cm2 / V .s  4.32 fF / mm2  194 m A / V 2
For operation in saturation region
1 'W
2
iD  kn VGS  VT 
2 L
1
8
2
100   194 
VGS  0.7   VGS  0.7  0.32 V  VGS  1.02 V
2
0.8
VDS min  VGS  VT  0.32 V
ECE 342 – Jose Schutt-Aine
VDS min  0.32 V
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Example – (con’t)
Triode region with vDS very small
vDS
rDS 
iD

small vDS
1
 'W

 kn L VGS  VT  
1
100 
194  106  10 VGS  0.7  
VGS  0.7  0.52 V
VGS  1.22 V
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Body Effect
• The body effect
– VT varies with bias between source and body
– Leads to modulation of VT
Potential on substrate affects threshold voltage
1/ 2

VT (VSB )  VTo    2 F  VSB    2 F

 kT   N 
F    ln  a 
 q   ni 
2qN a s 


Cox

1/ 2


Fermi potential of material
1/ 2
Body bias coefficient
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Channel-Length Modulation
With depletion layer widening, the channel length is in effect reduced from
L to L-DL  Channel-length modulation
This leads to the following I-V relationship
1 'W
2
iD  kn  vGS  VT  1  vDS 
2 L
Where  is a process technology parameter
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Channel-Length Modulation
Channel-length modulation causes iD to increase with vDS in
saturation region
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Problem
A MOSFET has VT = 1 V with measured data:
VGS(V)
2
2
VDS(V)
1
8
ID(mA)
80
91
Find 
(a) VGS  VT
VDS  VGS  VT  Pinchoff
(b) VGS  VT
VDS  VGS  VT  1V  Active region
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Problem (cont’)
Find iD at pinchoff VDSP = VGS-VT =1V
1 'W
2
I D  kn VGS  VT  1  VDS 
2 L
1 'W
2
I D1  kn VGS 1  VT  1  VDS 1 
2 L
I D2
1 'W
2
 kn VGS 2  VT  1  VDS 2 
2 L
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Problem (cont’)
1  VDS 1 91
R

 1.1375
1  VDS 2 80
1  VDS 2  R  RVDS1
 (VDS 2  RVDS1 )  R  1
R 1
1.1375  1


 0.0196 V 1
VDS 2  RVDS 1
8 1
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NMOS IV Curves
NMOS
700
VGS=1.0
VGS=1.5
VGS=2.0
VGS=2.5
600
500
IDS
400
300
200
100
0
0
0.5
1
1.5
2
2.5
Vds
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NMOS IV Curves
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MOSFET Circuit at DC – Problem 1
The MOSFET in the circuit shown has Vt = 1V,
kn’= 100mA/V2 and  = 0. Find the required
values of W/L and of R so that when
vI=VDD=+5 V, rDS=50 W and vo= 50 mV.
vI  VGS  5 V , vo  VDS  0.05 V
VDS
0.05
rDS  50 W 
 ID 
 0.001 A  1 mA
ID
50
VDD  vo 5  0.05
R

 4.95 k W
ID
1
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MOSFET Circuit at DC – Problem 1 (cont’)
VDS  VGS  Vt  triode region
2


V
W
'
DS
I D  kn VGS  Vt VDS 
L
2 
2


W
0.05
3
1  100 10
 5  1  0.05 

L
2 
W
 50
L
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MOSFET Circuit at DC – Problem 2
The NMOS transistors in the circuit shown
have Vt = 1V, mnCox = 120mA/V2,  = 0 and
L1=L2=1mm. Find the required values of
gate width for each of Q1 and Q2 and the
value of R, to obtain the voltage and
current values indicated.
VGS1  1.5V
1 'W
2
Using I D  kn VGS  Vt 
2 L
1 W
2
120 m A   1.5  1  W2  2 m m
2 1
5  3.5
R
 12.5 k W
0.120
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Gate Capacitance
VGT  0
VGT  0, VDS small
•
Capacitance
– Depends on bias
– Fringing fields are present
– Account for overlap C
VGT  0, VDS large
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Capacitance
• Gate Capacitance
– CG determines the amount of charge to switch gate
– Several distributed components
– Large discontinuity as device turns on
– At saturation capacitance is entirely between gate
and source
Define
VDS
X
VGS  VT
2

2
 1 X  
Cgs  Cgso  WLCox 1  
 
3
  2  X  
Cgd
  1 2 
2
 Cgdo  WLCox 1  
 
3
  2  X  
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MOS Capacitances
• Expect capacitance between every two of the
four terminals.
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MOS Parasitics
- Capacitance from gate to other 3 terminals
- Diodes to body
- Series resistance
- Wiring parasitics
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PMOS Transistor
PMOS
0
-100
VGS=-1.0
-200
-300
-400
-500
VGS=-1.0
VGS=-1.5
VGS=-2.0
VGS=-2.5
-600
-700
-2.5
-2
-1.5
-1
-0.5
0
Vds
- All polarities are reversed from nMOS
- vGS, vDS and Vt are negative
- Current iD enters source and leaves through drain
- Hole mobility is lower  low transconductance
- nMOS favored over pMOS
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PMOS Circuit
The PMOS transistor in the circuit shown has
Vt = -0.7 V, mpCox = 60mA/V2,  = 0 and
L=0.8mm. Find the values required for W
and R, in order to establish a drain current
of 115 mA and a voltage VD of 3.5 V.
3.5
R
 3.04 k W
0.115
1
W
2
3
0.115 mA   60  10 
 1.5  (0.7) 
2
0.8
W  4.8 m m
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