Chapter 5 – Field-Effect Transistors (FETs)
Physical structure of the enhancement-type NMOS transistor: (a) perspective view; (b) cross
section. Typically L = 1 to 10 m, W = 2 to 500 m, and the thickness of the oxide layer is in the
range of 0.02 to 0.1 m.
Field-Effect Transistors (FETs)
Field-Effect Transistors (FETs)
FET basic operational theory FET basic operational theory
•The current controlled mechanism (drain current) is based on
electric field established by the voltage applied to the control
terminal (gate).
•Current is only conducted by only one type of carrier “ electrons or
holes” (that is why sometimes FET is called unipolar transistors.
Another type is the insulated gate FET or IGFET.
•Why MOS (Metal-Oxide) Transistors?
•Very small (smaller silicone area on the IC)
•Simple to manufacture
•No need for biasing resistors.
•Used in VLSI (very-large-scale integration)
•The enhancement type MOSFET is the most significant
semiconductor devise available today.
Field-Effect Transistor (FET)
Metal-oxide semiconductor field-effect transistor (MOSFET) has been extremely
popular since the late 1970s.
Compared to BJTs, MOS transistors:
•Can be made smaller /higher integration scale
•Easier to fabricate /lower manufacturing cost
•Simpler circuitry for digital logic and memory
•Inferior analog circuit performance (lower gain)
Most digital ICs use MOS technology
Recent trend: more and more analog circuits are implemented in MOS technology for
lower cost integration with digital circuits in a same chip
Field-Effect Transistors (FETs)
Device Structure
•Four Terminals: Gate, Drain, Source, Body
•Unlike the BJT, the MOSFET is normally constructed as a symmetrical device.
•The name of Metal-Oxide-Semiconductor is apparent from the structure.
•Typically, L = 0.15 to 10 µm, W = 0.3 to 500µm, the thickness of the oxide layer is in the
range of 0.02 to 0.1 µ m.
•The minimum value of L achievable in a particular MOS technology is often referred as
the feature size of the technology.
•State-of-the-art: Intel Pentium 4uses 0.13 µm technology
•Modern technology uses poly-silicon which has high conductivity, instead of metal to
form the gate.
Physical Operation
of Enhancement MOSFET
Operation with No Gate Voltage
With no bias applied to the gate, two back-to-back diodes exist in series between drain
and source. The two back-to-back diodes prevent current conduction from drain to source
when a voltage vDS is applied. The resistance is of the order of 10^12 ohms
Creating a Channel for Current Flow
If S and D are grounded and a positive voltage is applied to G, the holes are repelled
from the channel region downwards, leaving behind a carrier-depletion region.
Further increasing VG attracts minority carrier ( electrons) from the substrate into the
channel region. When sufficient amount of electrons accumulate near the surface of the
substrate under the gate, an n region is created-called as the inversion layer.
Physical Operation of Enhancement MOSFET
Applying a Small vDS
When a small potential is
applied across the Gate and
source, it pushes away the
holes towards the substrate
and attract electrons from the
Drain and Source into the
channel region. When
sufficient electrons are
formulated beneath the Gate
area, current flows between
the Drain and the Source.
(Basically the holes are
pushed away in N channel –
NMOS type to be replaced by
the electrons from both the
Source and the Drain creating
a channel of N majority
causing current to flow from
Physical Operation of
Enhancement MOSFET
Applying a Small vDS
Applying a small vDS (~ 0.1 or 0.2 V) causes a
current iD to flow through the induced nchannel
from D to S.
The magnitude of iD depends on the density of
electrons in the channel, which in turn depends on
vGS.
For vGS = Vt (threshold voltage), the channel is
just induced and the conducted current is still
negligibly small.
As vGS > Vt, depth of the channel increases, iD
will be proportional to (vGS – Vt), known as excess
gate voltage or effective voltage.
Increasing vGS above Vt enhances the channel,
hence it is called enhancement type MOSFET.
Note that iG=0.
Physical Operation of
Enhancement MOSFET
Operation as vDS is Increased
v DSsat v GS  V t
vDS appears as a voltage drop across
the channel.
Voltage across the oxide decreases
from vGS at S to vGS-Vt at D.
The channel depth will be tapered, and
become more tapered as vDS is
increased.
Eventually, when vGS-vDS = Vt, the
channel will be pinched off.
Increasing vDS beyond this value has
no effect on the channel shape and iD
saturates (remains constant) at this
value. The MOSFET enters the
saturation region of operation.
vDSsat = Vgs- Vt
v DSsat v GS  V t
Physical Operation of
Enhancement MOSFET
v DSsat
v GS  V t
v DSsat
v GS  V t
The drain current iD versus the drain-to-source voltage vDS for an enhancement-type
NMOS transistor operated with vGS > Vt.
Field-Effect Transistors (FETs) - Enhancement Type
The enhancement-type NMOS transistor with a positive voltage applied to the gate. An n channel is
induced at the top of the substrate beneath the gate.
Field-Effect Transistors (FETs) - Enhancement Type
An NMOS transistor with vGS > Vt and with a small vDS applied. The device acts as a
conductance whose value is determined by vGS. Specifically, the channel conductance
is proportional to vGS - Vt, and this iD is proportional to (vGS - Vt) vDS. Note that the
depletion region is not shown (for simplicity).
Field-Effect Transistors (FETs) - Enhancement Type
Exercise 5.1
Field-Effect Transistors (FETs) - Enhancement Type
Exercise 5.1
v DS  0.2
K 
iD  0.0004
iD
vGS  Vt vDS
v DS
rDS 
iD
Vt  1
4
K  5  10
rDS  500
v GS  Vt  4
A
2
V
Field-Effect Transistors (FETs) - Enhancement Type
Derivation of ID- vDS Relationship
Derivation of ID- vDS Relationship
Field-Effect Transistors (FETs) - Enhancement Type
Saturation Region
Triode Region
Derivation of the iD - vDS characteristic of the NMOS transistor.
Field-Effect Transistors (FETs) - Enhancement Type
Field-Effect Transistors (FETs)
Enhancement Type
Field-Effect Transistors (FETs)
Enhancement Type
Cross section of a CMOS integrated circuit. Note that the PMOS transistor is
formed in a separate n-type region, known as an n well. Another arrangement is
also possible in which an n-type body is used and the n device is formed in a p
well.
Field-Effect Transistors (FETs)
Enhancement Type
(a) An n-channel enhancement-type MOSFET with vGS and vDS applied and with
the normal directions of current flow indicated. (b) The iD - vDS characteristics for
a device with Vt = 1 V and k’n(W/L) = 0.5 mA/V2.
Field-Effect Transistors (FETs)
Enhancement Type
The iD - vGS characteristic for an enhancement-type NMOS transistor in saturation
(Vt = 1 V and k’n(W/L) = 0.5 mA/V2).
Field-Effect Transistors (FETs)
Enhancement Type
Increasing vDS beyond vDSsat causes the channel pinch-off point to move slightly
away from the drain, thus reducing the effective channel length (by L).
Field-Effect Transistors (FETs)
Enhancement Type
iD
1
2
k' n

L
W
v GS  V t
 1  v DS
2
Effect of vDS on iD in the saturation region. The MOSFET parameter VA is
typically in the range of 30 to 200 V.
Field-Effect Transistors (FETs)
Enhancement Type
Field-Effect Transistors (FETs)
Enhancement Type
Field-Effect Transistors (FETs)
Enhancement Type
Large-signal equivalent circuit model of the n-channel MOSFET in saturation,
incorporating the output resistance ro. The output resistance models the linear
dependence of iD on vDS and is given by ro  VA/ID.
Field-Effect Transistors (FETs)
Enhancement Type
Field-Effect Transistors (FETs)
Enhancement Type
Field-Effect Transistors (FETs)
Enhancement Type – Practical Considerations
Exercise 5-4
Refer to exercise 5-3
a)
kn  20
iD  kn 
W  100
W
L
L  10
 ( vGS  Vt)  vDS 

1
2
vGS  3
 vDS 
2

iD  75
b)
nCox  20
iD 
1
2
 nCox
W
 nCox
W
L
 ( vGS  Vt )
2
 ( vGS  Vt )
2
iD  100
c)
iD 
1
2
L
iD  100
Vt  2
vDS  0.5
Exercise 5-5
vDS  3
For
iD 
1
2
 nCox
W
L
nCox
W
For
vGS  4
iD 
1
iD 
1
2
2
L
vGS  vDS
 ( vGS  Vt )
iD  1
2
2 1
 nCox
vDS  5
W
L
 ( vGS  Vt )
 2 ( vGS  Vt )
2
2
iD  4
For small vDS
iD  kn 
rDS 
rDS 
W
L
 [ ( vGS  Vt )  vDS]
vDS
iD
1
[ 2 ( ( vGS  Vt ) ) ]
rDS  0.25
K
Vt  2
Field-Effect Transistors (FETs)
Depletion Type
The depletion type MOSFET has similar structure to that the
enhancement type MOSFET but with one important difference:
The depletion MOSFET has a physically implanted channel. Thus an nchannel depletion-type MOSFET has an n-type silicone region
connecting the source and drain (both +n) at the top of the type
substrate. Thus if a voltage vDS is applied between the drain and
source, a current iD flows for vGS = 0 i.e there is no need to induce the
channel.
The channel depth and hence its conductivity is controlled by vGS.
Applying a positive vGS enhances the channel by attracting more
electrons. The reverse when applying negative volt. The negative
voltage is said to deplete the channel (depletion mode).
Field-Effect Transistors (FETs)
Depletion Type
The current-voltage characteristics of a depletion-type n-channel MOSFET for
which Vt = -4 V and k’n(W/L) = 2 mA/V2: (a) transistor with current and voltage
polarities indicated; (b) the iD - vDS characteristics; (c) the iD - vGS characteristic in
Field-Effect Transistors (FETs)
Depletion Type
vGS is positive the transistor will be operated in the enhancement mode
enhancement mode
vGS is negative the transistor will be operated in the depletion mode.
depletion mode.
The current-voltage
characteristics of a
depletion-type nchannel MOSFET
for which Vt = -4 V
and k’n(W/L) = 2
mA/V2
Field-Effect Transistors (FETs)
Depletion Type
Field-Effect Transistors (FETs)
Depletion Type
MOSFET Circuits at DC
MOSFET Circuits at DC
MOSFET Circuits at DC
MOSFET Circuits at DC
MOSFET As An Amplifier
MOSFET As An Amplifier
MOSFET As An Amplifier
MOSFET As An Amplifier
MOSFET As An Amplifier – Small-Signal Analysis
MOSFET As An Amplifier – Small-Signal Analysis
MOSFET As An Amplifier – The T Equivalent Circuit Models
MOSFET As An Amplifier – Modeling the Body Effect
MOSFET As An Amplifier – Exercise 5.17
MOSFET As An Amplifier – Exercise 5.18
MOSFET As An Amplifier – Exercise 5.19-20
Biasing a MOS Amplifier In Discrete Circuits
Biasing a MOS Amplifier In Integrated Circuits
Biasing a MOS Amplifier In Integrated Circuits
Biasing a MOS Amplifier In Integrated Circuits
Biasing a MOS Amplifier In Integrated Circuits
Basic Configurations of Single-Stage IC MOS Amplifiers
Basic Configurations of Single-Stage IC MOS Amplifiers
Basic Configurations of Single-Stage IC MOS Amplifiers
Basic Configurations of Single-Stage IC MOS Amplifiers
Basic Configurations of Single-Stage IC MOS Amplifiers
Basic Configurations of Single-Stage IC MOS Amplifiers
Exercises 5.22, 5.23, 5.25, 5.26, 5.27, 5.28.
The CMOS Digital Inverter
The CMOS Digital Inverter
The CMOS Digital Inverter
The CMOS Digital Inverter
The CMOS Digital Inverter
MOSFET As An Analog Switch
The MOSFET Internal Capacitances and High-Frequency Model
The Junction Field-Effect Transistor (JFET)
Gallium Arsenide (GaAs) Devices - MESFET
The Spice Model and Simulation Examples
Exercise - 5.22
W
kn 
L
Vt  2
0.5
RG  1000000
ID  0.001
VGS  10
given
1
1



2
 0.5 VGS  2
2
Find VGS  4
VG  0
RS 
VS  4
4  ( 10)
VDmin
3
RS  6  10
ID
VG  Vt
2
Neglecting the signal component of VG
To allow for a plus/minus 2 V signal swing at the drain
VD  0
Thus
RD 
10  0
ID
4
RD  1  10
Fig. 5.31 Conceptual circuit utilized to study the operation of the MOSFET as an amplifier.
Small-signal operation of the enhancement MOSFET amplifier.
Fig. 5.33 Total instantaneous voltages vGS and vD for the circuit in Fig. 5.31.
Fig. 5.34 Small-signal models for the MOSFET: (a) neglecting the dependence of iD on vDS in saturation (channel-length modulation
effect); and (b) including the effect of channel-length modulation modeled by output resistance ro = |VA|/ID.
g mb

Fig. 5.37 the T model of the MOSFET augmented with the drain-to-source resistance ro.
  gm

2 2 f  VSB
Fig. 5.41 Basic MOSFET current mirror.
Ro
V O
I O
r o2
V A2
IO
Fig. 5.42 Output characteristic of the current source in Fig. 5.40 and the current mirror of Fig. 5.41 for the case Q2 is matched to Q1.
Fig. 5.45 The CMOS common-source amplifier: (a) circuit; (b) i-v characteristic of the active-load Q2; (c) graphical construction to
determine the transfer characteristic; and transfer characteristic.
Fig. 5.47 The CMOS common-gate amplifier: (a) circuit; (b) small-signal equivalent circuit; and (c) simplified version of the circuit
in (b).
Fig. 5.48 The source follower: (a) circuit; (b) small-signal equivalent circuit; and (c) simplified version of the equivalent circuit.
Fig. 5.52 (a) NMOS amplifier with enhancement load; (b) graphical determination of the transfer characteristic; (c) transfer
characteristic.
Fig. 5.53 The NMOS amplifier with depletion load: (a) circuit; (b) graphical construction to determine the transfer characteristic; and
(c) transfer characteristic.
Fig. 5.54 Small-signal equivalent circuit of the depletion-load amplifier of Fig. 5.43 (a), incorporating the body effect of Q2.
Fig. 5.55 (a) The CMOS inverter. (b) Simplified circuit schematic for the inverter.
Fig. 5.56 Operation of the CMOS inverter when v1 is high: (a) circuit with v1 = VDD (logic-1 level, or VOH); (b) graphical construction
to determine the operating point; and (c) equivalent circuit.
Fig. 5.57 Operation of the CMOS inverter when v1 is low: (a) circuit with v1 = 0V (logic-0 level, or VOL); (b) graphical construction to
determine the operating point; and (c) equivalent circuit.
Fig. 5.58 The voltage transfer characteristic of the CMOS inverter.
Fig. 5.59 Dynamic operation of a capacitively loaded CMOS inverter: (a) circuit; (b) input and output waveforms; (c) trajectory of the
operating point as the input goes high and C discharges through the QN; (d) equivalent circuit during the capacitor discharge.
Fig. 5.64 The CMOS transmission gate.
Fig. 5.65 Equivalent circuits for visualizing the operation of the transmission gate in the closed (on) position: (a) vA is positive; (b) vA
is negative.
Fig. 5.67 (a) High-frequency equivalent circuit model for the MOSFET; (b) the equivalent circuit for the case the source is connected
to the substrate (body); (c) the equivalent circuit model of (b) with Cdb neglected (to simplify analysis).
Fig. 5.68 Determining the short-circuit current gain Io/Ii.