High Speed Analog to Digital
Converter
Presentation by :
Abdelrahman Radwan
George Ekladious
Introduction
• An electronic integrated circuit which
transforms a signal from analog (continuous) to
digital (discrete) form.
• Analog signals are directly measurable
quantities.
• Digital signals only have two states. For digital
computer, we refer to binary states, 0 and 1.
Why ADC ?
• storing analog data
• replicating or reconstructing analog data
• Microprocessors can only perform complex
processing on digitized signals.
• When signals are in digital form they are less
susceptible to the deleterious effects of additive
noise.
ADC Applications
• Measurements / Data Acquisition
• Control Systems
• PLCs (Programmable Logic Controllers)
• Sensor integration (Robotics)
• Cell Phones
• Video Devices
Audio Devices•
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Controller
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Principal of Operation
ADC Process
• Sampling and Holding (S/H)
• Quantizing and Encoding (Q/E)
Holding and Sampling
• Holding signal benefits the
accuracy of the A/D conversion.
• Minimum sampling rate
should be at least twice
the highest data frequency
of the analog signal.
• Quantizing - breaking down analog value is a set
of finite states.
• Encoding - assigning a digital word or number to
each state and matching it to the input signal
• Resolution: The smallest change in analog signal
that will result in a change in the digital output.
• V = Reference voltage range N = Number of bits in digital output. 2N =
Number of states. ∆V = Resolution
• The resolution represents the quantization error
inherent in the conversion of the signal to digital
form
Quantizing
The number of possible states that the
converter can output is:
N=2n
where n is the number of bits in the AD converter
Example: For a 3 bit A/D converter, N=23=8.
Analog quantization size:
Q=(Vmax-Vmin)/N = (10V – 0V)/8 = 1.25V
Quantization
We have 0-10V signals. Separate
them into a set of discrete states
with 1.25V increments.
Encoding
• Here we assign the digital value
(binary number) to each state
for the computer to read.
Accuracy of A/D Conversion
There are two ways to best improve the accuracy
of A/D conversion:
• increasing the resolution which improves the
accuracy in measuring the amplitude of the
analog signal.
• increasing the sampling rate which increases
the maximum frequency that can be measured.
Sampling Rate
Frequency at which ADC evaluates analog signal. As we see in the
second picture, evaluating the signal more often more accurately
depicts the ADC signal.
Aliasing
• Occurs when the input signal is changing much
faster than the sample rate.
For example, a 2 kHz sine wave being sampled at
1.5 kHz would be reconstructed as a 500 Hz (the
aliased signal) sine wave.
Nyquist Rule:
• Use a sampling frequency at least twice as high
as the maximum frequency in the signal to avoid
aliasing.
A/D converter Types
▫ Flash ADC
▫ Delta-Sigma ADC
▫ Dual Slope (integrating) ADC
▫ Successive Approximation ADC
Flash ADC
• Uses the 2N resistors to form a ladder voltage
divider, which divides the reference voltage into
2N equal intervals.
• Consists of a series of comparators, each one
comparing the input signal to a unique reference
voltage.
• The comparator outputs connect to the inputs of
a priority encoder circuit, which produces a
binary output
Flash ADC Circuit
Comparator
VIN
+
VREF
-
VOUT
If
Output
VIN > VREF High
VIN < VREF Low
Flash ADC operation
• As the analog input voltage exceeds the
reference voltage at each comparator, the
comparator outputs will sequentially saturate to
a high state.
• The priority encoder generates a binary number
based on the highest-order active input, ignoring
all other active inputs.
Example
• Design a Flash ADC with the following
parameters:
 number of output bits = 2;
 input voltage range = 0 to 3V;
 comparator outputs have positive saturation = +12V
and negative saturation = 0V;
Solution
Resolution = input voltage range / 2n
= 3 / 22
= 0.75V
Number of Comparators :
2n = 22 = 4
Thus we need 4 comparators and 4 equal
resistors.
Solution continued
Vref= 3V
Solution continued
Analogue input
VIN
Comparator outputs /V Binary number at output
W
X
Y
B
A
VIN < 0.75V
0
0
0
0
0
0.75V < VIN < 1.50V
12
0
0
0
1
1.50V < VIN < 2.25V
12
12
0
1
0
2.25V < VIN < 3.00V
12
12
12
1
1
VIN > 3.00V
Z =+12V indicating overflow
Flash ADC Advantages and Disadvantages
Advantages:
• Very Fast .
• Very simple operational theory .
• Speed is only limited by gate and comparator
propagation delay .
Disadvantages:
• Expensive.
• Each additional bit of resolution requires twice the
comparators.
• Prone to produce glitches in the output
Successive Approximation ADC
Operation Principle
• A Successive Approximation Register (SAR) is
added to the circuit
• Instead of counting up in binary sequence, this
register counts by trying all values of bits
starting with the MSB and finishing at the LSB.
• The register monitors the comparators output to
see if the binary count is greater or less than the
analog signal input and adjusts the bits
accordingly
Advantages and Disadvantages SA ADC
Advantages :
• Capable of high speed and reliable .
• Medium accuracy compared to other ADC types.
• Good tradeoff between speed and cost.
Disadvantages :
• Higher resolution successive approximation
ADC’s will be slower
Successive Approximation ADC
Example
Goal: Find digital value Vin
• 8-bit ADC
• Vin = 7.65
• Vfull scale = 10
Successive Approximation ADC
Example
• MSB  LSB
• Average high/low limits
• Compare to Vin
• Vin > Average  MSB = 1
• Vin < Average  MSB = 0
• Bit 7
• (Vfull scale +0)/2 = 5
• 7.65 > 5  Bit 7 = 1
1
Vfull scale = 10, Vin = 7.65
Successive Approximation ADC
Example
• MSB  LSB
• Average high/low limits
• Compare to Vin
• Vin > Average  MSB = 1
• Vin < Average  MSB = 0
• Bit 6
• (Vfull scale +5)/2 = 7.5
• 7.65 > 7.5  Bit 6 = 1
1
1
Vfull scale = 10, Vin = 7.65
Successive Approximation ADC
Example
• MSB  LSB
• Average high/low limits
• Compare to Vin
• Vin > Average  MSB = 1
• Vin < Average  MSB = 0
• Bit 5
• (Vfull scale +7.5)/2 = 8.75
• 7.65 < 8.75  Bit 5 = 0
1
1
0
Vfull scale = 10, Vin = 7.65
Successive Approximation ADC
Example
Vin = 7.65
• MSB  LSB
• Average high/low limits
• Compare to Vin
• Vin > Average  MSB = 1
• Vin < Average  MSB = 0
• Bit 4
• (8.75+7.5)/2 = 8.125
• 7.65 < 8.125  Bit 4 = 0
1
1
0
0
Successive Approximation ADC
Example
Vin = 7.65
• MSB  LSB
• Average high/low limits
• Compare to Vin
• Vin > Average  MSB = 1
• Vin < Average  MSB = 0
• Bit 3
• (8.125+7.5)/2 = 7.8125
• 7.65 < 7.8125  Bit 3 = 0
1
1
0
0
0
Successive Approximation ADC
Example
Vin = 7.65
• MSB  LSB
• Average high/low limits
• Compare to Vin
• Vin > Average  MSB = 1
• Vin < Average  MSB = 0
• Bit 2
• (7.8125+7.5)/2 = 7.65625
• 7.65 < 7.65625  Bit 2 = 0
1
1
0
0
0
0
Successive Approximation ADC
Example
Vin = 7.65
• MSB  LSB
• Average high/low limits
• Compare to Vin
• Vin > Average  MSB = 1
• Vin < Average  MSB = 0
• Bit 1
• (7.65625+7.5)/2 = 7.578125
• 7.65 > 7.578125  Bit 1 = 1
1
1
0
0
0
0
1
Successive Approximation ADC
Example
Vin = 7.65
• MSB  LSB
• Average high/low limits
• Compare to Vin
• Vin > Average  MSB = 1
• Vin < Average  MSB = 0
• Bit 0
• (7.65625+7.578125)/2 =
7.6171875
• 7.65 > 7.6171875  Bit 0 = 1
1
1
0
0
0
0
1
1
Wilkinson ADC
• Speed: High
• Cost: High
• Accuracy: High
Wilkinson Analog
Digital Converter
(ADC) circuit
schematic diagram
ADC Types Comparaison
Why High speed ADCs ?
Better Resolution Bandwidth
Low Power
Better Resolution Bandwidth
The average speed of high-speed A/D converters
has increased by a factor of ten over the past five
years.
Low Power
The usage of portable devices such as laptops and
Bluetooth devices its demanded to use a very low
power ADC .
Current Research
• 14 GSps, four-bit data converter pair in 90 nm
CMOS [7] .
• The experimental results show that the
The ADC consume 214 mW and from a 1.0-V
supply and occupy 0.1575 mm2 .
Ultralow-Voltage High-Speed ADC
• In the proposed design strategy [6], a 7-bit flash
ADC is designed and fabricated in 90-nm CMOS to
operate with a 0.5 V supply voltage.
• Using two-way interleaving, the prototype achieves
a maximum conversion rate of 420 MS/s with an
ERBW of 50 MHz.
• The total power consumption of the interleaved ADC
is 4.1 mW.
• Using the proposed FD-oriented design, this paper
achieves at least 3.5 times speed enhancement
compared with other state-of-the-art ULV ADC
High Speed ADCs Comparison
References
1.
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3.
4.
5.
6.
7.
http://ume.gatech.edu/mechatronics_course/ADC_F05.ppt
http://ume.gatech.edu/mechatronics_course/ADC_F10.pptx
http://www.me.berkeley.edu/ME102B/Past_Proj/f03/Proj6/T
MS320LF2407A_Documents/Intro-ADC.pdf
http://www.allaboutcircuits.com/vol_4/chpt_13/6.html
http://www.allaboutcircuits.com/vol_4/chpt_13/4.html
Lin, J.; Mano, I.; Miyahara, M.; Matsuzawa, A., "UltralowVoltage High-Speed Flash ADC Design Strategy Based on FoMDelay Product," Very Large Scale Integration (VLSI) Systems,
IEEE Transactions on, vol.PP, no.99, pp.1,1
Hao-Chiao Hong; Yung-Shun Chen; Wei-Chieh Fang, "14 GSps
Four-Bit Noninterleaved Data Converter Pair in 90 nm CMOS
With Built-In Eye Diagram Testability," Very Large Scale
Integration (VLSI) Systems, IEEE Transactions on , vol.22,
no.6, pp.1238,1247, June 2014