Designing_with_Cyclone_and_Cyclone_II_Device
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Designing with Cyclone & Cyclone II Devices Copyright © 2005 Altera Corporation Objectives Generate & Optimize a Cyclone & Cyclone II Design Use Quartus II Software to Enable & Disable Cyclone & Cyclone II Features Design a Multi-Clock System Using PLLs & Clock Resources Describe features in Cyclone & Cyclone II for implementing a DDR Memory Interface Choose a Configuration Strategy Configure a Cyclone Device Copyright © 2005 Altera Corporation 2 Agenda Introduction to Altera, Cyclone™, & Cyclone II Architecture Logic Structure Clocking Infrastructure & PLLs Memory Embedded Multipliers I/O Architecture Double-Data Rate (DDR) Low-Voltage Differential Signaling (LVDS) Configuration Copyright © 2005 Altera Corporation 3 The Programmable Solutions Company® Devices Stratix® II™ Cyclone II Stratix GX Stratix Cyclone Intellectual Property (IP) Signal Processing Communications Embedded Processors Nios®, Nios II Copyright © 2005 Altera Corporation 4 Devices (continued) MAX® II Mercury™ Devices ACEX® Devices FLEX® Devices MAX Devices Tools Quartus® II Software SOPC Builder DSP Builder Nios II IDE Programmable Logic Families Structured ASIC Stratix HardCopy, HardCopy Stratix High & Medium Density FPGAs Stratix II, Stratix, APEX™II, APEX 20K, & FLEX 10K Low-Cost FPGAs Cyclone II, Cyclone FPGAs with Clock Data Recovery Stratix GX & Mercury CPLDs MAX II, MAX 7000 & MAX 3000 Embedded Processor Solutions Nios™ II, Excalibur™ Configuration Devices Serial (EPCS) & Enhanced (EPC) Copyright © 2005 Altera Corporation 5 Software & Development Tools Quartus II All Stratix, Cyclone & Hardcopy Devices APEX II, APEX 20K/E/C, Excalibur, & Mercury Devices FLEX 10K/A/E, ACEX 1K, FLEX 6000 Devices MAX II, MAX 7000S/AE/B, MAX 3000A Devices Quartus II Web Edition Free Version Not All Features & Devices Included See www.altera.com for Feature Comparison MAX+PLUS® II All FLEX, ACEX, & MAX Devices Copyright © 2005 Altera Corporation 6 Altera’s Low-Cost Roadmap 2000 1997 2002 2004 Low Cost by Design New Era of Designing for Low Cost Copyright © 2005 Altera Corporation 7 Designing for Low Cost 1 Customer Requirements 2 Optimize I/O Pins for Each Package 3 Populate Core with LEs & Dedicated Functions 4 Optimize Layout Memory Logic PLLs Copyright © 2005 Altera Corporation 8 I/O Cyclone Device Family Altera’s First-Generation LowCost FPGA Family Designed Based on Customer Requirements Industry’s Lowest-Cost FPGA Family Shipping Today Higher Performance Than Other Low-Cost FPGAs Millions of Units Shipped Fastest Product Ramp in 20-Year Altera History Eliminates Low-End ASIC Decision Copyright © 2005 Altera Corporation 9 Shipping Today in Production Volumes! Introducing Cyclone II FPGAs The Lowest-Cost FPGAs Ever 30% Lower Cost than Cyclone Over 3X the Density than Cyclone Optimized for Cost from the Start Lowest Price per Logic Density I/O-Rich Offerings Enhanced Feature Set Dedicated DSP Functionality Dedicated External Memory Interface Circuitry Proven 90-nm Process Technology Second Altera Product on TSMC’s 90-nm Process Copyright © 2005 Altera Corporation 10 Cyclone Family Overview Device Logic Elements PLL Memory Bits Maximum User I/O Pins LVDS Compatible Channels EP1C3 2,910 1 59 K 104 34 EP1C4 4,000 2 76 K 301 129 EP1C6 5,980 2 90 K 185 72 EP1C12 12,060 2 234 K 249 103 EP1C20 20,060 2 288 K 301 129 Copyright © 2005 Altera Corporation 11 Cyclone Packaging & User I/O Device EP1C3 100-Pin TQFP 144-Pin TQFP 240-Pin PQFP 256-Pin FBGA 324-Pin FBGA 400-Pin FBGA 0.5 mm 16 x 16 0.5 mm 22 x 22 0.5 mm 32 x 32 1.0 mm 17 x 17 1.0 mm 19 x 19 1.0 mm 21 x 21 65 104 249 301 EP1C4 EP1C6 EP1C12 EP1C20 98 185 185 173 185 249 233 301 Denotes Vertical Migration Copyright © 2005 Altera Corporation 12 Cyclone II Family Overview Logic Elements PLLs M4K Memory Blocks Total Memory Bits 18x18 Embedded Multipliers Maximum User I/O Pins EP2C5 4,608 2 26 119,808 13 142 EP2C8 8,256 2 36 165,888 18 182 EP2C20 18,752 4 52 239,616 26 315 EP2C35 33,216 4 105 483,840 35 475 EP2C50 50,528 4 129 594,432 86 450 EP2C70 68,416 4 250 1,152,000 150 622 Device Copyright © 2005 Altera Corporation 13 Cyclone II Packaging & User I/O Copyright © 2005 Altera Corporation 14 Over 40 Optimized IP Cores Nios II Soft-Core Processor Plus a Large Suite of Peripherals in SOPC Builder Digital Signal Processing FFT & FIR Compiler I/O Interfaces 10/100/1000 Ethernet MAC PCI & PCI-X PL2 & PL3 Utopia Memory Controllers DDR2 & QDRII Copyright © 2005 Altera Corporation 15 Ordering Codes EP2C35F484C7 EP2C 35 F 484 C 7 Device Family (EP1C = Cyclone; EP2C = Cyclone II) Approximately # of Logic Elements (LE)s x 1000 Package Type: F = Fineline BGA, P = PQFP Total Package Pins Operating Temperature: Commercial, Industrial Speed Grade: 6 (Fastest), 7, or 8 Copyright © 2005 Altera Corporation 16 Cyclone/Cyclone II Architecture Logic Elements General Purpose Logic Functions PLLs & Clock Generation On- & Off-Chip Timing Management Embedded Memory General Purpose Internal Storage Embedded Multipliers (Cyclone II) DSP Functions Input/Output (I/O) Double-Data Rate (DDR) & High-Speed Differential Support Configuration Copyright © 2005 Altera Corporation 17 EP1C3 Device Floorplan EP1C3 Logic Array M4K RAM Block PLL IOEs Copyright © 2005 Altera Corporation 18 EP1C20 Device Floorplan EP1C20 Top IOEs: LVDS & DDR Logic Array M4K RAM Block Phase-Locked Loops (PLLs) Side IOEs: LVDS, DDR & PCI Side I/O Elements (IOEs): LVDS, DDR & PCI Bottom IOEs: LVDS & DDR Copyright © 2005 Altera Corporation 19 EP2C35 Cyclone II Floorplan PLLs Logic Elements Embedded Multipliers M4K Blocks Row I/O Copyright © 2005 Altera Corporation 20 Column I/O Architecture Comparison Device Family Cyclone Cyclone II Cyclone II Advantages Core Voltage 1.5 V 1.2 V Lower Power Process 130 nm 90 nm Lower Cost Logic Density (LEs) 2,910 to 20,060 4,608 to 68,416 3X I/O Pin Count 65 to 301 85 to 622 2X Embedded Memory (M4K Blocks - 4Kbit) 13 to 64 26 to 250 4X Memory Density (Bits) 60K to 295K 120K to 1,152K 4X Relative Performance 1.0 1.0 Same Parameter Relative Standby Relative Power Active Power Copyright © 2005 Altera Corporation 21 Parity 1.0 1.0 Lower Lower Power Feature Comparison Device Family Parameter Cyclone Cyclone II DSP Implementation Built with Logic Elements Up to 150 18x18 Embedded Multipliers PLLs per Device 1 to 2 2 to 4 I/O Standards Single Ended + Differential I/O Same as Cyclone + 4 New Standards External Memory Device Interfaces SDR, DDR SDRAM SDR, DDR, DDR2 SDRAM & QDR II SRAM Bottom Line: Embedded Multipliers Capable of Running at 250 MHz 2x the PLLs for a Complete System Clock Management Solution 4 New I/O Standards (mini-LVDS, LVPECL, HSTL, PCI-X) 2 New External Memory Device Interfaces (DDR2, QDRII) Copyright © 2005 Altera Corporation 22 Designing with Cyclone & Cyclone II Devices Architecture – Logic Structure Copyright © 2005 Altera Corporation Architecture – Logic Structure Cyclone Logic Array Blocks (LABs) & LEs Cyclone II LABs & LEs Interconnects (Routing) Copyright © 2005 Altera Corporation 24 Cyclone/Cyclone II Logic Elements Smallest Units of Logic Used for Combinatorial/Registered Logic Arranged in Groups Called LABs Copyright © 2005 Altera Corporation 25 LAB Resources LAB Rows LAB Columns EP1C3 EP1C4 EP1C6 13 24 26 17 20 32 EP1C12 EP1C20 26 48 32 64 Device Copyright © 2005 Altera Corporation 26 LAB Rows LAB Columns EP2C5 EP2C8 EP2C20 24 13 30 18 46 26 EP2C35 EP2C50 EP2C70 60 35 74 43 86 50 Device Total LE Resources Cyclone Device EP1C3 EP1C4 EP1C6 EP1C12 EP1C20 Total LEs 2,910 4,000 5,980 12,060 20,060 Copyright © 2005 Altera Corporation 27 Cyclone II Device EP2C5 EP2C8 EP2C20 EP2C35 EP2C50 EP2C75 Total LEs 4,608 8,256 18,752 33,216 50,528 68,416 Cyclone LABs Control Signals 4 10 LEs Local interconnect LAB-Wide Control Signals 30 LAB input Lines Local interconnect 4 4 4 4 4 4 4 4 4 Copyright © 2005 Altera Corporation 28 10 LE Feedback Lines LE1 LE2 LE3 LE4 LE5 LE6 LE7 LE8 LE9 LE10 Carry & Register Chain LAB Arrangement LABs Communicate Directly to Each Other & Other Blocks Both Horizontally & Vertically LAB LAB LAB LAB LAB LAB M512 LAB LAB LAB LAB LAB LAB LAB LAB M512 LAB LAB LAB Column LAB Row Copyright © 2005 Altera Corporation 29 Cyclone LAB-Wide Control Signals 10 Available LAB-Wide Signals 2 Clocks 2 Clock Enables (1 Per Clock) 2 Asynchronous Clears 1 Asynchronous Load or Preset 1 Synchronous Clear 1 Synchronous Load 1 Add/Subtract Control Copyright © 2005 Altera Corporation 30 LAB Control Signal Generation LAB Row Clocks Per Region 8 / Local interconnect Local interconnect Local interconnect Local interconnect Local interconnect Local interconnect CLKENA1 CLK1 Copyright © 2005 Altera Corporation 31 CLK2 CLKENA2 SYNCLOAD ASYNCLOAD /LABPRE CLR1 CLR2 ADDNSUB SYNCCLR Control Signal Details Clock & Clock Enables Are Linked LABCLKENA1 Cannot Control LABCLK0 Clock Inversions Are Performed at the LAB 1 Global Clock Can Be Used for Rising & Falling Edges Registers But Requires 2 LAB Clocks Synchronous Load & Clear Affect All LAB LEs Other Registers Must Be Placed in Other Labs Copyright © 2005 Altera Corporation 32 Cyclone LE Datasheet Image Copyright © 2005 Altera Corporation 33 Cyclone LE Features 4-Input Look-Up Table (LUT) Configurable Register 2 Operation Modes Dynamic Add/Subtract Control Carry-Select Chain Logic Performance-Enhancing Features LUT & Register Chain Area-Enhancing Features Register Packing & Feedback Copyright © 2005 Altera Corporation 34 Cyclone LE Inputs/Outputs Inputs 4 Data 2 LE Carry-Ins & 1 Lab Carry-In 1 Dynamic Addition/Subtraction Control Register Controls Outputs 2 LE Carry-Outs 2 Row/Column/DirectLink Outputs 1 Local Output 1 LUT Chain & 1 Register Chain Copyright © 2005 Altera Corporation 35 LE Register Controls Clock/Clock Enable Synchronous & Asynchronous Clear Synchronous & Asynchronous Load & Data Asynchronous Preset Preset Function Loads a ‘1 ALD/PRE ADATA Q D ENA CLRN Copyright © 2005 Altera Corporation 36 Cyclone LE Operation Modes Normal General Combinatorial or Registered Logic Dynamic Arithmetic Used for Adders Counters Accumulators Comparators Uses Carry Chain for Faster Operation Chosen Automatically by Quartus® II & Nativelink® Synthesis tools Based On Design & Design Constraints Copyright © 2005 Altera Corporation 37 Cyclone LE Normal Mode sload sclear aload Register Chain addnsub Reg data1 data2 data3 cin 4-input LUT data4 clock ena aclr Row, Column & Direct Link Routing Local Routing LUT Chain Register Chain Copyright © 2005 Altera Corporation 38 Cyclone Dynamic Arithmetic Mode LAB Carry-in Carry-in0 Carry-in1 Carry-in Logic Register Chain input addnsub Data1 Data2 Data3 Register Control Signals Two 2-input LUTs (Sum) Two 2-input LUTs (Carry) Sync Load & Clear Logic Reg Row, Column & Direct Link Routing Local Routing Carry-Out Logic CarryOut0 CarryOut1 Copyright © 2005 Altera Corporation 39 Register Chain Output Cyclone Carry Chain Details LAB Carry-in A1 0 1 B1 Le1 LE1 Sum1 A2 B2 Le2 LE2 Sum2 A3 B3 Le3 LE3 Sum3 A4 B4 LE4 Le4 Sum4 A5 B5 LE5 Sum5 1 0 A6 B6 LE6 Sum6 A7 B7 LE7 Sum7 A8 B8 LE8 Sum8 A9 B9 LE9 Sum9 A10 B10 LE10 Sum10 LAB Carry-out Copyright © 2005 Altera Corporation 40 Carry Chains Begin & End in Any LE 2 Carry Chains Can Exist in Any LAB Carry-Select Generated in LEs 5 & 10 Every LE Not in Critical Timing Path LUT & Register Chains LUT Chain Output of LUT Connects Directly to LUT Below Available Only in Normal Mode Ex. Wide Fan-in Functions LE1 Register Chain Output of Register Connects Directly to Register Below (Shift Register) LUT Can Be Used for Unrelated Function LUT Ex. LE Shift Register Chain Both Chains End at LAB Boundary Copyright © 2005 Altera Corporation 41 D Q Lut LE2 Lut D Q Register Chain Les 3 - 10 Register Packing & Feedback Register Packing LUT & Register Drive Different Outputs Normal Mode Only Ex. State Machines Register Feedback Register Output Feeds Its Own LUT Register Packing Register Feedback Le Le LUT D Q Copyright © 2005 Altera Corporation 42 LUT D Q Controlling Register Packing Quartus II Assignment Editor Auto Packed Registers Settings Affect Both Register Packing & Register Feedback OFF: No Packing Except Registers Packed by Another EDA tool Normal (Default): Register Packing Used with No Decrease in fmax Minimize Area: Aggressive Register Packing: May Decrease fmax Minimize Area with Chains: Aggressive Packing of Functions that Are Part of Arithmetic or Register Cascade Chains. Copyright © 2005 Altera Corporation 43 Control Signals Cyclone II LABs 38 LAB Input Lines 4 4 Local Interconnect 16 LEs Local interconnect LAB-Wide Control Signals 4 4 4 4 4 4 4 4 4 4 4 4 4 4 Copyright © 2005 Altera Corporation 44 16 LE Feedback Lines LE1 LE2 LE3 LE4 LE5 LE6 LE7 LE8 LE9 LE10 LE11 LE12 LE13 LE14 LE15 LE16 Carry & Register Chain Cyclone II LAB-Wide Control Signals 8 Available LAB-Wide Signals 2 Clocks 2 Clock Enables (1 Per Clock) 2 Asynchronous Clears 1 Synchronous Clear 1 Synchronous Load Copyright © 2005 Altera Corporation 45 LAB Control Signal Generation LAB Row Clocks 6 Local interconnect Local interconnect Local interconnect Local interconnect Same Restrictions as Cyclone CLKENA1 CLK1 Copyright © 2005 Altera Corporation 46 CLKENA2 CLK2 SYNCLOAD CLR1 SYNCCLR CLR2 Cyclone II LE Diagram Copyright © 2005 Altera Corporation 47 Cyclone II LE Features Two Modes Normal Arithmetic Carry Chains Ripple Carry, Not Carry-Select Like Cyclone Register Packing Register Feedback Register Chains Copyright © 2005 Altera Corporation 48 Cyclone II LE Normal Mode sload sclear (LAB-Wide) (LAB-Wide) Register Chain data1 data2 data3 cin Reg 4-input LUT clock (LAB-Wide) ena (LAB-Wide) aclr (LAB-Wide) data4 Row, Column & Direct Link Routing Local Routing Register Chain Register Feedback Copyright © 2005 Altera Corporation 49 Cyclone II LE Arithmetic Mode sload sclear (LAB-Wide) (LAB-Wide) Register Chain data1 data2 3-input LUT Reg clock (LAB-Wide) cin ena (LAB-Wide) 3-input LUT aclr (LAB-Wide) Row, Column & Direct Link Routing Local Routing Register Chain cout Copyright © 2005 Altera Corporation 50 Register Feedback Cyclone II LE Carry Chains Connected Vertically LE16 to LE1 in LAB Below Ripple Carry Implementation Copyright © 2005 Altera Corporation 51 Register Packing & Feedback Register Packing LE LUT Register Packing LUT & Register Drive Different Outputs Normal Mode Only Ex. State Machines D Q Register Feedback LE D Q LUT Register Feedback Register Output Feeds Its Own LUT Ex. Registered Inputs on IP/Sublevels Register Chain LE1 LUT D Q Register Chain LE2 LUT D Q Copyright © 2005 Altera Corporation 52 Register Output Feeds Register Input Below Ends at LAB Boundary Ex. Shift Registers Interconnects (Routing) Interconnects to Route Between All Device Blocks Horizontal Interconnects DirectLink R4 R24 Vertical Interconnects Carry, LUT, Register Chains C4 C16 Copyright © 2005 Altera Corporation 53 DirectLink LE2 LE3 LE4 LE5 LE6 LE7 LE8 LE9 LE10 Copyright © 2005 Altera Corporation 54 LE1 LE2 LE3 LE4 LE5 LE6 LE7 LE8 LE9 LE10 Local Interconnect LE1 Local Interconnect Local Interconnect Allows Blocks to Drive Local Interconnects of Neighboring Blocks in the Same Row M4K DirectLink (cont.) Provides Fast Communication between Neighboring Blocks One LE Has Fast Access to Up to 30 (Cyclone) or 48 (Cyclone II) LEs in Area Saves Row Resources Copyright © 2005 Altera Corporation 55 Row & Column Interconnects C16 2 Sizes of Row & Column Lines R4 & 24 C4 & C16 Each Block Has Own R4/C4 Resources to Drive in All Directions R24/C16 Do Not Interface Directly with Blocks R4 R24 Copyright © 2005 Altera Corporation 56 C4 Copyright © 2005 Altera Corporation 57 Interconnect Details Staggered Interconnects End-to-End Connections for Longer Routes LAB-Neighboring LABs Can Use Interconnects from Neighboring LABs Proximity is Key to Logic Performance in Cyclone & Cyclone II Copyright © 2005 Altera Corporation 58 DirectDrive™ Technology Each Interconnect Line Driven by Single Source Consistent Access to Routing Eliminates Congestion Uniform Routing Resources Across Device Ensures Blocks Can be Moved within or between Designs Copyright © 2005 Altera Corporation 59 Cyclone Series Comparison Device Family Parameter / Resource Cyclone Cyclone II Logic Density (LEs) 3,000 to 20,000 4,500 to 68,000 LAB-Wide Control Signals 10 LAB-Wide Signals (+ Async. Load/Preset & ADDnSUB) 8 LAB-Wide Signals LE Control Signals 6 Per LE (+ Async. Load/Preset) 5 Per LE LUT Chain Yes No Interconnects R4 C4 R4/R24 C4/C16 Copyright © 2005 Altera Corporation 60 Designing with Cyclone & Cyclone II Devices Architecture – PLLs & Clock Generation Copyright © 2005 Altera Corporation PLLs & Clock Generation Global Clocking Resources Clock Control Block PLLs Copyright © 2005 Altera Corporation 62 Global Clocking Resources Clock Nets Dedicated Clock Pins Dual-Purpose Pins Copyright © 2005 Altera Corporation 63 Global Clock Network Cyclone Device Availability 8 Global Clocks All Cyclone EP2C5 & EP2C8 16 Global Clocks EP2C20 & Larger Global Clock Network [n..0] n = 7 or 15 Provide Clocks for All Device Blocks Use for High-Fan Out Control/Data Signals Copyright © 2005 Altera Corporation 64 Dedicated Clock Pins Uses High Fan-Out Control Signals CLK, ENA, ACLR & SCLR High Fan-Out Data PLL Inputs Availability 4 (All Cyclone) 2 on Left & Right 8 (EP2C5, EP2C8) 4 on Left & Right 16 (EP2C20 & Larger) 4 on each Side Copyright © 2005 Altera Corporation 65 Dual-Purpose Clock Pins Uses High Fan-Out Control Signals CLK, ENA, ACLR & SCLR DQS of DDR Memory Interface TRDY/IRDY for PCI Interface High Fan-Out Data Availability 8 (All Cyclone, EP2C5 & EP2C8) 2 on each Side 20 (EP2C20 & Larger) 4 on Left & Right 6 on Top & Bottom Copyright © 2005 Altera Corporation 66 Global Clock Control Block 1 PLL Output Cyclone Static Clock Selection 1 Dedicated Clock Input 1 Dual-Purpose Clock Input GCLK[n] Internal Logic Provides Input to Global Clocks Nets One Per Global Clock Static Controls (Cyclone & Cyclone II) Clock Selection Clock Enable/Disable Dynamic Controls (Cyclone II Only) Clock Selection Clock Enable/Disable Copyright © 2005 Altera Corporation 67 Cyclone II Control Block Internal Logic Internal Logic Static Clock Selection 1 Dual-Purpose Clock Pin GCLK[n] Dedicated Clock Input Pins 4 2 Clock Control Block Static Clock Selection PLL Outputs 2 2 3 Dynamic Clock Selection Clock Select[1..0](1) Copyright © 2005 Altera Corporation 68 Note: 1) May be driven by internal logic or pin ALTCLKCTRL Megafunction Use for Dynamic Internal & External Clock Controls Copyright © 2005 Altera Corporation 69 Cyclone & Cyclone II PLL Features General-Purpose Multiplication & Division Three Output Frequencies Cyclone: 2 Internal & 1 External Cyclone II: 3 Internal & 1 External Three Operation Modes Single-Ended & Differential Inputs Single-Ended & Differential External Output Copyright © 2005 Altera Corporation 70 PLL Features (Cont.) Phase Shifting Uses VCO & Output Counters (No Delay Elements) Programmable Duty Cycle Lock Detect Signal Indicates a Stable Output in Phase with Reference Clock PLLENABLE, ARESET, & PFDENA Control Signals Copyright © 2005 Altera Corporation 71 Cyclone II PLL Additional Features Clock Switchover Manual Switchover (No Automatic Circuitry) Use CLKSWITCH Port to Select PLL Input Programmable Bandwidth Low Bandwidth Filters Jitter High Bandwidth Locks Faster Gated Lock User Specifies Number of Clock Cycles Before Valid Lock Signal Copyright © 2005 Altera Corporation 72 PLL Clock Feedback Modes No Compensation PLL Input Clock Aligned with PLL Output Clock “B” in Phase with “C” Normal Clock Edge at Input Pin Aligned with Clock Edge at LE Register “A” in Phase with “D” Zero-Delay Buffer Clock Edge at Input Pin Aligned with Clock Edge at External Output Clock Pin “A” in Phase with “F” Copyright © 2005 Altera Corporation 73 input Delay A Input Pin PLL B C FPGA Clock Tree (internal) Output Delay D LE Register F Output Pin Cyclone PLL To Logic or I/O Lock Detect CLK0 or LVDSCLK1p G0 fVCO N Δt PFD CP/LF 8 G1 VCO Global Clock Network 8 CLK1 or LVDSCLK1n Δt M E VCO Phase Selection Copyright © 2005 Altera Corporation 74 I/O Buffer Post-Scale Counter Cyclone PLL Specifications Feature Description PLL Output Taps Up to 12 Output Frequencies Per Device Off-Chip Output Clocks 2 Single-Ended / 2 Differential Frequency Range Input: 15.625 to 156 MHz Output (Internal) : 10 to 312 MHz Output (External): 15.625 to 320 MHz VCO Frequency Range 500 MHz to 1 GHz Input Frequency Jitter ± 200 ps Multiplication/Division f out f in NM*K M : 2 to 32 N, K (G or E) : 1 to 32 Output Frequency Jitter ± 300 ps Programmable Phase Adjustable in Steps as Small as 125 ps Lock Time 10 - 100 µs Control Signals PFDENA, ARESET, PLLENA Copyright © 2005 Altera Corporation 75 Cyclone II PLL Copyright © 2005 Altera Corporation 76 Cyclone II PLL Clock Inputs PLL1 PLL2 PLL3 PLL4 CLK0 CLK1 CLK2 CLK3 CLK4 CLK5 CLK6 CLK7 CLK8 CLK9 CLK10 CLK11 CLK12 CLK13 CLK14 CLK15 EP2C5 EP2C8 EP2C20 EP2C35 EP2C50 EP2C70 Device Copyright © 2005 Altera Corporation 77 Cyclone II PLL Feature Summary Feature Description PLL Output Taps Up to 12 Output Frequencies Per Device Off-Chip Output Clocks 4 Single-Ended / 4 Differential Frequency Range Input: 10 to 311 MHz Output (Internal) : 10 to 402.5 MHz Output (External): 10 to 200 MHz VCO Frequency Range 300 MHz to 1 GHz Multiplication/Division f out f M in N *C M, C : 1 to 32 N : 1 to 4 Programmable Phase Adjustable in Steps as Small as 125 ps Lock Time 1 ms (Maximum) Control Signals PFDENA, ARESET, PLLENA Note: 1) All values pending characterization Copyright © 2005 Altera Corporation 78 Cyclone PLL/Clock Layout DPCLK DPCLK DPCLK DPCLK 4 Clock Control Blocks Global Clocks 8 CLK 2 PLL1 4 8 4 DPCLK DPCLK 79 (1) CLK 2 DPCLK Notes: 1) EP1C3 has only PLL1 2) Functional Diagram Copyright © 2005 Altera Corporation PLL2 DPCLK Cyclone II PLL/Clock Layout DPCLK DPCLK EP2C5 & EP2C8 PLL2 DPCLK DPCLK 8 CLK 4 4 8 4 Global Clocks DPCLK 4 CLK DPCLK 4 Clock Control Blocks PLL1 Note: 1) Functional Diagram DPCLK Copyright © 2005 Altera Corporation 80 DPCLK Cyclone II PLL/Clock Layout EP2C20 EP2C35 EP2C50 EP2C70 CLK DPCLK CDPCLK 2 DPCLK 4 2 CDPCLK PLL2 PLL3 CDPCLK CDPCLK 4 (2) 4 Clock Control Blocks DPCLK DPCLK 16 CLK 4 4 16 4 4 Global Clocks DPCLK CLK DPCLK 4 CDPCLK Note: 1) Functional Diagram 2) Only 1 CDPCLK can feed the clock control block at one time. The other will be general purpose I/O Copyright © 2005 Altera Corporation 81 CDPCLK PLL1 PLL4 CDPCLK 2 4 DPCLK 2 DPCLK CLK CDPCLK EP1C3 100-Pin TQFP Exeptions 2 Dedicated Clock Input Pins 1 on Left & Right Sides 5 Total Dual-Purpose Pins No External Clock Output No LVDS Input Copyright © 2005 Altera Corporation 82 ALTPLL Megafunction Copyright © 2005 Altera Corporation 83 ALTPLL (cont.) Clock Switchover Copyright © 2005 Altera Corporation 84 ALTPLL (cont.) Set Output Frequency Set Phase Shift Set Duty Cycle Copyright © 2005 Altera Corporation 85 Cyclone Series Comparison Device Family Parameter / Resource Cyclone Cyclone II Global Clock Nets Up to 8 Up to 16 Clock Input Pins Up to 4 Up to 16 Dual-Purpose Pins Up to 8 Up to 20 Dynamic Clock Control No Yes PLLs Up to 2 Up to 4 PLL Locations Left/Right Sides Corners PLL Outputs 3 Output Frequencies (2 Internal & 1 External) 3 Output Frequencies (3 Internal & 1 External) PLL Features Phase Shifting, Lock Detect & Programmable Duty Cycle Cyclone Features + Manual Switchover, Programmable Bandwidth & Gated Lock Copyright © 2005 Altera Corporation 86 Designing with Cyclone & Cyclone II Devices Embedded Memory Copyright © 2005 Altera Corporation M4K Embedded Memory Up to 5 Columns of M4K Blocks Cyclone Cyclone II M4K Columns Total Blocks Total Bits EP1C3 1 13 59,904 EP1C4 1 17 EP1C6 2 EP1C12 EP1C20 Device M4K Columns Total Blocks Total Bits EP2C5 2 26 119,808 78,336 EP2C8 2 36 165,888 20 92,160 EP2C20 2 52 239,616 3 52 239,616 EP2C35 3 105 483,840 5 64 294,912 EP2C50 3 129 594,432 EP2C70 5 250 1,152,000 250 MHz Copyright © 2005 Altera Corporation 88 Device 250 MHz M4K Blocks Features 4608 Bits Per Block 9 Configurable Sizes 4 Clocking Modes Synchronous Inputs Optional Output Registers Parity Bit Support Mixed Width Capability Byte Enable Support Address Clock Enable Cyclone II Only Memory Initialization Copyright © 2005 Altera Corporation 89 Modes True Dual-Port RAM Simple Dual-Port RAM Single-Port RAM FIFO ROM Shift Register Mode ROM RAM Block with Write Enable Disabled Data Embedded in Configuration File Loaded (Initialized) at Configuration Time Copyright © 2005 Altera Corporation 90 ROM address[ ] q[ ] clock inclocken Single-Port RAM One Address Port for Reading & Writing Clocking Options Single Clock Input/Output Clock Mode Copyright © 2005 Altera Corporation 91 Single-Port RAM address[ ] data[ ] wren inclock inclocken inaclr q[ ] outclock outclocken outaclr Simple Dual-Port RAM Two Address Inputs One Read Address One Write Address Mixed Width Capability Clocking Options Single Clock Input/Output Clock Mode Read/Write Clock Mode Copyright © 2005 Altera Corporation 92 Simple Dual-Port RAM wraddress[ ] data[ ] wren inclock inclocken inaclr rdaddress[ ] q[ ] rden outclock outclocken outaclr True Dual-Port RAM Two Address Inputs Port A & Port B Supports Two Simultaneous Reads or Writes Mixed Width Capability Clocking Options Input/Output Clock Mode Independent Clock Mode Copyright © 2005 Altera Corporation 93 True Dual-Port RAM dataA[ ] addressA[ ] dataB[ ] addressB[ ] wrenA clockA clockenA aclrA qA[ ] wrenB A B clockB clockenB aclrB qB[ ] FIFO First-In First-Out Memory Ideal for Rate Changing Clocking Options Single Clock Read/Write Clock Mode Copyright © 2005 Altera Corporation 94 Shift Register M4K Blocks Support W x M x N Shift Register W = Bus Width M = Length of Each Tap N = Number of Taps Multiple Blocks Used Automatically when W*N > 36 W*M*N > 4608 Memory Outputs Feed Datain Copyright © 2005 Altera Corporation 95 Nine Configuration Sizes 4K x 1 2K x 2 1K x 4 512 x 8/9 256 x 16/18 128 x 32/36 Copyright © 2005 Altera Corporation 96 M4K Simple Dual-Port Read Port 4Kx1 2Kx2 1Kx4 512x8 256x16 128x32 Write Port 4Kx1 2Kx2 1Kx4 512x9 256x18 128x36 Copyright © 2005 Altera Corporation 97 512x8 256x16 128x32 512x9 256x18 128x36 M4K True Dual-Port Port B Port A 4Kx1 2Kx2 1Kx4 512x8 256x16 4Kx1 2Kx2 1Kx4 512x9 256x18 Copyright © 2005 Altera Corporation 98 512x8 256x16 512x9 256x18 Clocking Modes Clocking Mode True-Dual Port Mode Independent Input/Output Copyright © 2005 Altera Corporation 99 Single-Port Mode Read/Write Single Simple DualPort Mode Synchronous Implementation All Inputs Registered Self-Timed Write Enable (WREN) Strobe Generated Automatically Alleviates Memory Setup/Hold Time Design Worry Memory Write Occurs during Falling Edge of Clock Optional Output Registers Fully Pipelined Memory Copyright © 2005 Altera Corporation 100 Pseudo-Asynchronous Mode True Asynchronous Memory Not Supported Neither Input nor Output Is Registered Generate Write Enable while Meeting Data & Address Setup & Hold Times Pseudo-Asynchronous Implementation Supported in Dual-Port Modes Use Negative-Edge Clock for Read Address & Enable Bypass Output Registers Copyright © 2005 Altera Corporation 101 Single Address Read & Write New Data Available on Rising Edge of Same Clock (Flow-Through) Single-Port True Dual-Port Same Port (e.g. Write A while Read A) Masked Bytes Are Unknown Old Data Output Simple Dual-Port (Single Clock) True Dual-Port (Single Clock) Mixed Ports (e.g. Write A while Read B) Unsupported with Multi-Clock Configurations Copyright © 2005 Altera Corporation 102 Parity Supported by All Blocks Data Sizes Provide for 1 Extra Bit Per byte (4608 bits = 4096 + 512) 512 x 9 256 x 18 128 x 36 Create Custom Logic to Check/Generate Bits Use for Control Bits Also Copyright © 2005 Altera Corporation 103 M4K Block Memory Packing Partition Single M4K into Two Independent 2K Memory Blocks Supported for Single-Ports Only Features independently Defined Widths Increase Memory Utilization Configured As True Dual-Port with MSB High or Low LOGIC 256 X 4 LOGIC LOGIC 128 X 16 LOGIC Copyright © 2005 Altera Corporation 104 Address Clock Enable (addressstall) Holds Previous Address Available on Each Address Input Example Use : Cache Memory 1 0 addressA[n..0] Reg Memory addressstall Address Registers clock Cyclone II Only Copyright © 2005 Altera Corporation 105 M4K Interface R4 Local interconnect DirectLink dataout M4K RAM Block DirectLink byte enable DirectLink control signals clocks address C4 datain LAB Row Clocks 6 Copyright © 2005 Altera Corporation 106 C4 Memory Compiler MegaWizard Use for All Memory Functions Copyright © 2005 Altera Corporation 107 Ex. Dual-Port RAM Simple or True Dual-Port Mixed Width? implementation Copyright © 2005 Altera Corporation 108 Memory Size Ex. Dual-Port RAM Copyright © 2005 Altera Corporation 109 Verilog/VHDL RAM Guidelines NativeLink™ EDA Tools Support RAM inference Check Documentation for Various Implementations always@(posedge mem_clk) PROCESS (inclock) begin begin addr_reg <= addr; if (we) begin mem[addr]<=din; end assign dout=mem[addr_reg]; IF rising_edge(inclock) then address_reg <= address; IF (we = '1') then mem(conv_integer(address)) <= data; END IF; END IF; END PROCESS; q <= mem(conv_integer(address_reg)); Traditional Black Box Flow Use the MegaWizard to Generate the Wrapper Black Box in the 3rd Party tool Copyright © 2005 Altera Corporation 110 Memory Control Signals Cyclone Independent Clock Enables for Each Clock Asynchronous Clear on All Registers Individually Configurable Cyclone II Clock Enable Input Disables Clock to Entire Memory Asynchronous Clear on Output Registers Copyright © 2005 Altera Corporation 111 Cyclone Series Comparison Parameter / Resource Device Family Cyclone Cyclone II Memory Features Parity Bit Byte Enable Mixed Width Mixed Clocking Initialization Memory Packing All Cyclone + Address Clock Enable Performance 250 MHz 250 MHz Copyright © 2005 Altera Corporation 112 Designing with Cyclone & Cyclone II Devices Cyclone II Embedded Multiipliers Copyright © 2005 Altera Corporation Cyclone II Embedded Multipliers Complete Hardware Multipliers Optimized for CostEffective DSP Operations No Additional Arithmetic Logic Up to 3 Columns of Embedded Multipliers 250 MHz Performance Fully Pipelined Copyright © 2005 Altera Corporation 114 Device Embedded Multiplier Columns Total Embedded Multipliers EP2C5 1 13 EP2C8 1 18 EP2C20 1 26 EP2C35 1 35 EP2C50 2 86 EP2C70 3 150 Embedded Multiplier Features 2 Modes One 18 x 18 Multiplier Two 9 x 9 Multipliers Full Precision Outputs Dedicated Input & Output Registers Dynamic Signed & Unsigned Support 1 = Signed; 0 = Unsigned Copyright © 2005 Altera Corporation 115 9 x 9 Multiplication signa signb aclr clk ena Data A[8..0] 9 Reg X Data B[8..0] 9 Data Out[17..0] Reg 18 Reg 9x9 Data A[17..9] 9 Reg X Data B[17..9] 9 Data Out[35..18] Reg 18 Reg 9x9 Copyright © 2005 Altera Corporation 116 Embedded Multiplier Interface Copyright © 2005 Altera Corporation 117 Designing with Cyclone & Cyclone II Devices Input/Output Copyright © 2005 Altera Corporation Input/Output I/O Banks I/O Blocks I/O Elements & Features DDR Interface High-Speed Differential Interface Copyright © 2005 Altera Corporation 119 I/O Banks Cyclone, EP2C5 & EP2C8 EP2C20 & Larger 2 1 4 2 5 1 6 3 4 Copyright © 2005 Altera Corporation 120 3 8 7 I/O Banks Have Separate VCCIO Can Support Different I/O Standard Can Support Multiple Standards with Same VCCIO Have Dual-Purpose VREF Unused VREF Pins Available as User I/O Copyright © 2005 Altera Corporation 121 I/O Blocks Grouping of I/O Elements (IOEs) Share Local Interconnect Provides Data & Control Row I/O Blocks Cyclone: Up to 5 IOEs Cyclone II: Up to 3 IOEs Column I/O Blocks Cyclone: Up to 3 IOEs Cyclone II: Up to 4 IOEs Copyright © 2005 Altera Corporation 122 Row I/O Block Interface R4 Local Interconnect (1) DirectLink (2) Row I/O Block Row Pins: Up to 5 (Cyclone) Up to 3 (Cyclone II) C4 I/O CLK[5..0] Copyright © 2005 Altera Corporation 123 Note: 1) 35 (Cyclone) or 21 (Cyclone II) 2) 10 (Cyclone) or 6 (Cyclone II) Column I/O Block Interface Column Pins: Up to 3 (Cyclone) Up to 4 (Cyclone II) Column I/O Block Local Interconnect (1) I/O CLK[5..0] (2) R4 C4 C4 Note: 1) 21 (Cyclone) or 28 (Cyclone II) 2) 6 (Cyclone) or 8 (Cyclone II) Copyright © 2005 Altera Corporation 124 I/O Element Structure VCCIO VCCIO PCI Clamp Diode OE Programmable Pull-Up Resistor Dt OUT Bus-Hold Circuit Dt Dt Copyright © 2005 Altera Corporation 125 in to/from Core I/O Features Differential & Single-Ended I/O Standards Programmable Output Drive Strength Slew-Rate Control Bus-Hold Circuitry Weak Pull-Ups during Configuration Programmable Pull-Up Resistors Programmable Input & Output Delays Series On-Chip Termination Cyclone II Only Copyright © 2005 Altera Corporation 126 IOE Control Signal Copyright © 2005 Altera Corporation 127 Cyclone I/O Standard Support 3.3-V LVTTL/LVCMOS 2.5-V LVTTL/LVCMOS 1.8-V LVTTL/LVCMOS 1.5-V LVCMOS PCI LVDS SSTL-3 Class I & II SSTL-2 Class I & II Differential SSTL-2 Copyright © 2005 Altera Corporation 128 See Cyclone Handbook for I/O Bank Support Cyclone II I/O Standard Support SSTL-2 Class I & II SSTL-18 Class I & II HSTL-18 Class I & II HSTL-15 Class I & II “Pseudo”-Differential SSTL-2 Class I & II “Pseudo”- Differential SSTL-18 Class I & II “Pseudo”- Differential HSTL-18 Class I & II “Pseudo”- Differential HSTL-15 Class I & II See Cyclone II Handbook 3.3-V LVTTL/LVCMOS 2.5-V LVTTL/LVCMOS 1.8-V LVTTL/LVCMOS 1.5-V LVCMOS PCI/PCI-X LVDS mini-LVDS RSDS LVPECL for I/O Bank Support Copyright © 2005 Altera Corporation 129 Cyclone Programmable Drive Strength I/O Standard LVTTL (3.3 V) Copyright © 2005 Altera Corporation 130 IOH/IOL Current Strength Setting (mA) 4, 8, 12, 16, or 24 LVCMOS (3.3 V) 2, 4, 8, or 12 LVTTL (2.5 V) 2, 8, 12, or 16 LVTTL (1.8 V) 2, 8, or 12 LVTLL (1.5 V) 2, 4, or 8 Cyclone II Programmable Drive Strength Cyclone II I/O Standard Copyright © 2005 Altera Corporation 131 IOH/IOL Current Strength Setting (mA) LVTTL/LVCMOS (3.3 V) 4, 8, 12, 16, 20, 24 LVTTL/LVCMOS (2.5 V) 4, 8, 12, 16 LVTTL/LVCMOS (1.8 V) 2, 4, 6, 8, 10, 12 LVCMOS 1.5 V 2, 4, 6, 8 SSTL-2 Class I 8, 12 SSTL-2 Class II 16, 20, 24 SSTL-18 Class I 4, 6, 8, 10, 12 SSTL-18 Class II 8, 16, 18 HSTL-18 Class I 4, 6, 8, 10, 12 HSTL-18 Class II 16, 18, 20 HSTL-15 Class I 4, 6, 8, 10, 12 HSTL-15 Class II 16 Cyclone II Series OCT Series On-Chip Termination Supported Driver Impedance & Series Termination Implementation Uses Programmable Drive Strength Feature Supported Standards 50 Ω Resistance 2.5- & 1.8-V LVCMOS/LVTTL SSTL-2 Class I & II SSTL-18 Class I 25 Ω Resistance 3.3-V LVCMOS/LVTTL Copyright © 2005 Altera Corporation 132 Other I/O Features PCI Support on Side I/O 64-Bit, 66-MHz PCI v2.2 64-Bit, 100-MHz PCI-X Mode 1 Cyclone II Only Hot Socketing Support Copyright © 2005 Altera Corporation 133 Multi-Volt VCCIO Input (Volts) Output (Volts) 1.5 1.8 2.5 3.3 5.0 1.5 V ╳ ╳(3) ╳(3) ╳(3) ╳ 1.8 V ╳(6) ╳ ╳(3) ╳(3) ╳(4) ╳ 2.5 V ╳ ╳(3) ╳(4) ╳(4) ╳ 3.3 V ╳(5) ╳ ╳(4) ╳(4) ╳(4) ╳(2) 1.5 1.8 2.5 3.3 5.0 ╳ ╳(1) Notes: 1) Cyclone Only; VCCIO of 3.3V exceed Vth for 5.0V LVTTL outputs; VCCIO of 3.3V does not exceed Vth for 5.0 LVCMOS outputs; Supported on 2) Cyclone Only; Requires external resistors & PCI diode turned on; Supported on 3) Must disable PCI clamping diode 4) May drive devices (like Cyclone & Cyclone II) that tolerate inputs higher than VCCIO 5) VCCIO supply current may be slightly higher than expected 6) Cyclone II Only; VCCIO supply current may be slightly higher than expected Copyright © 2005 Altera Corporation 134 External Memory Support Cyclone DDR SDRAM FCRAM Up to 133 MHz Cyclone II DDR SDRAM DDR2 SDRAM Up to 167 MHz Left/Right I/O Banks : Class I Termination Only QDRII SRAM Left/Right I/O Banks : Class I Termination Only Copyright © 2005 Altera Corporation 135 DDR Implementation Data & Parity Bits Up to 18 Pins for Data & Parity DQS Pins Use Dual-Purpose Pins to Drive LE Registers PLL Generate System & Shifted DQ Write Clock Clock Delay Control Generate Shifted DQS Read Clock DDR/QDR Pins DQ Pins Copyright © 2005 Altera Corporation 136 DQS Pins DQ Pins DM Pins DDR input interface Details Data from External Memory Device •Registers implemented in LEs. Aligns DQS to Center of DQ (1) DQS DQ Δt Note: 1) Cyclone uses programmable delay element & Cylcone II uses clock delay control circuitry Global Clock Network Global Clock Multiplexer or Clock Control Block Copyright © 2005 Altera Corporation 137 Capture Registers Synchronization Registers/FIFO LE Reg LE Reg A LE Reg LE Reg B Global Clock DDR Output Interface Details DQS Output Enable LE Reg Data to External Memory Device DQ LE Reg Vcc LE Reg Gnd LE Reg In-Phase 1X Output Global Clock PLL Phase shifted 1X Output Output Enable LE Reg A LE Reg B LE Reg Phase shift of 72 degrees for FCRAM Copyright © 2005 Altera Corporation and 90 degrees for all others 138 LE Reg Cyclone II DDR Enhancements DQS Postamble Circuitry Copyright © 2005 Altera Corporation 139 DDR Groups Cyclone Up to 8 Groups in x8 Mode Cyclone II Up to 14 Groups in x8 Mode Up to 8 Groups in x9, x16, or x18 Modes Copyright © 2005 Altera Corporation 140 Differential Signaling Support Up to 640-Mbps Performance Supported On All Sides of Device Requires Simple External Network Does Not include Dedicated SERDES or PLL Cyclone Device Receiving Device External Resistor Network Copyright © 2005 Altera Corporation 141 External Termination Resistor Cyclone II Additional Support LVDS Receiver : Up to 805 Mbps (402.5 MHz Clock) Transmitter : Up to 622 Mbps (311 MHz Clock) RSDS & mini-LVDS : Up to 170 Mbps (85 MHz Clock) LVPECL (Clock Input Only) : Up to 150 MHz Diff. HSTL & Diff. SSTL : Up to 167 MHz Copyright © 2005 Altera Corporation 142 Cyclone LVDS Support Device Package Number of LVDS Channels EP1C3 144-Pin TQFP 34 EP1C4 324-Pin FBGA 103 400-Pin FBGA 129 144-Pin TQFP 29 240-Pin PQFP 72 256-Pin FBGA 72 240-Pin PQFP 66 256-Pin FBGA 72 324-Pin FBGA 103 324-Pin FBGA 95 400-Pin FBGA 129 EP1C6 EP1C12 EP1C20 Copyright © 2005 Altera Corporation 143 Cyclone II LVDS Support Device Device EP2C5 EP2C8 EP2C20 EP2C35 EP2C50 EP2C70 Copyright © 2005 Altera Corporation 144 Package 144-Pin TQFP 208-Pin PQFP 144-Pin TQFP 208-Pin PQFP 256-Pin FBGA 256-Pin FBGA 484-Pin FBGA 484-Pin FBGA 672-Pin FBGA 484-Pin FBGA 672-Pin FBGA 672-Pin FBGA 896-Pin FBGA Number of LVDS Channels 33 58 31 55 77 56 132 135 205 122 193 164 261 Feature Comparison Device Family Parameter / Resource Cyclone Cyclone II I/O Banks Up to 4 Up to 8 I/O Standard Support Differences LVDS, RSDS, SSTL, PCI, LVTTL, LVCMOS Same as Cyclone, Plus: HSTL, PCI-X, LVPECL Programmable Drive Strength Support LVTTL, LVCMOS LVTTL, LVCMOS, SSTL, HSTL On-Chip Termination No Yes External Memory Support DDR, FCRAM DDR, DDR2, QDR II DDR Memory Bit Widths X8 X8, x9, x16, x18 Copyright © 2005 Altera Corporation 145 Designing with Cyclone & Cyclone II Devices Configuration Copyright © 2005 Altera Corporation Configuration SRAM Devices Require Configuration at Power-Up Operating Modes Command Mode Configuration Configuration Data Downloaded from Storage Initialization Clears Registers Enables I/Os User Mode Copyright © 2005 Altera Corporation 147 Configuration Schemes Configuration Scheme Interface Fast Active Serial (Cyclone II Only) Dedicated Configuration Pins Source MSEL Pins 1 0 EPCS64 & EPCS16 Serial Configuration Devices 1 0 Active Serial (AS) Dedicated Configuration Pins All Serial Configuration Devices (Cyclone/EPCS64 Not Supported) 0 0 Passive Serial Dedicated Configuration Pins Enhanced Configuration Devices EPC2 & EPC1 Configuration Devices Microprocessor (Intelligent Host) Download Cable 0 1 JTAG Dedicated JTAG Pins Download Cable Microprocessor (Intelligent Host) JAM™ STAPL Copyright © 2005 Altera Corporation 148 N/A Fast Active Serial & Active Serial Configuration Data Stored in Low-Cost Serial Configuration Devices FPGA Controls Configuration (Master) Active Serial : Up to 20 MHz Fast Active Serial : Up to 40 MHz Multi-Device Chain Supported First FPGA is Master (Active Mode) All Others Are Slaves (Passive Mode) Serial Configuration Devices Cannot Be Chained Copyright © 2005 Altera Corporation 149 Fast AS & AS Diagram nCONFIG Signals Start of Configuration nSTATUS Indicates Configuration Error CONF_DONE Signals End of Configuration DCLK DATA0/DATA Configuration Data Input nCS0/nCS Chip Select ASDI/ASDO Note: 1) Connect to 3.3-V Supply Copyright © 2005 Altera Corporation 150 Sends Control Signals to Configuration Device Serial Configuration Devices Non-Volatile, Flash-Based Devices Four Variations EPCS64, EPCS16, EPCS4 & EPCS1 Programming Options Download Cables JTAG Indirect Configuration Device Programming (Serial Flash Loader) Next Slide Altera Programming Unit (APU) Third-Party Programmers Copyright © 2005 Altera Corporation 151 JTAG Indirect Configuration Device Programming Programs Serial Configuration Device via JTAG Uses JIC File Generated by Quartus II Procedure JTAG JTAG Device Cyclone or Cyclone II SPI JTAG Device Copyright © 2005 Altera Corporation 152 EPCS4 FPGA Device Configured with JIC Image via JTAG Configuration Device is Programmed with Application Image via Serial Interface Upon Power-up, EP1C3 is Configured with Application Image in Configuration Device JIC Device Programming - User Flow Compile Design for Cyclone Device Copyright © 2005 Altera Corporation 153 Convert .sof to .jic Create JTAG Chain Passive Serial Configuration Configuration Controlled by External Host Enhanced Configuration Device Configuration Device (EPC2 or EPC1) Embedded Processor External Host (MAX or MAX II Device) PC Through Download Cable Up to 100 MHz Configuration Clock Multi-Device Chain Supported EPC2 & EPC1 Devices May Be Cascaded EPC16, EPC8 & EPC4 Devices Cannot Be Cascaded Copyright © 2005 Altera Corporation 154 Passive Serial Diagram Enhanced Configuration Device Embedded Processor or External Host Copyright © 2005 Altera Corporation 155 Enhanced Configuration Device Three Variations EPC16, EPC8 & EPC4 Clocking Internal Oscillator 10, 33, 50 or 66 MHz External Oscillator Up to 133 MHz Programming Download Cable JTAG APU Third-Party Programmer Copyright © 2005 Altera Corporation 156 Store Multiple Pages (Images) for a Single FPGA Program Up to 8 Devices in Parallel with Different Images External Flash Interface Enhanced Configuration Device JTAG Configuration JTAG Boundary Scan Testing & Programming Supported JTAG Instructions Precede Any Device Operating Modes No Output DCLK in AS or Fast AS Mode Bypass Mode Allows Programming of Specific Devices in Chain Copyright © 2005 Altera Corporation 157 JTAG Configuration Diagram Notes: 1) Connect to same supply voltage as download cable. 2) These pins may be connected to support another configuration mode. If no other mode is desired, then pull nCONFIG high, MSEL [1..0] low and DCLK & DATA0 either high or low. Copyright © 2005 Altera Corporation 158 Data Compression Generate Compressed Configuration File in Quartus II Reduces Configuration File Size by 30-60% Device Decompresses Data As It Is Received Device-by-Device Basis in Multi-Device Chains Not Available during JTAG Configuration Copyright © 2005 Altera Corporation 159 Example Configuration Times Cyclone II Device POF Size in Bits (Uncompressed) POF Size in Bits (Compressed) EP2C5 967,680 EP2C8 Approximate Configuration Times Active Serial (20 MHz) Active Serial (40 MHz) Passive Serial (100 MHz) 691,200 35 ms 17 ms 7 ms 1,755,648 1,254,034 63 ms 31 ms 13 ms EP2C20 4,022,784 2,873,417 144 ms 72 ms 29 ms EP2C35 7,147,008 5,105,006 255 ms 128 ms 51 ms EP2C50 10,886,400 7,776,000 389 ms 194 ms 78 ms EP2C70 14,750,208 10,535,863 527 ms 263 ms 105 ms Note: All Values in Table Are Estimates & Subject to Change Copyright © 2005 Altera Corporation 160 Programming Files Programming File AS SOF Cable download using Altera programmer Cable download or APU (Use to program configuration device which in turn configures Cyclone or Cyclone II at power-up) RBF Microprocessor HEX Microprocessor or 3rd-party programmers JIC JTAG Comment POF JAM/JBC Copyright © 2005 Altera Corporation 161 PS Cable download (JTAG indirect configuration uses JTAG and either AS or PS) Cable download, APU or microprocessor Cyclone Series Comparison Parameter / Resource Configuration Modes Copyright © 2005 Altera Corporation 162 Device Family Cyclone Cyclone II Active Serial Passive Serial JTAG Fast Active Serial Active Serial Passive Serial JTAG Literature Cyclone Handbook Cyclone II Handbook AN306: Implementing Multipliers in FPGA Devices AN311: ASIC-to-FPGA Design Methodology and Guidelines AN344: ASI Reference Design AN348: Interfacing DDR SDRAM with Cyclone Devices AN356: Serial Digital Interface Reference Design for Cyclone & Stratix Devices AN357: Error Detection Using CRC in Altera Devices Reference Design: Cyclone DDR I/O Reference Design White Paper: SRunner - An Embedded Solution for Serial Configuration Device Programming White Paper: Delivering RISC Processors in an FPGA for $2 Copyright © 2005 Altera Corporation 163 Learn More through Technical Training Instructor-Led Training On-Line Training with Altera's instructor-led training courses, you can: with Altera's on-line training courses, you can: Listen to a lecture from an Altera technical training engineer (instructor) Take a course at any time that is convenient for you Take a course from the comfort of your home or Complete hands-on exercises with guidance from an office (no need to travel as with instructor-led courses) Altera instructor Each on-line course will take approximately 2-3 hours to complete. Ask questions and receive real-time answers from an Altera instructor Each instructor-led class is one day in length (8 working hours). www.altera.com/training View Training Class Schedule & Register for a Class Copyright © 2005 Altera Corporation 164 谢谢 Copyright © 2005 Altera Corporation 165
