VCC: Function-Architecture Co-Design:
Modelling and Examples
EE 249: November 7, 2002
Grant Martin
Fellow, Cadence Berkeley Labs
With thanks to Frank Schirrmeister, Jean-Yves Brunel
and Paolo Giusto
CADENCE CONFIDENTIAL
Agenda
• System-level SoC Design – The Rise in Abstraction
• The VCC Design Flow as an example of Function-Architecture
Co-Design
• Performance Modeling
• Architectural Services
• Co-Design Example: Automotive Distributed SW
• Co-Design Example: Design Space Exploration of Multimedia
platform
Embedded System on Chip (SoC) Design
System
Environment
Zone 4: Global
Satellite
Zone 3: Suburban Zone 2: Urban
Zone 1: In-Building
Pico-Cell
Macro-Cell Micro-Cell
Requirements
Specification
Specification
Untimed,
Unclocked,
C/C++ Level
Memory
Implementation
Timed,
Clocked,
RTL Level
Software
Analog
SOC
Firmware
CORE
Implementation
P/C
µ
Embedded
Software
Characterization
Testbench
Refinement
Design Export
Embedded
Systems Design
How did we use abstraction in the past?
Step 1 – Layout to Transistor
Digital Abstraction
1970’s
• Switching delay of the transistor
• The design complexity exceeds what
designers can comprehend and think
through at the layout level
• Interconnect delay between transistors
• Transistor level simulation allows to verify
the logic of digital and analog designs
based on transistor switching
characteristics
abstract
Transistor Model
Capacity Load
1970’s
cluster
How did we use abstraction in the past?
Step 2 – Transistors to Gates
Digital Abstraction
 Gate delay
 Interconnect delay between gates
1980’s
 The design complexity exceeds what
designers can comprehend and
simulate at the transistor level
abstract
Transistor Model
Capacity Load
1970’s
abstract
Gate Level Model
Capacity Load
cluster
1980’s
cluster
 Gate level simulation allows to verify
the logic of digital designs based on
gate switching characteristics.
How did we use abstraction in the past?
Step 3 – Gates to RTL-HDL
Digital Abstraction
 Not really a abstraction of performance
(e.g. SDF only used for gate to layout
to gate)
abstract
Gate Level Model
Capacity Load
1980’s
abstract
 Textual statements result in “many
gates” after synthesis
RTL
cluster
1990’s
 The design complexity exceeds what
designers can comprehend and
simulate at the gate level alone
 HDL is first used for fast verification,
synthesis allows translation of text into
gates
 Synthesis algorithms map text to actual
registers and logic in between based on
characterized gate and wire-load
libraries
 Gate and wire-load delays are refined
after layout. SDF emerges as format
1990’s
And what is the next step?
IP Block Performance
Ports
DMAC
Modeling of Performance for IP Blocks
abstract
Transistor Model
Capacity Load
1970’s
abstract
SDF
Gate Level Model
Capacity Load
MPEG
Audio Decoder
uC
I/F
abstract
abstract
 … by attaching performance data to
timing free functional models
Register File
Timers
RTL
cluster
Graphics
Engine
On-Chip Ram
RTL
Clusters
cluster
cluster
1980’s
1990’s
Year 2000 +
And what is the next step?
Inter IP Communication Performance
abstract
Transistor Model
Capacity Load
1970’s
abstract
SDF
Gate Level Model
Capacity Load
abstract
abstract
Modeling of Performance for
Communication between IP Blocks
RTL
cluster
RTL
Clusters
cluster
cluster
1980’s
1990’s
Year 2000 +
And what is the next step?
IP Block Performance
Inter IP Communication Performance
Ports
DMAC
Apply this to Hardware and Software
1970’s
RTOS
MPEG
Audio Decoder
uC
I/F
abstract
abstract
abstract
Transistor Model
Capacity Load
abstract
SDF
Gate Level Model
Capacity Load
cluster
RTL
cluster
Driver
Graphics
Engine
On-Chip Ram
RTL
Clusters
1990’s
SW
Models
Discontinuity:
Embedded Software
cluster
1980’s
Tasks
Register File
Timers
Year 2000 +
The Platform-Based Design Concept
Taking Design Block Reuse to the Next Level
Pre-Qualified/Verified
Foundation-IP*
Foundation Block + Reference Design
MEM
Hardware IP
SW IP
Application
Space CPU
FPGA
Scaleable
bus, test, power, IO,
clock, timing architectures
Processor(s), RTOS(es)
and SW architecture
Methodology / Flows:
Programmable
System-level performance
evaluation environment
*IP can be hardware (digital
or analogue) or software.
IP can be hard, soft or
‘firm’ (HW), source or
object (SW)
Foundry-Specific
Pre-Qualification
Rapid Prototype for
End-Customer Evaluation
SoC Derivative Design
Methodologies
Foundry Targetting Flow
The Platform-Based Design Concept
Platform Type Examples
“Full Application
HW/SW Platform”
Examples:
–TI OMAP
–Philips nExperia,
–Infineon MGold
“Processor
Centric”
Examples:
– ARM Micropack
– ST100 Platform
– Improv Jazz
Improv JAZZ Platform
“Communication
Centric”
Examples:
–Palmchip
–Sonics
SONICs Architecture
DMA
SiliconBackplane™
(patented)
{
C
CPU
MEM
DSP
I
MPEG
O
System House Requirements
… exploring and developing on top of SoC
Platforms
Application Space
Platform Based Design Objectives
• Define the application instance to be
implemented to satisfy product
requirements defined by consumer
Platform
Specification
• Specify the system platform together
with suppliers accordingly
• Evaluate top down different instances
of SOC platforms
System Platform
Platform
Design Space
Exploration
Architectural Space
SOC Provider Requirements
… designing SoC Platforms and Sub-systems
Application Space
Platform Based Design Objectives
• Define the SOC platform instance so
that multiple instances of applications
can be mapped to the same system
platform
• Present this to system customers as
SOC Design-Kit and optimally
leverage economy of scale for SOC
platform instance
Platform
Design Space
Exploration
System Platform
Platform
Specification
• Provide bottom up instances of SOC
platform for evaluation without
disclosing the details of the IP
Architectural Space
The VCC Design Flow:
An example of Function-Architecture CoDesign
CADENCE CONFIDENTIAL
VCC Front End
Embedded System Requirements
Functional IP
C/C++
SDL
SPW
Simulink
Platform Function
Platform
Architecture
System Integration
Performance Analysis and
Platform Configuration
Architecture IP
CPU/DSP
RTOS
Bus, Memory
HW
SW
Platform
Configuration
… at the
un-clocked, timing-aware
system level
• Enabling communication within the SOC Design Chain
• Design Space Exploration with abstracted Performance Models
• Untimed Functional and Performance Verification
• Integration Platform Design, Optimization and Configuration
VCC Front End
Functional Integration and Analysis
Embedded System Requirements
Functional IP
C/C++
SDL
SPW
Simulink
Platform Function
Platform
Architecture
System Integration
Performance Analysis and
Platform Configuration
Architecture IP
CPU/DSP
RTOS
Bus, Memory
HW
SW
Platform
Configuration
… at the
un-clocked, timing-aware
system level
VCC Front End
Define Architectural Options and Configuration
Embedded System Requirements
Functional IP
C/C++
SDL
SPW
Simulink
Platform Function
Platform
Architecture
System Integration
Performance Analysis and
Platform Configuration
Architecture IP
CPU/DSP
RTOS
Bus, Memory
HW
SW
Platform
Configuration
… at the
un-clocked, timing-aware
system level
VCC Front End
Define Function Architecture Mapping
Embedded System Requirements
Functional IP
C/C++
SDL
SPW
Simulink
Platform Function
Platform
Architecture
System Integration
Performance Analysis and
Platform Configuration
Architecture IP
CPU/DSP
RTOS
Bus, Memory
HW
SW
Platform
Configuration
… at the
un-clocked, timing-aware
system level
VCC Front End
Run Performance Analysis for Platform
Configuration
Embedded System Requirements
Functional IP
Platform Function
C/C++
SDL
SPW
Simulink
Cache Results
Platform
Architecture
System Integration
Performance Analysis and
Platform Configuration
Processor Load
Architecture IP
CPU/DSP
RTOS
Bus, Memory
HW
SW
Platform
Configuration
… at the
un-clocked, timing-aware
system level
Process Gant Chart Analysis
VCC Backend
• Linking System Level Design to Implementation
– Fast track to prototyping
– Fast track to software development
– Design consistency through the design flow
Communication
Refinement, Integration & Synthesis
Hardware
Assembly
Software
Assembly
Implementation Level Verification
Synthesis / Place & Route etc.
Design Export
… after initial platform
configuration through
design refinement and
communication synthesis
VCC Backend
Communication Refinement and Synthesis
Communication
Refinement
Communication
Synthesis
VCC Model
VCC Model to RTOS
Protocol Component
Abstract
Token
Abstract
Token
Communication
Refinement, Integration & Synthesis
Hardware
Assembly
Software
Assembly
Implementation Level Verification
Synthesis / Place & Route etc.
RTOS
VCC Model
RTOS to CPU
Protocol Component
Bus Slave to VCC
Model Component
CPU
Bus Slave
CPU to Bus Protocol
Component
Bus to Bus Slave
Component
Bus
Bus
Bus Model
Design Export
… after initial platform
configuration through
design refinement and
communication synthesis
VCC Backend
Export to Implementation (Design and Test Bench)
VCC
System Exploration
Communication Refinement
Flow To Implementation
Hardware
Top-level
System
Test Bench
Software
on RTOS
Communication
Refinement, Integration & Synthesis
Hardware
Assembly
Software
Assembly
Implementation Level Verification
Synthesis / Place & Route etc.
Design Export
… after initial platform
configuration through
design refinement and
communication synthesis
VCC Flow Summary
Embedded System Requirements
Functional IP
C/C++
SDL
SPW
Simulink
Platform Function
Platform
Architecture
System Integration
Performance Analysis and
Platform Configuration
Communication
Refinement, Integration & Synthesis
Hardware
Assembly
Software
Assembly
Implementation Level Verification
Synthesis / Place & Route etc.
Architecture IP
CPU/DSP
RTOS
Bus, Memory
HW
SW
Platform
Configuration
… at the
un-clocked, timing-aware
system level
Design Export
… after initial platform
configuration through
design refinement and
communication synthesis
Performance Modeling
… using Abstraction
CADENCE CONFIDENTIAL
Functional Simulation
Gate Level
Functional Simulation
Function
A
0
0
1
1
B OUT
0
1
1
0
0
0
1
0
• Gate switching defines functionality
• Combination of gate functionality
defines “functionality” of the design
• Simulation slow in complex systems
as huge amounts of events are to be
processed
Functional Simulation
Using VCC at the System-Level
Functional Simulation
• Function of system blocks executed
SPW
StateCharts
– General Descriptions
– C, C++, State Charts, OMI
– Application specific
SDL
– SPW, Telelogic SDL, Matlab
Simulink, ETAS Ascet
Simulink
A
0
0
1
1
Functio
n
B OUT
0
1
1
0
0
0
1
0
C++
C
• Functional execution defined as “fire
and return” with a OMI 4.0 compliant
discrete event simulation
infrastructure
• Simulation is as fast as the abstract,
un-timed models simulate
Performance Simulation
Gate Level
Functional Simulation
• Gate switching functionality
Function
A
0
0
1
1
B OUT
0
1
1
0
0
0
1
0
Performance
Dt
Performance Simulation
SDF and
Gate Level
Library
• functionality annotated with intrinsic
gate delay
• interconnect delay modeled from
capacity
Performance
InterConnect
Capacity
Refinement
• SDF data is refined after layout is
carried out
VCC Performance Simulation
System-Level Block Performance Modeling
Performance Simulation
Performance
• functionality annotated with intrinsic
delay models
• Delay Script and Inline Models,
refined after implementation
Interleaver
Dt
IP Functional Model
A
0
0
1
1
Functio
n
B OUT
0
1
1
0
0
0
1
0
Performance
Scripted
Delay
Model
Forward Error Correction
FEC() {
f = x.read();
// FEC function here
y.write(r);
}
Inline
Delay
Model
Dt
IP Functional Model
Forward Error Correction
FEC on CPU
FEC in slow HW
FEC() {
// FEC_ip_implem
f = x.read();
FEC in fast HW
delay()
{
// FEC_ip_implem
// FEC function here
input(x);
delay() Delay
{
Script
y.write(r);
run();input(x);
// FEC_ip_implem
}
delay(200*cps);
run();delay() {
output(y);
delay(128*cps);
input(x);
}
output(y);
run();
}
delay(64*cps);
output(y);
}
Annotated
IP Functional Model
FEC() {
f = x.read();
// FEC function part A here
__DelayCycles(60*cps);
// FEC function part B here
__DelayCycles(78*cps);
// FEC function part C here
__DelayCycles(23*cps);
y.write(r);
}
VCC Performance Simulation
System Level Block Interconnect Performance
Modeling
Post() from Behavior 1
Sender
Value()/Enable() from Behavior 2
Shared Memory
Communication Pattern
Receiver
RTOS
Standard C
Library
CPU
A
0
0
1
1
Functio
n
B OUT
0
1
1
0
0
0
1
0
Pattern Services
Memory
Access
InterConnect
Capacity
Memory
CPU
Port
Architecture Services
Performanc
e
RAM
Bus Adapter
RAM
Port
Slave
Adapter
ASIC
Port
Bus Adapter
Bus
Bus Arbiter
VCC Performance Simulation
Enabled through Architecture Services in VCC
A
B
Post(5)
Value()
Semaphore
Protected
SemProt_Send
SemProt_Recv
SemProt_Send
mutex_lock;
memcpy;
setEnabled
wait;
memcpy;
signal
signal
User Visible
RTOS
SwMutexes
write
MemoryAccess
BusMaster
Pattern Services
read
Architecture Services
CPU
Mem
SlaveAdapter
busRequest
BusArbiter
arbiterRequest/Release
busIndication
busIndication
VCC Performance Modeling …
… the System Level extension of SDF
Classical Gate Level Technology
Function
A
0
0
1
1
B OUT
0
1
1
0
0
0
1
0
VCC System Level Technology
IP Block
Performance
Performance
Dt
SDF and
Gate Level
Library
Function
C, C++,
SPW, SDL,
Simulink,
Statecharts
Performance
System
Level Library
Interleaver
Dt
SPW
Interconnect
Performance
InterConnect
Capacity
StateCharts
IP Block
Interconnect
Performance
SDL
Simulink
C++
C
How to get the performance numbers…
IP Block Performance Modeling
Top Down Flow
• In a pure top down design flow the
performance models are “Design
Requirements” for functional models
• They are refined using bottom up
techniques in due course throughout
the project
Bottom Up Flow
• SOC Provider characterizes IP
portfolio, e.g. of a Integration
platform
– using HDL model simulation
– using software simulation on ISS
– using benchmarking on SOC
IP Functional Model
Scripted
Delay
Model
Forward Error Correction
FEC() {
f = x.read();
// FEC function here
y.write(r);
}
IP Functional Model
Forward Error Correction
FEC on CPU
FEC in slow HW
FEC() {
// FEC_ip_implem
f = x.read();
FEC in fast HW
// {FEC_ip_implem
// FECdelay()
function
here
input(x);
delay() {Delay Script
y.write(r);
run(); input(x);
}
// FEC_ip_implem
delay(200*cps);
run(); delay() {
output(y);
delay(128*cps);
input(x);
}
output(y);
run();
}
delay(64*cps);
output(y);
}
Inline
Delay
Model
Annotated
IP Functional Model
FEC() {
f = x.read();
// FEC function part A here
__DelayCycles(60*cps);
// FEC function part B here
__DelayCycles(78*cps);
// FEC function part C here
__DelayCycles(23*cps);
y.write(r);
}
How to get the performance numbers…
IP Block Interconnect Performance Modeling
Top Down Flow
• Datasheets for architectural IP
information are entered in
parameters for architectural services
• Can be done fast by System
Integrator without SOC Provider
• Refinement with SOC Provider
models
Bottom Up Flows
• Architectural IP is profiled using
HDL simulation, ISS or silicon and
data is entered in VCC architectural
services
Value()/Enable() from Behavior 2
Post() from Behavior 1
Shared Memory
Communication Pattern
Sender
Receiver
RTOS
Standard C
Library
CPU
Memory
Access
RAM
Memory
CPU
Port
Bus Adapter
RAM
Port
Slave
Adapter
ASIC
Port
Bus Adapter
Bus
Bus Arbiter
Pattern Services
Architecture Services
How to get the performance numbers…
Software Estimation for ANSI C code (“Whitebox C”)
• Estimation of software performance prior to implementation
• CPU characterized as Virtual Processor Model
– Using a Virtual Machine Instruction Set
– Used for dynamic control SW estimation during performance simulation taking into
account bus loading, memory fetching, and register allocation
• Value
– True co-design: SW estimation using annotation into C Code (as opposed to to
simulation in instruction simulators used in co-verification)
– Good for early system scheduling, processor load estimation
– Two orders of magnitude faster than ISS
– Greater than 80 percent accuracy
– Enables pre-implementation decision but is not a verification model
How to get the performance numbers…
Virtual Processor Model Characterization Methods
Data Book Approach
– CPU data book information to count cycles and estimate VIM
Calibration Suite using “Best Fit”
– Run Calibration Suite on VIM and ISS
– Solve a set of linear equations to minimize difference
Application Specific Calibration Suite
– using the “Best Fit” method but use application specific routines for automotive,
wireless telecom, multimedia etc.
Exact Count on ISS
– cycle counts exactly derived from ISS run
– Filter specific commands out (e.g. OPi etc.)
How to get the performance numbers…
Software Estimation for ANSI C code (“Whitebox C”)
Virtual Machine
Instruction Set Model
LD,3.0
LI,1.0
ST,3.0
OP.c,3.0
OP.s,3.0
OP.i,4.0
OP.l,4.0
OP.f,4.0
OP.d,6.0
MUL.c,9.0
MUL.s,10.0
MUL.i,18.0
MUL.l,22.0
MUL.f,45.0
MUL.d,55.0
DIV.c,19.0
DIV.s,110.0
DIV.i,118.0
DIV.l,122.0
DIV.f,145.0
DIV.d,155.0
IF,5.0
GOTO,2.0
SUB,19.0
RET,21.0
Load from Data Memory
Load from Instr. Mem.
Store to Data Memory
Simple ALU Operation
Complex ALU Operation
Test and Branch
Unconditional Branch
Branch to Subroutine
Return from Subroutine
How to get the performance numbers…
Software Estimation for ANSI C code (“Whitebox C”)
ANSI C
Input
char *event;
int proc;
if (*(event+proc) & 0x1: 0x0)
...
Assembler
ld
ld
add
ld
ldi
and
cmp
br
ba

Whitebox C
declare ports
tmp=b+c
c=f(d)
MT update D1

Compile
generated C and
run natively
Performance
Estimation
#event,R1
#proc,R2
R1,R2,R3
(R3),R4
#0x1, R5
R4, R5, R6
R0, R6, R7
R7, LTRUE
LFALSE
tmp
r=(s<<*a)
a=r+m*x
y=a*c+b
MT update D2+D3
write B y

Analyse
ld
ld
op
ld
li
op
ts
-br
basic blocks
compute delays

D1
Generate new C
!tmp
with delay counts
Architecture
Characterization
D2
D3
Virtual
Processor
Model
f6(y)
MT update D4
return
D4
Architectural Services Example
CADENCE CONFIDENTIAL
Architecture Service
• The service is the element that defines the functionality of an
architecture
• A service is coded in C++ and performs a specific role to model
architecture, for example:
– bus arbitration
– memory access
– interrupt propagation
– etc.
Example of Services
ASIC
Behavior
Post
Pattern
Sender
Bus
BusMaster
BusArbiter
Mem
BusSlave
Memory
Example of Services
• Behavior calls Post, i.e., send a communication
• Pattern hears Post and directs ASIC block’s BusMaster to send
a communication
• BusMaster asks the Bus Block’s BusArbiter for use of the bus
• BusArbiter grants the bus, so communication can go to Memory
Block
• Memory Block’s BusSlave receives communication and forwards
to memory
• Memory stores communication.
Categories of Services
• Pattern Service
– services that coordinate the communication of architecture services
• Architecture Service
– services that define the functionality of architecture
• Internal Service
– generic, default service used during functional simulation
Pattern Service
• A pattern coordinates architectural services that collectively model a
communication path from sender to receiver
• Patterns are composed of a sender service and a receiver service
– Sender service defines Post
– Receiver service defines Enabled/Value
Post
Pattern
Sender
Enabled/ Pattern
Value Receiver
• Both the sender and receiver service direct the actions of architecture
services to send/receive communication
Basic Example
• Let’s assume two behaviors.
• b1 and b2 talk to each other:
– b1 says Post; b2 says Value
– and visa versa
Basic Example (cont)
• What does it mean for b1 to talk to b2?
• What does it mean for b1 to say Post?
• What does it mean for b2 to say Value?
• We should consider an architecture to give meaning to b1 and
b2.
• We should consider how the behavior blocks map to the
architecture.
Basic Example (cont)
• Let’s assume the following architecture:
Basic Example (cont)
• Here we map the behavior to the architecture:
Basic Example (cont)
• What do we see in the mapping diagram?
– b1 is mapped to software.
– b2 is mapped to hardware.
– b1 to b2 communication is set to Shared Memory.
– b2 to b1 communication is set to to Interrupt Register Mapped.
• For simplicity’s sake, we’re focusing on b1-to-b2 communication.
– b2 to b1 will be ignored for now.
• If b1 talks to b2, how does that look when mapped to an architecture?
– What happens when b1 says Post?
– What happens when b2 says Value?
– Note b1 to b2 is shared memory communication.
Basic Example (cont)
• Using Shared Memory, we have the
following sequence of communication:
1. b1 writes to memory:
b1  RTOS  CPU  Bus  Mem
2. b2 reads from memory:
b2  ASIC  Bus  Mem
Basic Example (cont)
• So b1 talks to b2 through the various architecture components:
– b1 says Post and that becomes a write to memory.
– b2 says Value and that becomes a read from memory.
• What is the underlying mechanism that propagates Post/Value
through the architecture?
– It’s something called the “service”.
Commercial Example
ST Microelectronics
IP models support codesign efforts
By
Benoit Clement
System-Level Design Engineer
Doha Benjelloun
System-Level Design Engineer
Co-Design Methodology for Systems &Architecture (CMSA)
STMicroelectronics, Grenoble, France
http://www.eetimes.com/story/OEG20010913S0069
Example of Co-Design – Distributed
Automotive SW
CADENCE CONFIDENTIAL
Distributed Automotive Applications over networks –
“Software-Software Codesign”
• Electronic Control Units
(ECU’s)
• Standard buses (TTP, CAN,
FlexRay)
• Standard Platforms
Current Design Practices
Requirements
Matlab
Engine Control
f1
ASCET
f3
Gear-Box Control
f2
specification
“zero time assumption”
f4
ECU-1
ECU-2
CAN/TTP-bus
ECU-3
.c
.c
analysis
“functional network”
.c ... Architecture
system design
“real world assumption”
implementation
“automatic target code gen.”
integration & calibration
“step into a real car”
production & after sales
“handling at the garage”
• Integration is done too late In the car
• Tools are PER-ECU – conservative, costly, no tradeoffs
Virtual Integration Platform for
Distributed Automotive Applications
Development Process
IP’s
Software Components
C-Code
Matlab
C++
Architectural Models
Buses Buses
CPUs
Buses Operating
Systems
Analysis
System Behavior
Specification
ASCET
Implementation
ASCET
Calibration
f1
System Architecture
f2
f3
Mapping
Performance
Simulation
Refinement
After Sales Service
Evaluation of
Architectural
and
Partitioning
Alternatives
Scenarios for SW-driven co-development
f f
f f f
??
f
f
f
f
??
f f
f
f
f
f
f
f
f
??
f
f f
f
f
f
f
f
f
ASCET-SD imported project in VCC
Message1
Message2
Message3
Message4
Interrupt
IntrptReceiveTask1
These are behavioral memories
HW_Intrpt1
TestBench
These are behavioral
HWIntrpt
memories
HW_Intrpt2
GlobalVariable
HWIntrp
HWIntrpt1
Timer10msec
ProjectA
SWIntrpt
HWIntrpt2
ReceiveSendTask1
Interrupt
IntrptSendTask1
ReceiveSendTask5
ReceiveSendTask3
The test-bench can include Matlab imported models
This is the ASCET imported Project
as well as VCC authored models
SW_Interrupt1
HWIntrpt1
Timer20ms
SW_Interrupt1
HW_Interrupt1
Module0
Module2
ReceiveSendTask6
Process8
SW_Interrupt2 SW_Interrupt2
SW_Interrupt
Timer30ms
HWIntrpt2
HW_Interrupt
SW_Interrupt
Module1
These are the modules
of the ASCET project
These are the processes
for the protected
variables
HW_Interrupt
Process9
GlobalVariable2
These are behavioral
timers
HWIntrpt
SWIntrpt
ReceiveSendTask7
ReceiveSendTas
ReceiveSendTask4
Process10
Universal Communications
Model of Bus
Behavioral Diagram
Behavioral
Memory 1
Module A
Module B
ECU 1
RTOS
ECU 1
RTOS
PPC
internal bus
Mem
Bus
Controller
Architectural
Bus Memory
Peak
Load
Broadcast Bus
PPC
internal bus
Mem
Bus
Controller
Example Design Flow (1): Power
Window
• Definition of a behavioral diagram: Import of functional components (software
projects and modules)
BrakeSwitchFil
Timer
BTSetUp
Manipulator
AquireSignal
BrakeOutFL
BrakeOutFR
PedalSensor1Fil
Base Brake & ABS
AquireSignal
Manipulator
PedalSensor2Fil
BrakeOutRL
AquireSignal
PedalSensor3Fil
Manipulator
AquireSignal
BrakeOutRR
HandBrakeSwitchFil
Manipulator
AquireSignal
ClampForceFLFil
AquireSignal
ClampForceFRFil
AquireSignal
ClampForceRLFil
AquireSignal
Base Steering
ClampForceRRFil
SteeringOut1
Manipulator
AquireSignal
SteeringOut2
Manipulator
SteeringWheelAngle1Fil
AquireSignal
BrakeSwitch
SteeringWheelAngle2Fil
AquireSignal
PedalSensor1
SteeringWheelAngle3Fil
PedalSensor2
AquireSignal
Uniform
Pulses
Uniform
Pulses
Uniform
Pulses
PedalSensor3
SteeringWheelAngle4Fil
AquireSignal
HandBrakeSwitch
ClampForceFL
RackPosition1Fil
AquireSignal
ClampForceFR
Handwheel
Feedback
RackPosition2Fil
ClampForceRL
AquireSignal
Trigger
ClampForceRR
SteeringWheelTorqueOut1
Manipulator
BrakeActuator
RackPosition3Fil
BrakeActuatorOut
AquireSignal
SteeringWheelAngle1
SteeringWheelTorqueOut2
Trigger
Manipulator
RackPosition4Fil
SteeringWheelAngle2
Trigger
AquireSignal
BrakeActuator
SteeringWheelAngle3
BrakeActuatorOut
DbW_TopBlock
SteeringWheelAngle4
Trigger
DriverSteer
DriverSteer
Driver
DriverBrake
DriverBrake
DriverGas
DriverGas
DriverClutch
Trigger
2 Track
Vehicle
Model
RackPosition1
AquireSignal
BrakeActuatorOut
RackPosition2
SteeringWheelTorque2Fil
AquireSignal
RackPosition3
Master1BrakeFL
Trigger
DriverClutch
SteeringWheelTorque1Fil
BrakeActuator
RackPosition4
SteeringWheelTorque3Fil
BrakeActuator
AquireSignal
Master1BrakeFR
BrakeActuatorOut
DriverGear
DriverGear
SteeringWheelTorque1
Master1BrakeRL
SteeringWheelTorque2
Trigger
Master1BrakeRR
TieRodForce1Fil
SteerActuator
SteeringWheelTorque3
SteerActuatorOut
AquireSignal
Master1SteeringAngleOut
TieRodForce2Fil
TieRodForce1
AquireSignal
Trigger
BrakeActuatorFR
SteerActuator
TieRodForce2
Master
Controller
Master1SteeringTorqueOut
SteerActuatorOut
TieRodForce3Fil
BrakeActuatorFL
vel_veh_master_1
AquireSignal
TieRodForce3
BrakeActuatorRL
Master1Warning
SpeedFL
BrakeActuatorRR
HandWheelTorqueActuator
BrakeDiagnosis
SpeedFLFil
SteeringActuator2
SpeedFR
AquireSignal
HandWheelTorqueActuator
SteeringActuator1
SpeedRL
Master2BrakeFL
SpeedFRFil
AquireSignal
SpeedRR
Master2BrakeFR
SteeringDiagnosis
SpeedRLFil
WarningLightYellow
YawRate
AquireSignal
LateralAcceleration
SpeedRRFil
WarningLightYellow
AquireSignal
Master
Controller
Master2BrakeRL
Master2BrakeRR
Master2SteeringAngleOut
HWFeedbackDiagnosis
CurrentBatterie1
Uniform
Pulses
WarningLightRed
YawRateFil
VoltageBatterie1
Trigger
Master2SteeringTorqueOut
AquireSignal
vel_veh_master_2
WarningLightRed
BordnetStimulator
CurrentBatterie2
LateralAccelerationFil
AquireSignal
Master2Warning
VoltageBatterie2
CurrentAlternator
VoltageAlternator
CurrentBatterie1Fil
AquireSignal
Diagnosis
Battery1Diagnosis
VoltageBatterie1Fil
ComputePowerManagement
AquireSignal
CurrentBatterie2Fil
AquireSignal
Battery2Diagnosis
ComputePowerManagement
AquireSignal
VoltageBatterie2Fil
Diagnosis
CurrentAlternatorFil
AquireSignal
AlternatorDiagnosis
ComputePowerManagement
VoltageAlternatorFil
AquireSignal
Design Flow (2)
• Generation of an ideal communication between the functional components
– No delay or error handling considered.
– Functional co-verification
Design Flow (3)
• Creation of an architectural diagram in VCC
PPC
RTOS
TTPController
PPC_TTP
PPC
RTOS
TTPController
Channel1
PPC_TTP
Channel2
PPC
RTOS
TTPController
Channel1
PPC_TTP
Channel2
PPC
RTOS
TTPController
Channel1
PPC_TTP
Channel2
PPC
RTOS
TTPController
Channel1
PPC_TTP
Channel2
PPC
RTOS
TTPController
Channel1
PPC_TTP
Channel2
TTPController
PPC_TTP
Channel1
Channel1
PPC_TTP
Channel2
RTOS
PPC
TTPController
Channel1
PPC_TTP
Channel2
RTOS
PPC
TTPController
Channel1
PPC_TTP
Channel2
RTOS
PPC
TTPController
Channel1
PPC_TTP
Channel2
RTOS
PPC
TTPController
Channel1
PPC_TTP
Channel2
RTOS
PPC
TTPController
Channel1
Channel2
RTOS
Channel1
Channel2
Channel2
TTP Channel 2
PPC_TTP
PPC
RTOS
PPC
TTPController
Design Flow (4)
• Mapping the software modules onto the ECU
– Either retaining the original per-ecu mapping from ASCET-SD or creating a new one
BrakeSwitch
PedalSensor1
PedalSensor2
Uniform
Pulses
Uniform
Pulses
Uniform
Pulses
PedalSensor3
Timer
Timer
Timer
BTSetUp
BTSetUp
BTSetUp
HandBrakeSwitch
ClampForceFL
ClampForceFR
force_clp_f_base_des
force_clp_f_base_des
force_clp_f_base_des
ClampForceRL
ComputeBrakeCommand
ComputeBrakeCommand
ComputeBrakeCommand
Trigger
ClampForceRR
BrakeActuator
BrakeActuatorOut
force_clp_r_base_des
force_clp_r_base_des
force_clp_r_base_des
SteeringWheelAngle1
DiagnosisBrakePedal
Trigger
DiagnosisBrakePedal
DiagnosisBrakePedal
long_acc_veh_des
long_acc_veh_des
long_acc_veh_des
SteeringWheelAngle2
Trigger
BrakeActuator
SteeringWheelAngle3
BrakeActuatorOut
DbW_TopBlock
force_clp_fl_ABS_des
force_clp_fl_ABS_des
force_clp_fl_ABS_des
SteeringWheelAngle4
Arbiter_Br
Arbiter_Br
Arbiter_Br
Trigger
DriverSteer
DriverSteer
Driver
DriverBrake
DriverBrake
DriverGas
DriverGas
DriverClutch
Trigger
2 Track
Vehicle
Model
RackPosition1
BrakeActuator
force_clp_fr_ABS_des
BrakeActuatorOut
force_clp_fr_ABS_des
force_clp_fr_ABS_des
RackPosition2
Comp_Cmd_ABS_Br
Comp_Cmd_ABS_Br
Comp_Cmd_ABS_Br
RackPosition3
force_clp_rl_ABS_des
force_clp_rl_ABS_des
force_clp_rl_ABS_des
Trigger
DriverClutch
BrakeActuator
RackPosition4
BrakeActuatorOut
DriverGear
DriverGear
SteeringWheelTorque1
force_clp_rr_ABS_des
force_clp_rr_ABS_des
force_clp_rr_ABS_des
SteeringWheelTorque2
Trigger
SteerActuator
SteeringWheelTorque3
SteerActuatorOut
TieRodForce1
Timer
BTSetUp
Trigger
BrakeActuatorFR
SteerActuator
TieRodForce2
Timer
BTSetUp
SteerActuatorOut
BrakeOutFL_channel1
BrakeActuatorFL
TieRodForce3
Base Brake & ABS one
channel
BrakeActuatorRL
SpeedFL
BrakeActuatorRR
HandWheelTorqueActuator
SteeringActuator2
BrakeOutFR_channel1
BrakeOutRL_channel1
Vote Brake Comand
SpeedFR
force_clp_f_base_des
HandWheelTorqueActuator
SteeringActuator1
BrakeOutRR_channel1
SpeedRL
ComputeBrakeCommand
SpeedRR
force_clp_r_base_des
WarningLightYellow
BrakeOutFL_channel2
YawRate
DiagnosisBrakePedal
Base Brake & ABS one
channel
LateralAcceleration
WarningLightYellow
long_acc_veh_des
BrakeOutFR_channel2
Vote Brake Comand
BrakeOutRL_channel2
force_clp_fl_ABS_des
CurrentBatterie1
Arbiter_Br
Uniform
Pulses
WarningLightRed
BrakeOutRR_channel2
VoltageBatterie1
Trigger
force_clp_fr_ABS_des
WarningLightRed
BordnetStimulator
CurrentBatterie2
Comp_Cmd_ABS_Br
BrakeOutFL_channel3
VoltageBatterie2
force_clp_rl_ABS_des
Base Brake & ABS one
channel
CurrentAlternator
VoltageAlternator
BrakeOutFR_channel3
Vote Brake Comand
force_clp_rr_ABS_des
BrakeOutRL_channel3
BrakeOutRR_channel3
Timer
BTSetUp
BrakeOutFL_channel4
BrakeSwitchFil
Timer
BTSetUp
Base Brake & ABS one
channel
Manipulator
AquireSignal
BrakeOutFL
BrakeOutFR_channel4
Vote Brake Comand
BrakeOutRL_channel4
VotedSteeringWheelAngle
Diagnosis_Lateral_Sensors
BrakeOutRR_channel4
ComputeSteeringCommand
VotedRackPosition
BrakeOutFR
PedalSensor1Fil
Base Brake & ABS
AquireSignal
Manipulator
PedalSensor2Fil
BrakeOutRL
AquireSignal
Timer
BTSetUp
Timer
PedalSensor3Fil
Manipulator
AquireSignal
BTSetUp
Base Steering one
channel
BrakeOutRR
HandBrakeSwitchFil
SteeringActuatorOut_channel1
Manipulator
AquireSignal
VotedSteeringWheelAngle
Diagnosis_Lateral_Sensors
ComputeSteeringCommand
ClampForceFLFil
VotedRackPosition
AquireSignal
ClampForceFRFil
Base Steering one
channel
AquireSignal
ClampForceRLFil
SteeringActuatorOut_channel2
Timer
Vote_Cmp_Rack_Act
BTSetUp
AquireSignal
Base Steering
ClampForceRRFil
SteeringOut1
Manipulator
AquireSignal
VotedSteeringWheelAngle
SteeringOut2
Manipulator
SteeringWheelAngle1Fil
Diagnosis_Lateral_Sensors
Base Steering one
channel
AquireSignal
SteeringWheelAngle2Fil
ComputeSteeringCommand
SteeringActuatorOut_channel3
VotedRackPosition
AquireSignal
SteeringWheelAngle3Fil
AquireSignal
Vote_Cmp_Rack_Act
Timer
BTSetUp
SteeringWheelAngle4Fil
AquireSignal
Base Steering one
channel
RackPosition1Fil
AquireSignal
Handwheel
Feedback
RackPosition2Fil
AquireSignal
SteeringActuatorOut_channel4
VotedSteeringWheelAngle
SteeringWheelTorqueOut1
Diagnosis_Lateral_Sensors
Manipulator
ComputeSteeringCommand
VotedRackPosition
RackPosition3Fil
AquireSignal
SteeringWheelTorqueOut2
Timer
Manipulator
BTSetUp
RackPosition4Fil
Timer
BTSetUp
AquireSignal
AquireSignal
SteeringWheelTorque1Fil
Handwheel
Feedback one
channel
SteeringWheelTorque2Fil
AquireSignal
Master1BrakeFL
SteeringWheelTorque3Fil
AquireSignal
SteeringWheelTorqueOut_channel1
VotedSteeringWheelTorque
Diagnosis Feedback Sensors
ComputeSteeringTorqueCommand
Master1BrakeFR
VotedTieRodForce
Vote HW Feedback
Master1BrakeRL
Handwheel
Feedback one
channel
Master1BrakeRR
TieRodForce1Fil
AquireSignal
Master1SteeringAngleOut
TieRodForce2Fil
AquireSignal
Master
Controller
TieRodForce3Fil
SteeringWheelTorqueOut_channel2
Timer
BTSetUp
Master1SteeringTorqueOut
Vote HW Feedback
vel_veh_master_1
AquireSignal
Handwheel
Feedback one
channel
Master1Warning
BrakeDiagnosis
SpeedFLFil
AquireSignal
SteeringWheelTorqueOut_channel3
VotedSteeringWheelTorque
Master2BrakeFL
SpeedFRFil
Diagnosis Feedback Sensors
AquireSignal
ComputeSteeringTorqueCommand
Master2BrakeFR
VotedTieRodForce
SteeringDiagnosis
SpeedRLFil
AquireSignal
SpeedRRFil
AquireSignal
Master
Controller
Master2BrakeRL
Master2BrakeRR
Master2SteeringAngleOut
HWFeedbackDiagnosis
Timer
BTSetUp
YawRateFil
Master2SteeringTorqueOut
AquireSignal
vel_veh_master_2
LateralAccelerationFil
AquireSignal
Master2Warning
Cyclo
Static
Scheduler
CurrentBatterie1Fil
AquireSignal
Cyclo
Static
Scheduler
Cyclo
Static
Scheduler
Static
Priority
Scheduler
Static
Priority
Scheduler
Cyclo
Static
Scheduler
ComputePowerManagement
Cyclo
Static
Scheduler
Cyclo
Static
Scheduler
Static
Priority
Scheduler
Diagnosis
Battery1Diagnosis
VoltageBatterie1Fil
Cyclo
Static
Scheduler
Static
Priority
Scheduler
Cyclo
Static
Scheduler
Cyclo
Static
Scheduler
VotedSteeringWheelTorque
Static
Priority
Scheduler
Cyclo
Static
Scheduler
Static
Priority
Scheduler
Cyclo
Static
Scheduler
Cyclo
Static
Scheduler
ComputeSteeringTorqueCommand
CurrentBatterie2Fil
InterruptBus
AquireSignal
InterruptBus
Simple
ASIC
Battery2Diagnosis
InterruptBus
DataBus
InternalDataBus
InterruptBus
Simple
ASIC
CPU
InterruptBus
InterruptBus
InterruptBus
InternalDataBus
DataBus
Simple
ASIC
CPU
DataBus
InternalDataBus
CPU
Simple
ASIC
InterruptBus
InterruptBus
InternalDataBus
DataBus
CPU
Simple
ASIC
InterruptBus
InternalDataBus
DataBus
CPU
InterruptBus
Simple
ASIC
InterruptBus
InternalDataBus
ComputePowerManagement
ExternalBus
ExternalBus
AquireSignal
ExternalBus
ExternalBus
ExternalBus
ExternalBus
VoltageBatterie2Fil
Diagnosis
CurrentAlternatorFil
AquireSignal
ExternalBusPort
ExternalBusPort
ExternalBusPort
ExternalBusPort
ExternalBusPort
ExternalBusPort
AlternatorDiagnosis
ComputePowerManagement
VoltageAlternatorFil
AquireSignal
ECU_2Tasks_1BusCha
ECU_2Tasks_1BusCha
ExternalBusPort
ECU_2Tasks_1BusCha
Cyclo
Static
Scheduler
Static
Priority
Scheduler
Cyclo
Static
Scheduler
InterruptBus
InterruptBus
Cyclo
Static
Scheduler
InterruptBus
InternalDataBus
ExternalBus
DataBus
CPU
Simple
ASIC
ECU_2Tasks_1BusChan
ExternalBusPort
ECU_2Tasks_1BusChan
ExternalBusPort
ExternalBusPort
Cyclo
Static
Scheduler
Static
Priority
Scheduler
InternalDataBus
DataBus
Static
Priority
Scheduler
Cyclo
Static
Scheduler
InterruptBus
Cyclo
Static
Scheduler
InterruptBus
InterruptBus
InterruptBus
InterruptBus
CPU
Simple
ASIC
InternalDataBus
DataBus
CPU
Simple
ASIC
InternalDataBus
DataBus
CPU
Simple
ASIC
InternalDataBus
ExternalBus
ExternalBus
ExternalBusPort
ExternalBusPort
InterruptBus
InterruptBus
Simple
ASIC
ECU_2Tasks_1BusChan
ExternalBusPort
Cyclo
Static
Scheduler
Static
Priority
Scheduler
Cyclo
Static
Scheduler
ECU_2Tasks_1BusChan
ExternalBusPort
ECU_2Tasks_1BusChan
ExternalBusPort
Cyclo
Static
Scheduler
Static
Priority
Scheduler
ECU_2Tasks_1BusChan
ExternalBusPort
ECU_2Tasks_1BusCha
ExternalBusPort
Cyclo
Static
Scheduler
ECU_2Tasks_1BusChan
ExternalBusPort
ExternalBus
ExternalBus
ExternalBusPort
ExternalBusPort
ExternalBusPort
ExternalBusPort
DataBus
CPU
Diagnosis Feedback Sensors
VotedTieRodForce
AquireSignal
DataBus
CPU
Design Flow(5)
• Generation of the CPU scheduling
– Either manually or automatically in case the original scheduling is preserved
Hierarchical
Scheduler
Single
Task
Scheduler
Single
Task
Scheduler
Single
Task
Scheduler
Parent
Scheduler
Design Flow (6)
• Computation Performance Simulation
– No communication performance estimation
– Co-verification of Computational Resource ‘fit’
Design Flow(7)
• Design iterations
– Re-distribution of the functionality and tuning of the scheduling
BrakeSwitch
PedalSensor1
PedalSensor2
Uniform
Pulses
Uniform
Pulses
Uniform
Pulses
PedalSensor3
Timer
Timer
Timer
BTSetUp
BTSetUp
BTSetUp
HandBrakeSwitch
ClampForceFL
ClampForceFR
C
h
an
ne
l1
h
an
n
el
2
ClampForceRL
l
ClampForceRR
ha
nn
el
2
Trigger
BrakeActuator
h
an
ne
l1
BrakeActuatorOut
SteeringWheelAngle1
ha
nn
el
1
force_clp_f_base_des
ComputeBrakeCommand
force_clp_r_base_des
force_clp_f_base_des
force_clp_f_base_des
ComputeBrakeCommand
ComputeBrakeCommand
force_clp_r_base_des
force_clp_r_base_des
DiagnosisBrakePedal
Trigger
DiagnosisBrakePedal
DiagnosisBrakePedal
long_acc_veh_des
long_acc_veh_des
long_acc_veh_des
SteeringWheelAngle2
Trigger
BrakeActuator
SteeringWheelAngle3
BrakeActuatorOut
DbW_TopBlock
force_clp_fl_ABS_des
force_clp_fl_ABS_des
force_clp_fl_ABS_des
SteeringWheelAngle4
Arbiter_Br
Arbiter_Br
Arbiter_Br
Trigger
DriverSteer
Trigger
DriverSteer
Driver
2 Track
Vehicle
Model
DriverBrake
DriverBrake
DriverGas
DriverGas
DriverClutch
RackPosition1
BrakeActuator
force_clp_fr_ABS_des
BrakeActuatorOut
force_clp_fr_ABS_des
force_clp_fr_ABS_des
RackPosition2
Comp_Cmd_ABS_Br
Comp_Cmd_ABS_Br
Comp_Cmd_ABS_Br
RackPosition3
force_clp_rl_ABS_des
force_clp_rl_ABS_des
force_clp_rl_ABS_des
Trigger
DriverClutch
BrakeActuator
RackPosition4
BrakeActuatorOut
DriverGear
DriverGear
SteeringWheelTorque1
force_clp_rr_ABS_des
force_clp_rr_ABS_des
force_clp_rr_ABS_des
SteeringWheelTorque2
Trigger
SteerActuator
SteeringWheelTorque3
SteerActuatorOut
TieRodForce1
Timer
BTSetUp
Trigger
BrakeActuatorFR
SteerActuator
TieRodForce2
Timer
BTSetUp
SteerActuatorOut
BrakeOutFL_channel1
BrakeActuatorFL
TieRodForce3
Base Brake & ABS one
channel
BrakeActuatorRL
SpeedFL
BrakeActuatorRR
HandWheelTorqueActuator
SteeringActuator2
BrakeOutFR_channel1
BrakeOutRL_channel1
Vote Brake Comand
SpeedFR
force_clp_f_base_des
HandWheelTorqueActuator
SteeringActuator1
BrakeOutRR_channel1
SpeedRL
ComputeBrakeCommand
SpeedRR
force_clp_r_base_des
WarningLightYellow
BrakeOutFL_channel2
YawRate
DiagnosisBrakePedal
Base Brake & ABS one
channel
LateralAcceleration
WarningLightYellow
long_acc_veh_des
BrakeOutFR_channel2
Vote Brake Comand
BrakeOutRL_channel2
force_clp_fl_ABS_des
CurrentBatterie1
Arbiter_Br
Uniform
Pulses
WarningLightRed
BrakeOutRR_channel2
VoltageBatterie1
Trigger
force_clp_fr_ABS_des
WarningLightRed
BordnetStimulator
CurrentBatterie2
Comp_Cmd_ABS_Br
BrakeOutFL_channel3
VoltageBatterie2
force_clp_rl_ABS_des
Base Brake & ABS one
channel
CurrentAlternator
VoltageAlternator
BrakeOutFR_channel3
Vote Brake Comand
force_clp_rr_ABS_des
BrakeOutRL_channel3
BrakeOutRR_channel3
Timer
BTSetUp
BrakeOutFL_channel4
BrakeSwitchFil
Timer
Base Brake & ABS one
channel
Manipulator
AquireSignal
BTSetUp
C
h
an
ne
l1
C
ha
nn
el
2
C
BrakeOutFL
BrakeOutFR_channel4
Vote Brake Comand
BrakeOutRL_channel4
VotedSteeringWheelAngle
Diagnosis_Lateral_Sensors
BrakeOutRR_channel4
ComputeSteeringCommand
VotedRackPosition
BrakeOutFR
PedalSensor1Fil
Base Brake & ABS
AquireSignal
Manipulator
PedalSensor2Fil
BrakeOutRL
AquireSignal
Timer
BTSetUp
Timer
PedalSensor3Fil
Manipulator
AquireSignal
BTSetUp
Base Steering one
channel
BrakeOutRR
HandBrakeSwitchFil
SteeringActuatorOut_channel1
Manipulator
AquireSignal
VotedSteeringWheelAngle
Diagnosis_Lateral_Sensors
ComputeSteeringCommand
ClampForceFLFil
VotedRackPosition
AquireSignal
ClampForceFRFil
Base Steering one
channel
AquireSignal
ClampForceRLFil
SteeringActuatorOut_channel2
Timer
Vote_Cmp_Rack_Act
BTSetUp
AquireSignal
Base Steering
ClampForceRRFil
SteeringOut1
Manipulator
AquireSignal
VotedSteeringWheelAngle
SteeringOut2
Manipulator
SteeringWheelAngle1Fil
Diagnosis_Lateral_Sensors
Base Steering one
channel
AquireSignal
SteeringWheelAngle2Fil
ComputeSteeringCommand
SteeringActuatorOut_channel3
VotedRackPosition
AquireSignal
SteeringWheelAngle3Fil
AquireSignal
Vote_Cmp_Rack_Act
Timer
BTSetUp
SteeringWheelAngle4Fil
AquireSignal
Base Steering one
channel
RackPosition1Fil
AquireSignal
Handwheel
Feedback
RackPosition2Fil
AquireSignal
SteeringActuatorOut_channel4
VotedSteeringWheelAngle
SteeringWheelTorqueOut1
Diagnosis_Lateral_Sensors
Manipulator
ComputeSteeringCommand
VotedRackPosition
RackPosition3Fil
AquireSignal
SteeringWheelTorqueOut2
Timer
Manipulator
BTSetUp
RackPosition4Fil
Timer
BTSetUp
AquireSignal
AquireSignal
SteeringWheelTorque1Fil
Handwheel
Feedback one
channel
SteeringWheelTorque2Fil
AquireSignal
Master1BrakeFL
SteeringWheelTorque3Fil
AquireSignal
SteeringWheelTorqueOut_channel1
VotedSteeringWheelTorque
Diagnosis Feedback Sensors
ComputeSteeringTorqueCommand
Master1BrakeFR
VotedTieRodForce
Vote HW Feedback
Master1BrakeRL
Handwheel
Feedback one
channel
Master1BrakeRR
TieRodForce1Fil
AquireSignal
Master1SteeringAngleOut
Master
Controller
TieRodForce2Fil
AquireSignal
TieRodForce3Fil
SteeringWheelTorqueOut_channel2
Timer
BTSetUp
Master1SteeringTorqueOut
Vote HW Feedback
vel_veh_master_1
AquireSignal
SpeedFLFil
Handwheel
Feedback one
channel
l
Master1Warning
l
l
BrakeDiagnosis
AquireSignal
SteeringWheelTorqueOut_channel3
VotedSteeringWheelTorque
Master2BrakeFL
SpeedFRFil
Diagnosis Feedback Sensors
AquireSignal
ComputeSteeringTorqueCommand
Master2BrakeFR
VotedTieRodForce
SteeringDiagnosis
SpeedRLFil
Master
Controller
AquireSignal
SpeedRRFil
AquireSignal
Master2BrakeRL
Master2BrakeRR
Master2SteeringAngleOut
HWFeedbackDiagnosis
Timer
BTSetUp
YawRateFil
Master2SteeringTorqueOut
AquireSignal
vel_veh_master_2
LateralAccelerationFil
AquireSignal
Master2Warning
Cyclo
Static
Scheduler
CurrentBatterie1Fil
AquireSignal
Cyclo
Static
Scheduler
Cyclo
Static
Scheduler
Static
Priority
Scheduler
Diagnosis
Battery1Diagnosis
Cyclo
Static
Scheduler
Cyclo
Static
Scheduler
Static
Priority
Scheduler
Static
Priority
Scheduler
Cyclo
Static
Scheduler
ComputePowerManagement
VoltageBatterie1Fil
Cyclo
Static
Scheduler
Static
Priority
Scheduler
Cyclo
Static
Scheduler
Cyclo
Static
Scheduler
VotedSteeringWheelTorque
Static
Priority
Scheduler
Cyclo
Static
Scheduler
Static
Priority
Scheduler
Cyclo
Static
Scheduler
Cyclo
Static
Scheduler
ComputeSteeringTorqueCommand
CurrentBatterie2Fil
InterruptBus
AquireSignal
InterruptBus
Simple
ASIC
Battery2Diagnosis
InterruptBus
DataBus
InternalDataBus
InterruptBus
Simple
ASIC
CPU
InterruptBus
InterruptBus
InterruptBus
InternalDataBus
DataBus
Simple
ASIC
CPU
DataBus
InternalDataBus
CPU
Simple
ASIC
InterruptBus
InterruptBus
InternalDataBus
DataBus
CPU
Simple
ASIC
InterruptBus
InternalDataBus
DataBus
CPU
InterruptBus
Simple
ASIC
InterruptBus
InternalDataBus
ComputePowerManagement
ExternalBus
ExternalBus
ExternalBus
ExternalBus
ExternalBus
ExternalBus
VoltageBatterie2Fil
AquireSignal
Diagnosis
CurrentAlternatorFil
AquireSignal
ExternalBusPort
ExternalBusPort
ExternalBusPort
ExternalBusPort
ExternalBusPort
ExternalBusPort
AlternatorDiagnosis
ComputePowerManagement
VoltageAlternatorFil
AquireSignal
ECU_2Tasks_1BusCha
ECU_2Tasks_1BusCha
ExternalBusPort
ECU_2Tasks_1BusCha
Cyclo
Static
Scheduler
Static
Priority
Scheduler
InterruptBus
PPC
TTPController
C
ha
nn
el
2
RTOS
PPC
RTOS
TTPController
PPC
RTOS
PPC
TTPController
C
h
an
n
el
1
RTOS
PPC
RTOS
TTPController
C
PPC
RTOS
TTPController
C
ha
nn
el
1
C
C
ha
nn
el
2
C
PPC_TTP
Channel1
PPC_TTP
Channel1
PPC_TTP
Channel1
PPC_TTP
Channel1
PPC_TTP
Channel1
PPC_TTP
Channel1
Channel2
Channel2
Channel2
Channel2
Channel2
Channel2
PPC_TTP
Channel1
PPC_TTP
Channel1
PPC_TTP
Channel1
PPC_TTP
Channel1
Channel2
Channel2
Channel2
Channel2
TTP Channel 2
PPC
TTPController
C
h
an
n
e1
C
h
an
n
el
2
RTOS
PPC
TTPController
C
h
an
n
e
1
C
h
an
n
el
2
PPC
RTOS
TTPController
C
ha
n
el1
C
ha
nn
e2
RTOS
PPC
TTPController
C
ha
nn
el
1
PPC
TTPController
C
ha
nn
el
2
PPC_TTP
Channel1
Channel2
ExternalBusPort
ECU_2Tasks_1BusChan
ExternalBusPort
ExternalBusPort
Cyclo
Static
Scheduler
Static
Priority
Scheduler
Static
Priority
Scheduler
Cyclo
Static
Scheduler
Cyclo
Static
Scheduler
InterruptBus
InternalDataBus
DataBus
InterruptBus
InterruptBus
InterruptBus
InterruptBus
InterruptBus
CPU
Simple
ASIC
InternalDataBus
DataBus
Simple
ASIC
CPU
InternalDataBus
ExternalBus
ExternalBusPort
ExternalBusPort
C
h
an
n
e
1
RTOS
Simple
ASIC
ECU_2Tasks_1BusChan
ExternalBusPort
DataBus
CPU
Simple
ASIC
InternalDataBus
ExternalBus
ExternalBusPort
TTPController
C
ha
nn
el
2
CPU
ExternalBus
C
h
an
n
el
2
RTOS
DataBus
ECU_2Tasks_1BusChan
ExternalBusPort
Cyclo
Static
Scheduler
Static
Priority
Scheduler
Cyclo
Static
Scheduler
InterruptBus
InterruptBus
InternalDataBus
ExternalBus
ECU_2Tasks_1BusChan
ExternalBusPort
ECU_2Tasks_1BusChan
ExternalBusPort
Cyclo
Static
Scheduler
Static
Priority
Scheduler
Cyclo
Static
Scheduler
InterruptBus
Simple
ASIC
ECU_2Tasks_1BusChan
ExternalBusPort
ECU_2Tasks_1BusCha
ExternalBusPort
Cyclo
Static
Scheduler
Cyclo
Static
Scheduler
ECU_2Tasks_1BusChan
ExternalBusPort
C
ha
nn
el
2
ExternalBus
ExternalBusPort
ExternalBusPort
DataBus
CPU
Diagnosis Feedback Sensors
VotedTieRodForce
AquireSignal
DataBus
CPU
Design Flow(8)
• Initialization of the UCM performance model.
– Automated generation of an initial communication matrix that carries the dependency
of the functional system mapping.
• Definition of a specific bus protocol implementation
– UCM parameterization. Definition of the communication cycle layout. Data frame
definition.
BrakeSwitch
PedalSensor1
PedalSensor2
Uniform
Pulses
Uniform
Pulses
Uniform
Pulses
PedalSensor3
Timer
Timer
Timer
BTSetUp
BTSetUp
BTSetUp
HandBrakeSwitch
ClampForceFL
ClampForceFR
force_clp_f_base_des
force_clp_f_base_des
force_clp_f_base_des
ClampForceRL
ComputeBrakeCommand
ComputeBrakeCommand
ComputeBrakeCommand
Trigger
ClampForceRR
BrakeActuator
BrakeActuatorOut
force_clp_r_base_des
force_clp_r_base_des
force_clp_r_base_des
SteeringWheelAngle1
DiagnosisBrakePedal
Trigger
DiagnosisBrakePedal
DiagnosisBrakePedal
long_acc_veh_des
long_acc_veh_des
long_acc_veh_des
SteeringWheelAngle2
Trigger
BrakeActuator
SteeringWheelAngle3
BrakeActuatorOut
DbW_TopBlock
force_clp_fl_ABS_des
force_clp_fl_ABS_des
force_clp_fl_ABS_des
SteeringWheelAngle4
Arbiter_Br
Arbiter_Br
Arbiter_Br
Trigger
DriverSteer
DriverSteer
Driver
DriverBrake
DriverBrake
DriverGas
DriverGas
DriverClutch
Trigger
2 Track
Vehicle
Model
RackPosition1
BrakeActuator
force_clp_fr_ABS_des
BrakeActuatorOut
force_clp_fr_ABS_des
force_clp_fr_ABS_des
RackPosition2
Comp_Cmd_ABS_Br
Comp_Cmd_ABS_Br
Comp_Cmd_ABS_Br
RackPosition3
force_clp_rl_ABS_des
force_clp_rl_ABS_des
force_clp_rl_ABS_des
Trigger
DriverClutch
BrakeActuator
RackPosition4
BrakeActuatorOut
DriverGear
DriverGear
SteeringWheelTorque1
force_clp_rr_ABS_des
force_clp_rr_ABS_des
force_clp_rr_ABS_des
SteeringWheelTorque2
Trigger
SteerActuator
SteeringWheelTorque3
SteerActuatorOut
TieRodForce1
Timer
BTSetUp
Trigger
BrakeActuatorFR
SteerActuator
TieRodForce2
Timer
BTSetUp
SteerActuatorOut
BrakeOutFL_channel1
BrakeActuatorFL
TieRodForce3
Base Brake & ABS one
channel
BrakeActuatorRL
SpeedFL
BrakeActuatorRR
HandWheelTorqueActuator
SteeringActuator2
BrakeOutFR_channel1
BrakeOutRL_channel1
Vote Brake Comand
SpeedFR
force_clp_f_base_des
HandWheelTorqueActuator
SteeringActuator1
BrakeOutRR_channel1
SpeedRL
ComputeBrakeCommand
SpeedRR
force_clp_r_base_des
WarningLightYellow
BrakeOutFL_channel2
YawRate
DiagnosisBrakePedal
Base Brake & ABS one
channel
LateralAcceleration
WarningLightYellow
long_acc_veh_des
BrakeOutFR_channel2
Vote Brake Comand
BrakeOutRL_channel2
force_clp_fl_ABS_des
CurrentBatterie1
Arbiter_Br
Uniform
Pulses
WarningLightRed
BrakeOutRR_channel2
VoltageBatterie1
Trigger
force_clp_fr_ABS_des
WarningLightRed
BordnetStimulator
CurrentBatterie2
Comp_Cmd_ABS_Br
BrakeOutFL_channel3
VoltageBatterie2
force_clp_rl_ABS_des
Base Brake & ABS one
channel
CurrentAlternator
VoltageAlternator
BrakeOutFR_channel3
Vote Brake Comand
force_clp_rr_ABS_des
BrakeOutRL_channel3
BrakeOutRR_channel3
Timer
BTSetUp
BrakeOutFL_channel4
BrakeSwitchFil
Timer
BTSetUp
Base Brake & ABS one
channel
Manipulator
AquireSignal
BrakeOutFL
BrakeOutFR_channel4
Vote Brake Comand
BrakeOutRL_channel4
VotedSteeringWheelAngle
Diagnosis_Lateral_Sensors
BrakeOutRR_channel4
ComputeSteeringCommand
VotedRackPosition
BrakeOutFR
PedalSensor1Fil
Base Brake & ABS
AquireSignal
Manipulator
PedalSensor2Fil
BrakeOutRL
AquireSignal
Timer
BTSetUp
Timer
PedalSensor3Fil
Manipulator
AquireSignal
BTSetUp
Base Steering one
channel
BrakeOutRR
HandBrakeSwitchFil
SteeringActuatorOut_channel1
Manipulator
AquireSignal
VotedSteeringWheelAngle
Diagnosis_Lateral_Sensors
ComputeSteeringCommand
ClampForceFLFil
VotedRackPosition
AquireSignal
ClampForceFRFil
Base Steering one
channel
AquireSignal
ClampForceRLFil
SteeringActuatorOut_channel2
Timer
Vote_Cmp_Rack_Act
BTSetUp
AquireSignal
Base Steering
ClampForceRRFil
SteeringOut1
Manipulator
AquireSignal
VotedSteeringWheelAngle
SteeringOut2
Manipulator
SteeringWheelAngle1Fil
Diagnosis_Lateral_Sensors
Base Steering one
channel
AquireSignal
SteeringWheelAngle2Fil
ComputeSteeringCommand
SteeringActuatorOut_channel3
VotedRackPosition
AquireSignal
SteeringWheelAngle3Fil
AquireSignal
Vote_Cmp_Rack_Act
Timer
BTSetUp
SteeringWheelAngle4Fil
AquireSignal
Base Steering one
channel
RackPosition1Fil
AquireSignal
Handwheel
Feedback
RackPosition2Fil
AquireSignal
SteeringActuatorOut_channel4
VotedSteeringWheelAngle
SteeringWheelTorqueOut1
Diagnosis_Lateral_Sensors
Manipulator
ComputeSteeringCommand
VotedRackPosition
RackPosition3Fil
AquireSignal
SteeringWheelTorqueOut2
Timer
Manipulator
BTSetUp
RackPosition4Fil
Timer
BTSetUp
AquireSignal
AquireSignal
SteeringWheelTorque1Fil
Handwheel
Feedback one
channel
SteeringWheelTorque2Fil
AquireSignal
Master1BrakeFL
SteeringWheelTorque3Fil
AquireSignal
SteeringWheelTorqueOut_channel1
VotedSteeringWheelTorque
Diagnosis Feedback Sensors
ComputeSteeringTorqueCommand
Master1BrakeFR
VotedTieRodForce
Vote HW Feedback
Master1BrakeRL
Handwheel
Feedback one
channel
Master1BrakeRR
TieRodForce1Fil
AquireSignal
Master1SteeringAngleOut
TieRodForce2Fil
AquireSignal
Master
Controller
TieRodForce3Fil
SteeringWheelTorqueOut_channel2
Timer
BTSetUp
Master1SteeringTorqueOut
Vote HW Feedback
vel_veh_master_1
AquireSignal
Handwheel
Feedback one
channel
Master1Warning
BrakeDiagnosis
SpeedFLFil
AquireSignal
SteeringWheelTorqueOut_channel3
VotedSteeringWheelTorque
Master2BrakeFL
SpeedFRFil
Diagnosis Feedback Sensors
AquireSignal
ComputeSteeringTorqueCommand
Master2BrakeFR
VotedTieRodForce
SteeringDiagnosis
SpeedRLFil
AquireSignal
SpeedRRFil
AquireSignal
Master
Controller
Master2BrakeRL
Master2BrakeRR
Master2SteeringAngleOut
HWFeedbackDiagnosis
Timer
BTSetUp
YawRateFil
Master2SteeringTorqueOut
AquireSignal
vel_veh_master_2
LateralAccelerationFil
AquireSignal
Master2Warning
Cyclo
Static
Scheduler
CurrentBatterie1Fil
AquireSignal
Cyclo
Static
Scheduler
Cyclo
Static
Scheduler
Static
Priority
Scheduler
Static
Priority
Scheduler
Cyclo
Static
Scheduler
ComputePowerManagement
Cyclo
Static
Scheduler
Cyclo
Static
Scheduler
Static
Priority
Scheduler
Diagnosis
Battery1Diagnosis
VoltageBatterie1Fil
Cyclo
Static
Scheduler
Static
Priority
Scheduler
Cyclo
Static
Scheduler
Cyclo
Static
Scheduler
VotedSteeringWheelTorque
Static
Priority
Scheduler
Cyclo
Static
Scheduler
Static
Priority
Scheduler
Cyclo
Static
Scheduler
Cyclo
Static
Scheduler
ComputeSteeringTorqueCommand
CurrentBatterie2Fil
InterruptBus
AquireSignal
InterruptBus
Simple
ASIC
Battery2Diagnosis
InterruptBus
DataBus
InternalDataBus
InterruptBus
Simple
ASIC
CPU
InterruptBus
InterruptBus
InterruptBus
InternalDataBus
DataBus
Simple
ASIC
CPU
DataBus
InternalDataBus
CPU
Simple
ASIC
InterruptBus
InterruptBus
InternalDataBus
DataBus
CPU
Simple
ASIC
InterruptBus
InternalDataBus
DataBus
CPU
InterruptBus
Simple
ASIC
InterruptBus
InternalDataBus
ComputePowerManagement
ExternalBus
ExternalBus
AquireSignal
ExternalBus
ExternalBus
ExternalBus
ExternalBus
VoltageBatterie2Fil
Diagnosis
CurrentAlternatorFil
AquireSignal
ExternalBusPort
ExternalBusPort
ExternalBusPort
ExternalBusPort
ExternalBusPort
ExternalBusPort
AlternatorDiagnosis
ComputePowerManagement
VoltageAlternatorFil
AquireSignal
ECU_2Tasks_1BusCha
ECU_2Tasks_1BusCha
ExternalBusPort
Cyclo
Static
Scheduler
Cyclo
Static
Scheduler
Static
Priority
Scheduler
Cyclo
Static
Scheduler
InterruptBus
InterruptBus
InternalDataBus
ExternalBus
DataBus
CPU
Cyclo
Static
Scheduler
InterruptBus
Simple
ASIC
ECU_2Tasks_1BusChan
ExternalBusPort
ExternalBusPort
Cyclo
Static
Scheduler
Static
Priority
Scheduler
Static
Priority
Scheduler
Cyclo
Static
Scheduler
Cyclo
Static
Scheduler
InterruptBus
InternalDataBus
DataBus
InterruptBus
InterruptBus
InterruptBus
InterruptBus
InterruptBus
CPU
Simple
ASIC
InternalDataBus
DataBus
CPU
Simple
ASIC
InternalDataBus
DataBus
CPU
Simple
ASIC
InternalDataBus
ExternalBus
ExternalBus
ExternalBusPort
ExternalBusPort
ECU_2Tasks_1BusChan
ExternalBusPort
Cyclo
Static
Scheduler
InterruptBus
Simple
ASIC
ECU_2Tasks_1BusChan
ExternalBusPort
Static
Priority
Scheduler
Cyclo
Static
Scheduler
ECU_2Tasks_1BusChan
ExternalBusPort
ECU_2Tasks_1BusChan
ExternalBusPort
Cyclo
Static
Scheduler
Static
Priority
Scheduler
ECU_2Tasks_1BusChan
ExternalBusPort
ECU_2Tasks_1BusCha
ExternalBusPort
Bus Type
Pattern
ECU_2Tasks_1BusChan
ExternalBusPort
ECU_2Tasks_1BusCha
ExternalBus
ExternalBus
ExternalBusPort
ExternalBusPort
ExternalBusPort
ExternalBusPort
DataBus
CPU
Diagnosis Feedback Sensors
VotedTieRodForce
AquireSignal
DataBus
CPU
Design Flow (9)
• Performance simulation including the bus latencies
• Full System co-verification: both communications and computation
Bus Type
Pattern
Design Iterations
Example of Co-Design: Design Space
Exploration of Multimedia Platform
CADENCE CONFIDENTIAL
Multimedia Applications – Design
Space Exploration
map_FAKIR_Diagrams.MPEG_VIPER_SH2
Frame Processing - Actual Delay (sec)
2B
1I
2B
3B
4P
5B
6B
7P
8B
9B
10I
11B
12B
13P
14B
15B
23B
24B
25P
26B
27B
28P
29B
16P
17B
18B
19P
20B
21B
22I
16:t_hdr
3B
4P
5B
6B
7P
8B
9B
10I 11B
12B
13P
14B
23B
24B
25P
26B
27B
28P
15B
16P
17B
18B
19P
20B
21B
22I
14:t_memMan (Peeker)
15:t_memMan
14:t_output
13:t_isiq
12:t_vld
11:t_predict
10:t_idct
proc
procID
28 “Peeker” Frames in … 2 sec!
8:t_output
9:t_add
8:t_writeMB
7:t_memory
1B
2P
3P
4B
5P
6P
7B
8I
9I
10B
11P
12P
22B
23P
24P
25B
26P
13B
14P
15P
16B
17P
18P
19B
20I
21I
6:t_decMV
5:in_es
4:drop_finfo
3:ofileproc
0,00
0,20
0,40
0,60
0,80
Application Analyst
1,00
tStart
0,00E+00
1,00E-01
2,00E-01
3,00E-01
4,00E-01
5,00E-01
6,00E-01
AvgOfintraDelay
7,00E-01
8,00E-01
3,50E+06
3,00E+06
2,50E+06
2,00E+06
1,50E+06
1,00E+06
5,00E+05
0,00E+00
1
3
5
7
9
11
13
15
17
frameID
Process Analyst
19
21
23
25
2
4
7
9
10
11
12
14
16
17
18
19
22
23
25
26
27
30
33
35
36
37
40
42
Communication Analyst
Data Analysis Workbooks
for specific roles
(Excel+StatBox)
Design Data
Exported from
VCC diagrams
using “VCCAPI”
map_FAKIR_Diagrams.MPEG_VIPER_SH2
YAPI Transactions - Write - Number of bytes per channel per frame
4,00E+06
nbByte
1I
R2c
R25c
R27c
R30c
R34b
R16m
R27m
R30m
R32m
E1s
E16s
E27s
E2c
E16c
E27c
E30c
E34b
E32m
W1s
W2c
W27c
9,00E-01 W30c
W34b
W6m
map_FAKIR_Diagrams.MPEG_VIPER_S1
Breakdown of Workload on Architectural Resources of Type: RTOS, CORE, MEM &
BUS - Per Process - Average Intrinsic Delay per Frame (sec)
15:t_hdr
Classification
Design Space Navigator
(SQL queries)
vccDse
Database
vccMap
Database
vccSim
Database
Thdr
YSH1
YSH1
YSH1
YHS1
YSH1
Thdr_status_In
Toutput
YSH1
YSH1
YSH1
YSH1
Tpredict
TdecMV
Tmemory
Yo_Info
Y_Info
Tmemory_line_address_Out
Tpredict_prop_pic_In
VHH1
YHS1
YSH1
YSH1
Y_Data
Tvld
Tpredict_token_Out
TdecMV_prop_mv_In
YSH1
Yo_Data
Uo_Info
Tmemory_line_data_In
Tpredict_token_In
Tpredict_prop_pred_In
U_Info
Toutput_line_address_In
Tpredict_prop_pred_Out
Uo_Data
Toutput_cmd_In
es
Tvld_bits_In
TdecMV_prop_mv_Out
U_Data
Vo_Info
V_Info
Vo_Data
V_Data
Sinfo
finfo
Tpredict_mv_In
TdecMV_prop_pred_In
Toutput_prop_seq_In
Tpredict_mv_Out
TdecMV_prop_pred_Out
YSS1
YHS1
YSH1
YHH1
Tmemory_mb_p_In
Tadd_mb_p_Out
Tpredict_prop_seq_In
TmemMan_pic_In
Tpredict_prop_seq_Out
YHH1
Sinfo
Toutput_line_data_Out
cosy_init
cosy_init
finfo
cosy_init
YSH1
YSS1
YSH1
YHH1
YHHP
TmemMan_cmd_In
TwriteMB_prop_pic_In
TmemMan_cmd_Out
mb_QFS_In
YHH1
YSH1
YHHP
YHHP
mb_F_In
mb_f_In
TmemMan_prop_seq_In
Toutput_cmd_Out
mb_d_In
mb_f_Out
mb_F_Out
Tisiq_prop_seq_In
Tidct_prop_seq_Out
Tidct_prop_seq_In
Tidct_prop_mb_In
Tidct_prop_mb_Out
TmemMan_prop_seq_Out
mb_d_Out
Tadd_prop_seq_In
Tadd_prop_seq_Out
Tisiq_prop_mb_In
TwriteMB_prop_seq_Out
TwriteMB_prop_seq_In
TmemMan_prop_pic_Out
TwriteMB_prop_mb_In
TwriteMB_mem_id_In
Tadd_prop_mb_In
Tisiq
TwriteMB_pic_In
TwriteMB_mem_id_Out
Toutput_prop_seq_Out
Toutput_pic_Out
TwriteMB_prop_mb_Out
Tadd_prop_mb_Out
cosy_init
YHH1
YHH1
YHHP
YHHP
cosy_init
cosy_init
Tidct
Tadd
TwriteMB
TmemMan
cosy_init
YHHP
YSH1
YHHP
YHH1
YHSP
YHS1
YHSP
YHHP
YHHP
YHH1
YHHP
YSH1
YHH1
YHSP
Created by COSY (c) May 2001
FPBC_MPIC
EJTAG
PR3940
FPIMI
MMI
Memory
pSOS
RTOS
TM_3218
f_pi_bus
FR_MEM
M_bridge
MBS
MPBC_GLOBAL
TPIC
PCI
ICP1_2
BOOT_DBG
GPIO
DE
VMPG
SMCARD
USB
IIC1_2
IEEE1394
SPDIO
VMPG_
AUX
AIO1_3
VIP1_2
m_pi_bus
t_pi_bus
UART1_3
SSI
MSP1_2
CLOCKS
C_Bridge
TPBC
Performance Data
Collected by VCC
probes under control
of system events
Export Mapping Data to DataBase
Thdr
YSH1
YSH1
YSH1
YHS1
YSH1
Thdr_status_In
YSH1
YSH1
YSH1
Toutput
YSH1
VHH1
YHS1
YSH1
YSH1
Tpredict
TdecMV
Tmemory
Yo_Info
YSH1
Y_Info
Tmemory_line_address_Out
Tpredict_prop_pic_In
Y_Data
Tvld
Uo_Info
Tmemory_line_data_In
Tpredict_token_In
Tpredict_prop_pred_In
Tpredict_token_Out
TdecMV_prop_mv_In
Yo_Data
U_Info
Toutput_line_address_In
Tpredict_prop_pred_Out
Uo_Data
Toutput_cmd_In
U_Data
Tvld_bits_In
es
TdecMV_prop_mv_Out
YHS1
YSH1
YSS1
YHH1
Toutput_prop_seq_In
Tpredict_mv_Out
Tadd_mb_p_Out
TmemMan_pic_In
cosy_init
V_Data
Sinfo
finfo
YHH1
finfo
cosy_init
YHH1
Vo_Data
Sinfo
Toutput_line_data_Out
cosy_init
YSH1
V_Info
Tmemory_mb_p_In
Tpredict_prop_seq_In
Tpredict_prop_seq_Out
YSS1
Vo_Info
Tpredict_mv_In
TdecMV_prop_pred_In
TdecMV_prop_pred_Out
YHHP
YSH1
TmemMan_cmd_In
TwriteMB_prop_pic_In
TmemMan_cmd_Out
YHH1
YSH1
YHHP
YHHP
mb_QFS_In
mb_F_In
mb_f_In
TmemMan_prop_seq_In
Tidct_prop_seq_Out
Tidct_prop_seq_In
Tisiq_prop_mb_In
TmemMan_prop_seq_Out
mb_d_Out
Tadd_prop_seq_In
Tadd_prop_seq_Out
Tidct_prop_mb_In
TwriteMB_prop_seq_In
TwriteMB_prop_seq_Out
Tadd_prop_mb_In
TwriteMB_prop_mb_In
Tidct_prop_mb_Out
YHH1
YHH1
YHHP
Toutput_cmd_Out
mb_d_In
mb_f_Out
mb_F_Out
Tisiq_prop_seq_In
YHHP
TwriteMB_mem_id_In
TwriteMB_mem_id_Out
Toutput_prop_seq_Out
Toutput_pic_Out
YHSP
TwriteMB_prop_mb_Out
Tadd_prop_mb_Out
cosy_init
Tisiq
TwriteMB_pic_In
TmemMan_prop_pic_Out
cosy_init
cosy_init
Tidct
Tadd
TwriteMB
TmemMan
YHS1
cosy_init
YHHP
YSH1
YHHP
YHH1
YHHP
YHHP
YHH1
YHHP
YSH1
YHH1
YHSP
YHSP
in
Created by COSY (c) May 2001
TDROP_field_inf
o
FPBC_MPIC
EJTAG
PR3940
YSH1
cosy_init
FPIMI
beh_MPEG_Processes
MMI
Memory
SMPEGDecode
Yo_Info
TBINFILE_unsig
ned_char
pSOS
RTOS
TM_3218
TBE
finfo
Sinfo
f_pi_bus
YSH1
sinfob
CA_Info
FR_MEM
M_bridge
es
Yo_Data
CA_Data
out
cosy_init
cosy_init
Uo_Info
CB_Info
Uo_Data
CB_Data
Vo_Info
CC_Info
Vo_Data
CC_Data
cosy_init
YSH1
YSH1
MBS
MPBC_GLOBAL
TPIC
PCI
cosy_init
Created by COSY (c) June 2001
YSH1
YSH1
YSH1
YSH1
ICP1_2
BOOT_DBG
DE
SMCARD
USB
IIC1_2
IEEE1394
GPIO
VMPG
SPDIO
VMPG_
AUX
FPBC_MPIC
EJTAG
PR3940
AIO1_3
VIP1_2
FPIMI
MMI
Memory
pSOS
RTOS
m_pi_bus
TM_3218
t_pi_bus
UART1_3
SSI
MSP1_2
f_pi_bus
FR_MEM
M_bridge
CLOCKS
MBS
MPBC_GLOBAL
TPIC
PCI
ICP1_2
BOOT_DBG
DE
SMCARD
USB
GPIO
VMPG
SPDIO
VMPG_
AUX
IIC1_2
AIO1_3
IEEE1394
VIP1_2
m_pi_bus
t_pi_bus
UART1_3
SSI
MSP1_2
CLOCKS
C_Bridge
TPBC
C_Bridge
TPBC
System-Observation-Windows
FPBC_MPIC
EJTAG
PR3940
FPIMI
MMI
Memory
pSOS
RTOS
TM_3218
f_pi_bus
FR_MEM
M_bridge
MBS
MPBC_GLOBAL
Thdr
Thdr_status_In
Toutput
Tpredict
TdecMV
Tmemory
Yo_Info
Y_Info
Tmemory_line_address_Out
Tpredict_prop_pic_In
Y_Data
Tvld
Yo_Data
Uo_Info
Tmemory_line_data_In
Tpredict_token_In
Tpredict_prop_pred_In
Tpredict_token_Out
TdecMV_prop_mv_In
U_Info
Toutput_line_address_In
Tpredict_prop_pred_Out
Uo_Data
Toutput_cmd_In
es
Tvld_bits_In
U_Data
TdecMV_prop_mv_Out
Vo_Info
Tpredict_mv_In
TdecMV_prop_pred_In
Toutput_prop_seq_In
Tpredict_mv_Out
TdecMV_prop_pred_Out
V_Info
Vo_Data
V_Data
Sinfo
finfo
Tmemory_mb_p_In
Tadd_mb_p_Out
Tpredict_prop_seq_In
TmemMan_pic_In
Tpredict_prop_seq_Out
Sinfo
Toutput_line_data_Out
cosy_init
cosy_init
finfo
For, e.g. Each MPEG Frame
Measure…
cosy_init
TPIC
PCI
ICP1_2
BOOT_DBG
DE
SMCARD
USB
IIC1_2
IEEE1394
GPIO
VMPG
SPDIO
VMPG_
AUX
AIO1_3
VIP1_2
TmemMan_cmd_In
TwriteMB_prop_pic_In
m_pi_bus
TmemMan_cmd_Out
mb_QFS_In
mb_F_In
mb_f_In
TmemMan_prop_seq_In
Toutput_cmd_Out
mb_d_In
mb_f_Out
mb_F_Out
Tisiq_prop_seq_In
Tidct_prop_seq_In
Tidct_prop_seq_Out
Tadd_prop_seq_Out
Tisiq_prop_mb_In
TmemMan_prop_seq_Out
mb_d_Out
Tadd_prop_seq_In
Tidct_prop_mb_In
TwriteMB_prop_seq_Out
TwriteMB_prop_seq_In
Tadd_prop_mb_In
TwriteMB_prop_mb_In
Tidct_prop_mb_Out
Tadd_prop_mb_Out
TmemMan_prop_pic_Out
TwriteMB_mem_id_In
TwriteMB_pic_In
TwriteMB_mem_id_Out
Toutput_prop_seq_Out
t_pi_bus
UART1_3
SSI
MSP1_2
Toutput_pic_Out
TwriteMB_prop_mb_Out
cosy_init
cosy_init
cosy_init
Tisiq
Tidct
Tadd
TwriteMB
TmemMan
cosy_init
CLOCKS
C_Bridge
TPBC
Created by COSY (c) May 2001
e.g. process activity
Frame
ID
1
1
1
1
1
1
1
1
…
2
2
2
2
2
2
2
2
2
…
Port Name
Tvld_bits_In
Tvld_cmd_In
Tvld_prop_pic_In
Tvld_prop_slice_In
mb_QFS_Out
Thdr_status_Out
Tisiq_prop_mb_Out
TdecMV_prop_mv_Out
…
Tvld_bits_In
Tvld_cmd_In
Tvld_prop_pic_In
Tvld_prop_slice_In
mb_QFS_Out
Thdr_status_Out
Tisiq_prop_mb_Out
TdecMV_prop_mv_Out
TdecMV_prop_pred_Out
…
Transaction
Nb
324
208
1
36
1,622
208
1,622
1,622
…
525
206
1
36
1,619
206
1,619
1,619
1,619
…
Item
Nb
20,736
208
1
36
622,704
208
1,622
1,622
….
33,600
206
1
36
621,696
206
1,619
1,619
1,619
…
Actual
Delay
0.14
0.13
0.00
0.00
6.66
0.01
0.03
0.04
…
0.23
0.12
0.00
0.00
6.53
0.01
0.03
0.04
0.09
…
e.g. MEMORY usage
Intra
Delay
0.02
0.00
0.00
0.00
0.65
0.01
0.03
0.04
….
0.03
0.00
0.00
0.00
0.65
0.01
0.03
0.04
0.09
…
Pict 1 Pict 2
Frame
ID
1
1
1
1
1
1
1
…
2
2
2
2
2
2
2
2
…
Requestor
Behavior/in_es_out_sender
Behavior/decode/t_vld_Tvld_bits_In_receiver
Behavior/decode/t_hdr_Tvld_cmd_Out_sender
Behavior/decode/t_vld_Tvld_cmd_In_receiver
Behavior/decode/t_hdr_Tvld_prop_pic_Out_sender
Behavior/decode/t_vld_Tvld_prop_pic_In_receiver
Behavior/decode/t_hdr_Tvld_prop_slice_Out_sender
….
Behavior/in_es_out_sender
Behavior/decode/t_vld_Tvld_bits_In_receiver
Behavior/decode/t_hdr_Tvld_cmd_Out_sender
Behavior/decode/t_vld_Tvld_cmd_In_receiver
Behavior/decode/t_hdr_Tvld_prop_pic_Out_sender
Behavior/decode/t_vld_Tvld_prop_pic_In_receiver
Behavior/decode/t_hdr_Tvld_prop_slice_Out_sender
Behavior/decode/t_vld_Tvld_prop_slice_In_receiver
…
Delay
Mean
5.64E-06
2.91E-06
2.40E-07
2.40E-07
2.16E-06
2.16E-06
7.20E-07
…
5.64E-06
2.91E-06
2.40E-07
2.40E-07
2.16E-06
2.16E-06
7.20E-07
7.20E-07
…
Delay
StDev
3.00E-06
1.20E-06
1.17E-14
1.17E-14
0.00E+00
0.00E+00
1.22E-14
…
3.00E-06
1.20E-06
1.17E-14
1.17E-14
0.00E+00
0.00E+00
1.22E-14
1.22E-14
…
“Probe-Synch” & Observer Probes
 Probe-Synch is triggered on
conditions in a behavioral
block (i.e. MPEG frame
decoded)
 Control up to 200 distributed
observer probes of different
types: i.e Memory probes, Bus
probes, CPU “Delay” probes
etc…
MEMORY OBSERVER
PROBE
CPU
OBSERVER
PROBE
 Observer Probes record
summary data at the
granularity defined by the
peeker
BUS
OBSERVER
PROBE
Queries 1: link Map & Simulation data
Calculate Average Actual & Intrinsic Communication Rates of all “YAPI”
application level Channels
SELECT simComAppYapi.sessionCounter AS frameID…,
simComAppYapi.actualDelay,…
FROM
mapComAppYapi INNER JOIN fctProc ON mapComAppYapi.srcProcID =
fctProc.ID…
WHERE
simComAppYapi.VccInstanceName)=[fctProc].[diagName] & "/" &
[fctProc].[procName];
chanID
2
2
16
frameID
3
10
18
nbTransaction
nbItem
nbByte
actualDelay
5,76E+02 5,76E+02 6,91E+03
5,10E+01 5,10E+01 6,12E+02
1,62E+03 1,62E+03 4,54E+04
Simulation “Frame” Context
Key to retrieve Design “Mapping” Decision
intrinsicDelay
6,06E-04
4,56E-05
7,26E-02
6,06E-04
4,56E-05
3,54E-05
Simulation results
Queries 2: calculate basic Statistics
Calculate Average Actual & Intrinsic Communication Rates of all
“YAPI” application level Channels
SELECT DISTINCTROW
Avg([nbByte]/[actualDelay]) AS AvgOfActualRate,
StDev([nbByte]/[actualDelay]) AS StDevOfActualRate,…
Avg([nbByte]/[intraDelay]) AS AvgOfIntraRate, … INTO
staComAppYapiRate_perChan
FROM mkStaComAppYapiRate_perChan_step1
GROUP BY chanID…;
comA trans chanI portID AvgOfActualRate StDevOf
ppClas action
D
ActualR
s
ate
YAPI
Rd
2
14
5,61E+06 5,98E+0
4
YAPI
Wr
2
48
7,34E+06 1,58E+0
6
YAPI
Rd
3
15
6,27E+07
YAPI
Rd
4
11
5,62E+08
YAPI
Wr
4
46
5,80E+08
YAPI
Wr
7
44
7,29E+06
1,61E+0
7
4,86E+0
7
7,15E+0
MinOfA
ctualR
ate
5,55E+
06
6,47E+
06
6,27E+
07
5,39E+
08
5,49E+
08
5,10E+
MaxOfA AvgOfIntraRate StDevOf
ctualRat
IntraRat
e
e
5,77E+0
6,09E+06 5,86E+0
6
4
1,21E+0
1,13E+07 4,90E+0
7
5
6,27E+0
6,67E+07
7
6,00E+0
6,47E+08 1,59E+0
8
7
7,20E+0
5,89E+08 4,82E+0
8
7
3,15E+0
7,57E+06 7,86E+0
Application Analyst
map_FAKIR_Diagrams.MPEG_VIPER_SH2
Frame Processing - Actual Delay (sec)
15:t_hdr
1I
2B
1I
2B
3B
4P
3B
5B
4P
6B
5B
7P
6B
8B
7P
9B
8B
10I
9B
11B
12B
10I 11B
13P
14B
15B
23B
24B
25P
26B
27B
28P
29B
16P
17B
18B
19P
20B
21B
22I
12B
13P
14B
23B
24B
25P
26B
27B
28P
15B
16P
17B
18B
19P
20B
21B
22I
10B
11P
12P
22B
23P
24P
25B
26P
13B
14P
15P
16B
17P
18P
19B
20I
21I
14:t_memMan (Probe-Synch)
procID
28 Frames in … 2 sec
8:t_output
1B
0,00
2P
0,20
3P
4B
5P
6P
0,40
7B
0,60
tStart
8I
9I
0,80
1,00
Process Analyst
map_FAKIR_Diagrams.MPEG_VIPER_S1
Breakdown of Process Execution on basic Architectural Resources of Type:
CORE, MEM & BUS - Average Actual Delay per Frame (sec)
R27m
R34b
E32m
W32m
R2c
E34b
W34b
E2c
W2c
16:t_hdr R32m
R27m
R30m
R32m
E32m
R34b
W34b
E34b
W2c
R2c
E2c
15:t_memMan W32m
Process
R2c
R27c
R32m
R34b
E27c
W2c
W25m
W32m
W27c
W34b
W6m
14:t_output
“t-predict”
13:t_isiq
R2c
R30c
R34b E2c E30c
R32m
E34b
R16m
R34b
R2c E2c E27c
E34b
12:t_vld R32m
proc
11:t_predict
R2c
E2c
E27c
E34b
E32m
E30c
E34b
E30c
E34b
W2c
E32m
E32m
W27c
W34b
W30m
W6m
W32m
W2c W32m
W30c
W34b
W2c W32m
W30c
W34b
R2c
R32m
R30c
R34b
E2c W2cW30c
E30c
E34b
E32m
W34b
W32m
W6m
7:t_memory
6:t_decMV
R30c
R34b
R32m
E2c
Body-Function
Exec Delay
On Memory “32”
W2c W30m
W27c
W34b
W32m
E2c
R2c R30c
R34b
R32m
9:t_add
8:t_writeMB
E32m
R2c R27c
R32m
R34b
10:t_idct
IO-(Read Trans.)
Exec Delay
On CPU
“2”
E32m
W2c W32m
W30c
W34b
R2c R32m
R34b
W2c
W27m
W34b
W30m
W32m
R2c
R27m
R32m
R34b
E2c
E34b
E32mW2c
W32m
W34b
E16c
5:in_es W34b
Body-Function
Execution Delay
On CPU “2”
IO- (Write Trans.)
Execution Delay
On CPU “2”
R25c
R34b
R2c
4:drop_finfo R32m
R34b
R2c
3:ofileproc R32m
0,00E+00
5,00E-02
1,00E-01
1,50E-01
2,00E-01
2,50E-01
AvgOfactualDelay
3,00E-01
3,50E-01
4,00E-01
R2c
R25c
R27c
R30c
R34b
R16m
R27m
R30m
R32m
E2c
E16c
E27c
E30c
E34b
E32m
W2c
W27c
W30c
W34b
W6m
W25m
W27m
W30m
W32m
Communication Analyst
map_FAKIR_Diagrams.MPEG_VIPER_S1
YAPI Transactions - Write - Number of bytes per channel per frame
4,00E+06
3,50E+06
3,00E+06
nbByte
2,50E+06
2,00E+06
1,50E+06
1,00E+06
5,00E+05
0,00E+00
1
3
5
7
9
11
13
frameID
15
17
19
21
23
25
2
4
6
8
9
10
11
14
15
17
18
20
21
22
23
26
30
32
34
35
36
37
40
41
Communication Analyst
map_FAKIR_Diagrams.MPEG_VIPER_SH2
YAPI IO Rates - avg Actual versus avg Intrinsic (Byte/sec, log scale)
1,00E+11
1,00E+10
1,00E+09
AvgOfActualRate
1,00E+08
1,00E+07
1,00E+06
26Wr
17Wr
42Rd
27Wr
71Wr
71Rd
16Rd
47Wr
43Wr
11Wr
59Rd
11Rd
4Wr
10Rd
4Rd
59Wr
30Wr
22Wr
10Wr
45Rd
18Rd
56Rd
56Wr
14Rd
70Rd
50Rd
54Wr
26Rd
65Wr
42Wr
25Rd
17Rd
35Wr
33Rd
64Rd
37Rd
53Rd
3Rd
16Wr
40Rd
75Wr
12Wr
44Wr 30Rd
27Rd
18Wr
9Wr
54Rd
36Rd
46Wr
9Rd
45Wr
7Wr
2Wr
70Wr
47Rd
19Rd
2Rd
66Rd
66Wr
33Wr
14Wr
50Wr
64Wr
36Wr
25Wr
19Wr
53Wr
37Wr
44Rd
75Rd
62Wr
23Wr
65Rd
43Rd
40Wr
48Wr
1,00E+05
1,00E+04
48Rd
12Rd
23Rd
Very bad “performance”
compared to “intrinsic rate”;
Arbitration issue or… always
busy waiting for input?
1,00E+03
1,00E+02
YAPI.Rd
YAPI.Wr
62Rd
1,00E+01
1,00E+00
1,00E+05
1,00E+06
1,00E+07
1,00E+08
AvgOfIntraRate
1,00E+09
1,00E+10
Principal Component Analysis Characteristics
map_FAKIR_Diagrams.MPEG_VIPER_SH2 - Principal Component Analysis YAPI Application Level Communication
1
AvgOfnbItem
0,8
fifoDepth
Linked
characteristics
0,6
-- axe F2 (23 %) -->
0,4
AvgOfactualDelay
0,2
AvgOfnbTransaction
0
AvgOfPerf
-0,2
itemSize
-0,4
-0,6
Opposed
characteristics
-0,8
-1
-1
-0,8
-0,6
-0,4
-0,2
0
0,2
-- axe F1 (34 %) -->
0,4
0,6
0,8
1
Principal Component Analysis Results on 108 Communication
Channelsmap_FAKIR_Diagrams.MPEG_VIPER_SH2 - Principal Component Analysis
-
YAPI Application Level Communication
11Rd.VHH1
11Wr.VHH1
0,9
AvgOfnbItem
fifoDepth
0,7
42Wr.YHHP
54Rd.YHH1
26Rd.YHHP
59Rd.YHH1
54Wr.YHH1
59Wr.YHH1
42Rd.YHHP
26Wr.YHHP
4Rd.VHH1
10Rd.VHH1
4Wr.VHH1
10Wr.VHH1
-- axe F2 (23 %) -->
0,5
0,3
AvgOfactualDelay
0,1
-0,1
AvgOfnbTransaction
40Wr.VHH1
65Rd.YHH1
43Rd.YHHP
16Wr.YHHP
12Rd.VHH1
36Wr.YHS1
23Rd.YHS1
62Rd.YHSP75Rd.YHH1
19Wr.YSH1
35Wr.YHH1
44Wr.YHS1
75Wr.YHH1
48Rd.YSH1
40Rd.VHH1
65Wr.YHH1
71Rd.YHHP
71Wr.YHHP
16Rd.YHHP
19Rd.YSH1
47Rd.YHS1
9Wr.VHH1
45Rd.YSH1
45Wr.YSH1
2Wr.VHH1
46Wr.YHH1
43Wr.YHHP
64Rd.YSH1
47Wr.YHS1
9Rd.VHH1
36Rd.YHS1
53Rd.YSH1
37Rd.YSH1
12Wr.VHH1
2Rd.VHH1
25Rd.YSH1
7Wr.YHH1
70Rd.YSH1
14Rd.YSH1
66Rd.YSS1
50Rd.YSH1
53Wr.YSH1
23Wr.YHS1
66Wr.YSS1
70Wr.YSH1
33Rd.YSH1
44Rd.YHS1
48Wr.YSH1
37Wr.YSH1
62Wr.YHSP
27Rd.YHSP
64Wr.YSH1
25Wr.YSH1
50Wr.YSH1
14Wr.YSH1
33Wr.YSH1
27Wr.YHSP
30Rd.YHH1
17Rd.YHHP
3Rd.VHH1
18Rd.YSH1
56Rd.YHH1
18Wr.YSH1
AvgOfPerf
56Wr.YHH1
17Wr.YHHP
22Wr.YHHP
30Wr.YHH1
-0,3
itemSize
-0,5
-0,9
-0,7
-0,5
-0,3
-0,1
0,1
-- axe F1 (34 %) -->
0,3
0,5
0,7
0,9
Clustering into Communication Port Classes
map_FAKIR_Diagrams.MPEG_VIPER_SH2 - Principal Component Analysis YAPI Application Level Communication
Class 1
4
11Rd.VHH1
11Wr.VHH1
Class 3
3
Class 2
42Wr.YHHP
54Rd.YHH1
-- axe F2 (23 %) -->
26Rd.YHHP
59Rd.YHH1
54Wr.YHH1
59Wr.YHH1
42Rd.YHHP
26Wr.YHHP
2
4Rd.VHH1
10Rd.VHH1
4Wr.VHH1
10Wr.VHH1
1
Class 4
40Wr.VHH1
65Rd.YHH1
43Rd.YHHP
16Wr.YHHP
12Rd.VHH1
36Wr.YHS1
23Rd.YHS1
62Rd.YHSP
0
30Rd.YHH1
17Rd.YHHP
56Rd.YHH1
-1
Class 5
-2
-4
-3
-2
75Rd.YHH1
19Wr.YSH1
35Wr.YHH1
44Wr.YHS175Wr.YHH1
48Rd.YSH1
40Rd.VHH1
65Wr.YHH1
16Rd.YHHP
19Rd.YSH1
47Rd.YHS1
71Rd.YHHP
45Rd.YSH1
45Wr.YSH1
2Wr.VHH1
46Wr.YHH1
71Wr.YHHP
43Wr.YHHP
64Rd.YSH1
47Wr.YHS1
36Rd.YHS1
9Wr.VHH1
53Rd.YSH1
37Rd.YSH1
12Wr.VHH1
9Rd.VHH1
2Rd.VHH1
25Rd.YSH1
14Rd.YSH1
50Rd.YSH1
53Wr.YSH1
23Wr.YHS1
44Rd.YHS1
33Rd.YSH1
7Wr.YHH1
70Rd.YSH1
48Wr.YSH1
37Wr.YSH1
66Rd.YSS1
62Wr.YHSP
27Rd.YHSP
64Wr.YSH1
25Wr.YSH1
50Wr.YSH1
14Wr.YSH1
33Wr.YSH1
27Wr.YHSP
66Wr.YSS1
70Wr.YSH1
3Rd.VHH1
18Rd.YSH1
18Wr.YSH1
56Wr.YHH1
17Wr.YHHP
22Wr.YHHP
30Wr.YHH1
-1
-- axe F1 (34 %) -->
0
1
2
Summary
• Talked about System-level SoC Design and changes in abstractions
• Discussed the VCC Design Flow as an example of FunctionArchitecture Co-Design, including the key concepts of:
– Performance Modeling
– Architectural Services
• Described two usage examples of function-architecture co-design,
illustrating the pragmatic use of these concepts by real design teams:
– Automotive Distributed SW
– Design Space Exploration of Multimedia platform
• As a result, I hope you are convinced of both the need for system level
design for SoC, and the real possibility of creating practical tools to
support it
• Next important step for such tools: a common standardised model
integration infrastructure based on SystemC